From 294879f6f258dad81334bb84470623eee09b1ddf Mon Sep 17 00:00:00 2001 From: rusefi Date: Fri, 8 Oct 2021 14:09:30 -0400 Subject: [PATCH] Button to apply nDBANK #2996 --- .../Data_Base/STM32_Prog_DB_0x451.xml | 725 ++++++++++++++++++ .../{ => bin}/Qt5Core.dll | Bin .../{ => bin}/Qt5SerialPort.dll | Bin .../STM32_Programmer_CLI/{ => bin}/Qt5Xml.dll | Bin .../{ => bin}/STM32_Programmer_CLI.exe | Bin .../{ => bin}/libgcc_s_seh-1.dll | Bin .../{ => bin}/libstdc++-6.dll | Bin .../{ => bin}/libwinpthread-1.dll | Bin .../STM32_Programmer_CLI/{ => bin}/zlib1.dll | Bin 9 files changed, 725 insertions(+) create mode 100644 misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x451.xml rename misc/install/STM32_Programmer_CLI/{ => bin}/Qt5Core.dll (100%) rename misc/install/STM32_Programmer_CLI/{ => bin}/Qt5SerialPort.dll (100%) rename misc/install/STM32_Programmer_CLI/{ => bin}/Qt5Xml.dll (100%) rename misc/install/STM32_Programmer_CLI/{ => bin}/STM32_Programmer_CLI.exe (100%) rename misc/install/STM32_Programmer_CLI/{ => bin}/libgcc_s_seh-1.dll (100%) rename misc/install/STM32_Programmer_CLI/{ => bin}/libstdc++-6.dll (100%) rename misc/install/STM32_Programmer_CLI/{ => bin}/libwinpthread-1.dll (100%) rename misc/install/STM32_Programmer_CLI/{ => bin}/zlib1.dll (100%) diff --git a/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x451.xml b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x451.xml new file mode 100644 index 0000000000..35fce476c5 --- /dev/null +++ b/misc/install/STM32_Programmer_CLI/Data_Base/STM32_Prog_DB_0x451.xml @@ -0,0 +1,725 @@ + + + + 0x451 + STMicroelectronics + MCU + Cortex-M7 + STM32F76x/STM32F77x + STM32F7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x20 + + + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + Single + 0x20 + + + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + + + + + + + + + + + + + ITCM Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + Single + 0x20 + + + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + + + + + + User Configuration + + + + + IWDG_STOP + + 0x1F + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0x1E + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + nDBANK + + 0x1D + 0x1 + RW + + Flash in dual bank with 128 bits read access + Flash in single bank with 256 bits read access + + + + nDBOOT + + 0x1C + 0x1 + RW + + Dual Boot enabled + Dual Boot disabled + + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x10 + 0x10 + RW + + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0xC + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP0 + + 0x10 + 0x6 + RW + + Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on bank1 sector 2i, 2i+1 + + + + nWRP6 + + 0x16 + 0x6 + RW + + Write protection active on bank2 sector 2i and 2i+1 + Write protection not active on bank2 sector 2i, 2i+1 + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + + + + + + User Configuration + + + + + IWDG_STOP + + 0xF + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0xE + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + nDBANK + + 0xD + 0x1 + RW + + Flash in dual bank with 128 bits read access + Flash in single bank with 256 bits read access + + + + nDBOOT + + 0xC + 0x1 + RW + + Dual Boot enabled + Dual Boot disabled + + + + + + + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + + + + + + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x0 + 0x10 + RW + + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0xC + RW + + Write protection active on this sector + Write protection not active on this sector + + + + nWRP0 + + 0x0 + 0x6 + RW + + Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on bank1 sector 2i, 2i+1 + + + + nWRP6 + + 0x6 + 0x6 + RW + + Write protection active on bank2 sector 2i and 2i+1 + Write protection not active on bank2 sector 2i, 2i+1 + + + + + + + + + + \ No newline at end of file diff --git a/misc/install/STM32_Programmer_CLI/Qt5Core.dll b/misc/install/STM32_Programmer_CLI/bin/Qt5Core.dll similarity index 100% rename from misc/install/STM32_Programmer_CLI/Qt5Core.dll rename to misc/install/STM32_Programmer_CLI/bin/Qt5Core.dll diff --git a/misc/install/STM32_Programmer_CLI/Qt5SerialPort.dll b/misc/install/STM32_Programmer_CLI/bin/Qt5SerialPort.dll similarity index 100% rename from misc/install/STM32_Programmer_CLI/Qt5SerialPort.dll rename to misc/install/STM32_Programmer_CLI/bin/Qt5SerialPort.dll diff --git a/misc/install/STM32_Programmer_CLI/Qt5Xml.dll b/misc/install/STM32_Programmer_CLI/bin/Qt5Xml.dll similarity index 100% rename from misc/install/STM32_Programmer_CLI/Qt5Xml.dll rename to misc/install/STM32_Programmer_CLI/bin/Qt5Xml.dll diff --git a/misc/install/STM32_Programmer_CLI/STM32_Programmer_CLI.exe b/misc/install/STM32_Programmer_CLI/bin/STM32_Programmer_CLI.exe similarity index 100% rename from misc/install/STM32_Programmer_CLI/STM32_Programmer_CLI.exe rename to misc/install/STM32_Programmer_CLI/bin/STM32_Programmer_CLI.exe diff --git a/misc/install/STM32_Programmer_CLI/libgcc_s_seh-1.dll b/misc/install/STM32_Programmer_CLI/bin/libgcc_s_seh-1.dll similarity index 100% rename from misc/install/STM32_Programmer_CLI/libgcc_s_seh-1.dll rename to misc/install/STM32_Programmer_CLI/bin/libgcc_s_seh-1.dll diff --git a/misc/install/STM32_Programmer_CLI/libstdc++-6.dll b/misc/install/STM32_Programmer_CLI/bin/libstdc++-6.dll similarity index 100% rename from misc/install/STM32_Programmer_CLI/libstdc++-6.dll rename to misc/install/STM32_Programmer_CLI/bin/libstdc++-6.dll diff --git a/misc/install/STM32_Programmer_CLI/libwinpthread-1.dll b/misc/install/STM32_Programmer_CLI/bin/libwinpthread-1.dll similarity index 100% rename from misc/install/STM32_Programmer_CLI/libwinpthread-1.dll rename to misc/install/STM32_Programmer_CLI/bin/libwinpthread-1.dll diff --git a/misc/install/STM32_Programmer_CLI/zlib1.dll b/misc/install/STM32_Programmer_CLI/bin/zlib1.dll similarity index 100% rename from misc/install/STM32_Programmer_CLI/zlib1.dll rename to misc/install/STM32_Programmer_CLI/bin/zlib1.dll