From 5d7a30ce2b79a9ad370d322a16333157dd7627fb Mon Sep 17 00:00:00 2001 From: Matthew Kennedy Date: Wed, 22 Feb 2023 14:53:31 -0800 Subject: [PATCH] no qc --- .github/workflows/build-firmware.yaml | 23 - firmware/config/boards/f429-208/board.c | 422 ----- firmware/config/boards/f429-208/board.h | 1430 ----------------- firmware/config/boards/f429-208/board.mk | 24 - .../boards/f429-208/board_configuration.cpp | 20 - .../boards/f429-208/compile_f429-208.sh | 5 - firmware/config/boards/f429-208/prepend.txt | 0 .../hellen88bmw/compile_hellen88bmw_avr.sh | 12 - ...mpile_mre_f4_hardware_QC_special_build.bat | 2 - .../microrusefi/board_configuration.cpp | 5 - ...ompile_mre_f4_hardware_QC_special_build.sh | 26 - .../boards/proteus/board_configuration.cpp | 10 - ...le_proteus_f4_hardware_QC_special_build.sh | 9 - ...le_proteus_f7_hardware_QC_special_build.sh | 9 - firmware/config/boards/readme.md | 4 - firmware/console/binary/tunerstudio.cpp | 6 - firmware/console/status_loop.cpp | 20 - firmware/controllers/algo/engine.cpp | 34 - .../engine_cycle/main_trigger_callback.cpp | 2 - firmware/controllers/flash_main.cpp | 14 - .../controllers/trigger/trigger_central.cpp | 32 - firmware/rusefi.cpp | 6 - .../compile_and_upload.bat | 3 - misc/jenkins/compile_other_versions/run.bat | 97 -- simulator/simulator/efifeatures.h | 2 - 25 files changed, 2217 deletions(-) delete mode 100644 firmware/config/boards/f429-208/board.c delete mode 100644 firmware/config/boards/f429-208/board.h delete mode 100644 firmware/config/boards/f429-208/board.mk delete mode 100644 firmware/config/boards/f429-208/board_configuration.cpp delete mode 100755 firmware/config/boards/f429-208/compile_f429-208.sh delete mode 100644 firmware/config/boards/f429-208/prepend.txt delete mode 100644 firmware/config/boards/hellen/hellen88bmw/compile_hellen88bmw_avr.sh delete mode 100644 firmware/config/boards/microrusefi/!compile_mre_f4_hardware_QC_special_build.bat delete mode 100755 firmware/config/boards/microrusefi/compile_mre_f4_hardware_QC_special_build.sh delete mode 100755 firmware/config/boards/proteus/compile_proteus_f4_hardware_QC_special_build.sh delete mode 100755 firmware/config/boards/proteus/compile_proteus_f7_hardware_QC_special_build.sh delete mode 100644 misc/jenkins/compile_other_versions/compile_and_upload.bat delete mode 100644 misc/jenkins/compile_other_versions/run.bat diff --git a/.github/workflows/build-firmware.yaml b/.github/workflows/build-firmware.yaml index e24d433cf6..db0ac968a7 100644 --- a/.github/workflows/build-firmware.yaml +++ b/.github/workflows/build-firmware.yaml @@ -20,9 +20,6 @@ jobs: # What boards should we build for? In the 'include' section below, # set up what each of these boards needs to build. # - # see also gen_config where we have a similar list for all boards! - # see also build-primary-bundle where default/primary bundle is build separately - # # build-target: [ # alphax-2chan, # alphax-4chan, @@ -31,7 +28,6 @@ jobs: # hellen72, # hellen81, # hellen88bmw, - # hellen88bmw_avr, # hellen-nb1, # hellen-gm-e67, # hellenNA8_96, @@ -45,14 +41,11 @@ jobs: # mre_f4_no_openblt, # mre_f4_debug, # mre_f4_recovery, - # mre_f4_hardware_QC_special_build, # mre_f7, # prometheus_405, # prometheus_469, # proteus_f4, - # proteus_f4_hardware_QC_special_build, # proteus_f7, - # proteus_f7_hardware_QC_special_build, # proteus_h7, # proteus_legacy, # stm32f429_nucleo, @@ -97,10 +90,6 @@ jobs: # folder: config/boards/hellen/hellen88bmw # ini-file: fome_hellen88bmw.ini - # - build-target: hellen88bmw_avr - # folder: config/boards/hellen/hellen88bmw - # ini-file: fome_hellen88bmw.ini - - build-target: hellen-nb1 folder: config/boards/hellen/hellen-nb1 ini-file: fome_hellen-nb1.ini @@ -157,10 +146,6 @@ jobs: # folder: config/boards/microrusefi # ini-file: fome_mre_f4.ini - # - build-target: mre_f4_hardware_QC_special_build - # folder: config/boards/microrusefi - # ini-file: fome_mre_f4.ini - # - build-target: mre_f7 # folder: config/boards/microrusefi # ini-file: fome_mre_f7.ini @@ -177,18 +162,10 @@ jobs: folder: config/boards/proteus ini-file: fome_proteus_f4.ini - # - build-target: proteus_f4_hardware_QC_special_build - # folder: config/boards/proteus - # ini-file: fome_proteus_f4.ini - - build-target: proteus_f7 folder: config/boards/proteus ini-file: fome_proteus_f7.ini - # - build-target: proteus_f7_hardware_QC_special_build - # folder: config/boards/proteus - # ini-file: fome_proteus_f7.ini - # - build-target: proteus_h7 # folder: config/boards/proteus # ini-file: fome_proteus_h7.ini diff --git a/firmware/config/boards/f429-208/board.c b/firmware/config/boards/f429-208/board.c deleted file mode 100644 index 05dc8b37f2..0000000000 --- a/firmware/config/boards/f429-208/board.c +++ /dev/null @@ -1,422 +0,0 @@ -/** - * @file boards/f429-208/board.c - * - * @date Oct 14, 2022 - * @author Andrey Gusakov, 2022 - */ - -#include "hal.h" -#include "hal_community.h" -#include "hal_sdram_lld.h" -/* for UNUSED() */ -#include "efilib.h" - -#include "board.h" - -/* - * SDRAM driver configuration structure. - */ -static const SDRAMConfig sdram_cfg = { - .sdcr = (uint32_t) (FMC_ColumnBits_Number_8b | - FMC_RowBits_Number_12b | - FMC_SDMemory_Width_16b | - FMC_InternalBank_Number_4 | - FMC_CAS_Latency_3 | - FMC_Write_Protection_Disable | - FMC_SDClock_Period_2 | - FMC_Read_Burst_Disable | - FMC_ReadPipe_Delay_1), - - .sdtr = (uint32_t)( (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) - (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns)) - (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) - (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns)) - (2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns)) - (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns) - (2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) - - .sdcmr = (uint32_t)(((4 - 1) << 5) | - ((FMC_SDCMR_MRD_BURST_LENGTH_2 | - FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | - FMC_SDCMR_MRD_CAS_LATENCY_3 | - FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | - FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)), - - /* if (STM32_SYSCLK == 180000000) -> - 64ms / 4096 = 15.625us - 15.625us * 90MHz = 1406 - 20 = 1386 */ - //.sdrtr = (1386 << 1), - .sdrtr = (uint32_t)(683 << 1), -}; - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Type of STM32 GPIO port setup. - */ -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t odr; - uint32_t afrl; - uint32_t afrh; -} gpio_setup_t; - -/** - * @brief Type of STM32 GPIO initialization data. - */ -typedef struct { -#if STM32_HAS_GPIOA || defined(__DOXYGEN__) - gpio_setup_t PAData; -#endif -#if STM32_HAS_GPIOB || defined(__DOXYGEN__) - gpio_setup_t PBData; -#endif -#if STM32_HAS_GPIOC || defined(__DOXYGEN__) - gpio_setup_t PCData; -#endif -#if STM32_HAS_GPIOD || defined(__DOXYGEN__) - gpio_setup_t PDData; -#endif -#if STM32_HAS_GPIOE || defined(__DOXYGEN__) - gpio_setup_t PEData; -#endif -#if STM32_HAS_GPIOF || defined(__DOXYGEN__) - gpio_setup_t PFData; -#endif -#if STM32_HAS_GPIOG || defined(__DOXYGEN__) - gpio_setup_t PGData; -#endif -#if STM32_HAS_GPIOH || defined(__DOXYGEN__) - gpio_setup_t PHData; -#endif -#if STM32_HAS_GPIOI || defined(__DOXYGEN__) - gpio_setup_t PIData; -#endif -#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_setup_t PJData; -#endif -#if STM32_HAS_GPIOK || defined(__DOXYGEN__) - gpio_setup_t PKData; -#endif -} gpio_config_t; - -/** - * @brief STM32 GPIO static initialization data. - */ -static const gpio_config_t gpio_default_config = { -#if STM32_HAS_GPIOA - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, -#endif -#if STM32_HAS_GPIOB - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, -#endif -#if STM32_HAS_GPIOC - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, -#endif -#if STM32_HAS_GPIOD - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, -#endif -#if STM32_HAS_GPIOE - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, -#endif -#if STM32_HAS_GPIOF - {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, -#endif -#if STM32_HAS_GPIOG - {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, -#endif -#if STM32_HAS_GPIOH - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, -#endif -#if STM32_HAS_GPIOI - {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, -#endif -#if STM32_HAS_GPIOJ - {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, -#endif -#if STM32_HAS_GPIOK - {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { - - gpiop->OTYPER = config->otyper; - gpiop->OSPEEDR = config->ospeedr; - gpiop->PUPDR = config->pupdr; - gpiop->ODR = config->odr; - gpiop->AFRL = config->afrl; - gpiop->AFRH = config->afrh; - gpiop->MODER = config->moder; -} - -static void stm32_gpio_init(void) { - - /* Enabling GPIO-related clocks, the mask comes from the - registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); - - /* Initializing all the defined GPIO ports.*/ -#if STM32_HAS_GPIOA - gpio_init(GPIOA, &gpio_default_config.PAData); -#endif -#if STM32_HAS_GPIOB - gpio_init(GPIOB, &gpio_default_config.PBData); -#endif -#if STM32_HAS_GPIOC - gpio_init(GPIOC, &gpio_default_config.PCData); -#endif -#if STM32_HAS_GPIOD - gpio_init(GPIOD, &gpio_default_config.PDData); -#endif -#if STM32_HAS_GPIOE - gpio_init(GPIOE, &gpio_default_config.PEData); -#endif -#if STM32_HAS_GPIOF - gpio_init(GPIOF, &gpio_default_config.PFData); -#endif -#if STM32_HAS_GPIOG - gpio_init(GPIOG, &gpio_default_config.PGData); -#endif -#if STM32_HAS_GPIOH - gpio_init(GPIOH, &gpio_default_config.PHData); -#endif -#if STM32_HAS_GPIOI - gpio_init(GPIOI, &gpio_default_config.PIData); -#endif -#if STM32_HAS_GPIOJ - gpio_init(GPIOJ, &gpio_default_config.PJData); -#endif -#if STM32_HAS_GPIOK - gpio_init(GPIOK, &gpio_default_config.PKData); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -#define SDRAM ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE) - -/** - * FMC_Command_Mode - */ -#define FMCCM_NORMAL ((uint32_t)0x00000000) -#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) -#define FMCCM_PALL ((uint32_t)0x00000002) -#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) -#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) -#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) -#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) - -static void __early_sdram_wait_ready(void) { - /* Wait until the SDRAM controller is ready */ - while (SDRAM->SDSR & FMC_SDSR_BUSY); -} - -static void __early_sdram_delay(void) -{ - /* something > 100uS */ - volatile int tmp = 168 * 1000 * 100; - - do { - tmp--; - } while(tmp); -} - -static void __early_sdram_init(const SDRAMConfig *config) -{ - uint32_t command_target = 0; - - #ifdef rccResetFSMC - rccResetFSMC(); - #endif - rccEnableFSMC(FALSE); - - SDRAM->SDCR1 = config->sdcr; - SDRAM->SDTR1 = config->sdtr; - SDRAM->SDCR2 = config->sdcr; - SDRAM->SDTR2 = config->sdtr; - -#if STM32_SDRAM_USE_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_SDRAM_USE_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - /* Step 3: Configure a clock configuration enable command.*/ - __early_sdram_wait_ready(); - SDRAM->SDCMR = FMCCM_CLK_ENABLED | command_target; - - /* Step 4: Insert delay (tipically 100uS).*/ - __early_sdram_delay(); - - /* Step 5: Configure a PALL (precharge all) command.*/ - __early_sdram_wait_ready(); - SDRAM->SDCMR = FMCCM_PALL | command_target; - - /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ - __early_sdram_wait_ready(); - SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (config->sdcmr & FMC_SDCMR_NRFS); - - /* Step 6.2: Send the second command.*/ - __early_sdram_wait_ready(); - SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (config->sdcmr & FMC_SDCMR_NRFS); - - /* Step 7: Program the external memory mode register.*/ - __early_sdram_wait_ready(); - SDRAM->SDCMR = FMCCM_LOAD_MODE | command_target | - (config->sdcmr & FMC_SDCMR_MRD); - - /* Step 8: Set clock.*/ - __early_sdram_wait_ready(); - SDRAM->SDRTR = config->sdrtr & FMC_SDRTR_COUNT; - - __early_sdram_wait_ready(); -} - -static int __early_sdram_test(void *base, size_t size) -{ - size_t i; - uint32_t *ptr = base; - - /* test 0 */ - for (i = 0; i < size / sizeof(uint32_t); i++) { - ptr[i] = 0; - } - - for (i = 0; i < size / sizeof(uint32_t); i++) { - if (ptr[i] != 0) - return -1; - } - - /* test 1 */ - for (i = 0; i < size / sizeof(uint32_t); i++) { - ptr[i] = 0xffffffff; - } - - for (i = 0; i < size / sizeof(uint32_t); i++) { - if (ptr[i] != 0xffffffff) - return -1; - } - - /* test 2 */ - for (i = 0; i < size / sizeof(uint32_t); i++) { - ptr[i] = i; - } - - for (i = 0; i < size / sizeof(uint32_t); i++) { - if (ptr[i] != i) - return -1; - } - - return 0; -} - -/** - * @brief Early initialization code. - * @details GPIO ports and system clocks are initialized before everything - * else. - */ -void __early_init(void) { - - stm32_gpio_init(); - stm32_clock_init(); - - /* - * Initialise FSMC for SDRAM. - */ -#if 0 - /* clear driver struct */ - memset(&SDRAMD1, 0 sizeof(SDRAMD1)); - sdramInit(); - sdramStart(&SDRAMD1, &sdram_cfg); -#else - __early_sdram_init(&sdram_cfg); -#endif - - if (1) { - /* yes, hardcoded values */ - __early_sdram_test((void *) 0xD0000000, 8 * 1024 * 1024); - } -} - -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) -{ - UNUSED(sdcp); - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) -{ - UNUSED(sdcp); - /* TODO: Fill the implementation.*/ - return false; -} -#endif /* HAL_USE_SDC */ - -#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) -/** - * @brief MMC_SPI card detection. - */ -bool mmc_lld_is_card_inserted(MMCDriver *mmcp) -{ - UNUSED(mmcp); - /* TODO: Fill the implementation.*/ - return true; -} - -/** - * @brief MMC_SPI card write protection detection. - */ -bool mmc_lld_is_write_protected(MMCDriver *mmcp) -{ - UNUSED(mmcp); - /* TODO: Fill the implementation.*/ - return false; -} -#endif diff --git a/firmware/config/boards/f429-208/board.h b/firmware/config/boards/f429-208/board.h deleted file mode 100644 index dc050d7638..0000000000 --- a/firmware/config/boards/f429-208/board.h +++ /dev/null @@ -1,1430 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * This file has been automatically generated using ChibiStudio board - * generator plugin. Do not edit manually. - */ - -#ifndef BOARD_H -#define BOARD_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * Setup for RusEFI STM32F429-208 board. - */ - -/* - * Board identifier. - */ -#define BOARD_ST_STM32F429I_DISCOVERY -#define BOARD_NAME "RusEFI STM32F429-208" - -/* - * USB settings - */ -#define EFI_USB_AF 10U -//#define EFI_USB_SERIAL_ID Gpio::A10 -#define EFI_USB_SERIAL_DM Gpio::A11 -#define EFI_USB_SERIAL_DP Gpio::A12 - -/* - * Board oscillators-related settings. - * NOTE: LSE not fitted. - */ -#if !defined(STM32_LSECLK) -#define STM32_LSECLK 0U -#endif - -//#if !defined(STM32_HSECLK) -//#define STM32_HSECLK 20000000U -//#endif - -/* - * Board voltages. - * Required for performance limits calculation. - */ -#define STM32_VDD 300U - -/* - * MCU type as defined in the ST header. - */ -#ifndef STM32F429xx - #define STM32F429xx -#endif - -/* - * IO pins assignments. - */ -#define GPIOA_BUTTON 0U -#define GPIOA_MEMS_INT1 1U -#define GPIOA_MEMS_INT2 2U -#define GPIOA_LCD_B5 3U -#define GPIOA_LCD_VSYNC 4U -#define GPIOA_PIN5 5U -#define GPIOA_LCD_G2 6U -#define GPIOA_ACP_RST 7U -#define GPIOA_I2C3_SCL 8U -#define GPIOA_UART_TX 9U -#define GPIOA_OTG_FS_ID 10U -#define GPIOA_OTG_FS_DM 11U -#define GPIOA_OTG_FS_DP 12U -#define GPIOA_SWDIO 13U -#define GPIOA_SWCLK 14U -#define GPIOA_TP_INT 15U - -#define GPIOB_LCD_R3 0U -#define GPIOB_LCD_R6 1U -#define GPIOB_BOOT1 2U -#define GPIOB_SWO 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U -#define GPIOB_PIN6 6U -#define GPIOB_PIN7 7U -#define GPIOB_LCD_B6 8U -#define GPIOB_LCD_B7 9U -#define GPIOB_LCD_G4 10U -#define GPIOB_LED1 11U -#define GPIOB_OTG_HS_ID 12U -#define GPIOB_OTG_HS_VBUS 13U -#define GPIOB_OTG_HS_DM 14U -#define GPIOB_OTG_HS_DP 15U - -#define GPIOC_FMC_SDNWE 0U -#define GPIOC_SPI5_MEMS_CS 1U -#define GPIOC_SPI5_LCD_CS 2U -#define GPIOC_PIN3 3U -#define GPIOC_OTG_HS_PSO 4U -#define GPIOC_OTG_HS_OC 5U -#define GPIOC_LCD_HSYNC 6U -#define GPIOC_LCD_G6 7U -#define GPIOC_PIN8 8U -#define GPIOC_I2C3_SDA 9U -#define GPIOC_LCD_R2 10U -#define GPIOC_PIN11 11U -#define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_OSC32_IN 14U -#define GPIOC_OSC32_OUT 15U - -#define GPIOD_FMC_D2 0U -#define GPIOD_FMC_D3 1U -#define GPIOD_PIN2 2U -#define GPIOD_LCD_G7 3U -#define GPIOD_PIN4 4U -#define GPIOD_PIN5 5U -#define GPIOD_LCD_B2 6U -#define GPIOD_PIN7 7U -#define GPIOD_FMC_D13 8U -#define GPIOD_FMC_D14 9U -#define GPIOD_FMC_D15 10U -#define GPIOD_LCD_TE 11U -#define GPIOD_LCD_RDX 12U -#define GPIOD_LCD_WRX 13U -#define GPIOD_FMC_D0 14U -#define GPIOD_FMC_D1 15U - -#define GPIOE_FMC_NBL0 0U -#define GPIOE_FMC_NBL1 1U -#define GPIOE_PIN2 2U -#define GPIOE_PIN3 3U -#define GPIOE_PIN4 4U -#define GPIOE_PIN5 5U -#define GPIOE_PIN6 6U -#define GPIOE_FMC_D4 7U -#define GPIOE_FMC_D5 8U -#define GPIOE_FMC_D6 9U -#define GPIOE_FMC_D7 10U -#define GPIOE_FMC_D8 11U -#define GPIOE_FMC_D9 12U -#define GPIOE_FMC_D10 13U -#define GPIOE_FMC_D11 14U -#define GPIOE_FMC_D12 15U - -#define GPIOF_FMC_A0 0U -#define GPIOF_FMC_A1 1U -#define GPIOF_FMC_A2 2U -#define GPIOF_FMC_A3 3U -#define GPIOF_FMC_A4 4U -#define GPIOF_FMC_A5 5U -#define GPIOF_PIN6 6U -#define GPIOF_LCD_DCX 7U -#define GPIOF_SPI5_MISO 8U -#define GPIOF_SPI5_MOSI 9U -#define GPIOF_LCD_DE 10U -#define GPIOF_FMC_SDNRAS 11U -#define GPIOF_FMC_A6 12U -#define GPIOF_FMC_A7 13U -#define GPIOF_FMC_A8 14U -#define GPIOF_FMC_A9 15U - -#define GPIOG_FMC_A10 0U -#define GPIOG_FMC_A11 1U -#define GPIOG_PIN2 2U -#define GPIOG_PIN3 3U -#define GPIOG_FMC_BA0 4U -#define GPIOG_FMC_BA1 5U -#define GPIOG_LCD_R7 6U -#define GPIOG_LCD_CLK 7U -#define GPIOG_FMC_SDCLK 8U -#define GPIOG_PIN9 9U -#define GPIOG_LCD_G3 10U -#define GPIOG_LCD_B3 11U -#define GPIOG_LCD_B4 12U -#define GPIOG_LED3_GREEN 13U -#define GPIOG_LED4_RED 14U -#define GPIOG_FMC_SDNCAS 15U - -#define GPIOH_OSC_IN 0U -#define GPIOH_OSC_OUT 1U -#define GPIOH_PIN2 2U -#define GPIOH_PIN3 3U -#define GPIOH_PIN4 4U -#define GPIOH_FMC_SDNWE 5U -#define GPIOH_FMC_SDNE1 6U -#define GPIOH_FMC_SDCKE1 7U -#define GPIOH_PIN8 8U -#define GPIOH_PIN9 9U -#define GPIOH_PIN10 10U -#define GPIOH_PIN11 11U -#define GPIOH_PIN12 12U -#define GPIOH_PIN13 13U -#define GPIOH_PIN14 14U -#define GPIOH_PIN15 15U - -#define GPIOI_PIN0 0U -#define GPIOI_PIN1 1U -#define GPIOI_PIN2 2U -#define GPIOI_PIN3 3U -#define GPIOI_PIN4 4U -#define GPIOI_PIN5 5U -#define GPIOI_PIN6 6U -#define GPIOI_PIN7 7U -#define GPIOI_PIN8 8U -#define GPIOI_PIN9 9U -#define GPIOI_PIN10 10U -#define GPIOI_PIN11 11U -#define GPIOI_PIN12 12U -#define GPIOI_PIN13 13U -#define GPIOI_PIN14 14U -#define GPIOI_PIN15 15U - -/* - * IO lines assignments. - */ -#define LINE_BUTTON PAL_LINE(GPIOA, 0U) -#define LINE_MEMS_INT1 PAL_LINE(GPIOA, 1U) -#define LINE_MEMS_INT2 PAL_LINE(GPIOA, 2U) -#define LINE_LCD_B5 PAL_LINE(GPIOA, 3U) -#define LINE_LCD_VSYNC PAL_LINE(GPIOA, 4U) -#define LINE_LCD_G2 PAL_LINE(GPIOA, 6U) -#define LINE_ACP_RST PAL_LINE(GPIOA, 7U) -#define LINE_I2C3_SCL PAL_LINE(GPIOA, 8U) -#define LINE_UART_TX PAL_LINE(GPIOA, 9U) -#define LINE_UART_RX PAL_LINE(GPIOA, 10U) -#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) -#define LINE_OTF_FS_DP PAL_LINE(GPIOA, 12U) -#define LINE_SWDIO PAL_LINE(GPIOA, 13U) -#define LINE_SWCLK PAL_LINE(GPIOA, 14U) -#define LINE_TP_INT PAL_LINE(GPIOA, 15U) -#define LINE_LCD_R3 PAL_LINE(GPIOB, 0U) -#define LINE_LCD_R6 PAL_LINE(GPIOB, 1U) -#define LINE_BOOT1 PAL_LINE(GPIOB, 2U) -#define LINE_SWO PAL_LINE(GPIOB, 3U) -#define LINE_FMC_SDCKE1 PAL_LINE(GPIOH, 7U) -#define LINE_FMC_SDNE1 PAL_LINE(GPIOH, 6U) -#define LINE_LCD_B6 PAL_LINE(GPIOB, 8U) -#define LINE_LCD_B7 PAL_LINE(GPIOB, 9U) -#define LINE_LCD_G4 PAL_LINE(GPIOB, 10U) -#define LINE_LCD_G5 PAL_LINE(GPIOB, 11U) -#define LINE_OTG_HS_ID PAL_LINE(GPIOB, 12U) -#define LINE_OTG_HS_VBUS PAL_LINE(GPIOB, 13U) -#define LINE_OTG_HS_DM PAL_LINE(GPIOB, 14U) -#define LINE_OTG_HS_DP PAL_LINE(GPIOB, 15U) -#define LINE_FMC_SDNWE PAL_LINE(GPIOH, 5U) -#define LINE_SPI5_MEMS_CS PAL_LINE(GPIOC, 1U) -#define LINE_SPI5_LCD_CS PAL_LINE(GPIOC, 2U) -#define LINE_OTG_HS_PSO PAL_LINE(GPIOC, 4U) -#define LINE_OTG_HS_OC PAL_LINE(GPIOC, 5U) -#define LINE_LCD_HSYNC PAL_LINE(GPIOC, 6U) -#define LINE_LCD_G6 PAL_LINE(GPIOC, 7U) -#define LINE_I2C3_SDA PAL_LINE(GPIOC, 9U) -#define LINE_LCD_R2 PAL_LINE(GPIOC, 10U) -#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) -#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) -#define LINE_FMC_D2 PAL_LINE(GPIOD, 0U) -#define LINE_FMC_D3 PAL_LINE(GPIOD, 1U) -#define LINE_LCD_G7 PAL_LINE(GPIOD, 3U) -#define LINE_LCD_B2 PAL_LINE(GPIOD, 6U) -#define LINE_FMC_D13 PAL_LINE(GPIOD, 8U) -#define LINE_FMC_D14 PAL_LINE(GPIOD, 9U) -#define LINE_FMC_D15 PAL_LINE(GPIOD, 10U) -#define LINE_LCD_TE PAL_LINE(GPIOD, 11U) -#define LINE_LCD_RDX PAL_LINE(GPIOD, 12U) -#define LINE_LCD_WRX PAL_LINE(GPIOD, 13U) -#define LINE_FMC_D0 PAL_LINE(GPIOD, 14U) -#define LINE_FMC_D1 PAL_LINE(GPIOD, 15U) -#define LINE_FMC_NBL0 PAL_LINE(GPIOE, 0U) -#define LINE_FMC_NBL1 PAL_LINE(GPIOE, 1U) -#define LINE_FMC_D4 PAL_LINE(GPIOE, 7U) -#define LINE_FMC_D5 PAL_LINE(GPIOE, 8U) -#define LINE_FMC_D6 PAL_LINE(GPIOE, 9U) -#define LINE_FMC_D7 PAL_LINE(GPIOE, 10U) -#define LINE_FMC_D8 PAL_LINE(GPIOE, 11U) -#define LINE_FMC_D9 PAL_LINE(GPIOE, 12U) -#define LINE_FMC_D10 PAL_LINE(GPIOE, 13U) -#define LINE_FMC_D11 PAL_LINE(GPIOE, 14U) -#define LINE_FMC_D12 PAL_LINE(GPIOE, 15U) -#define LINE_FMC_A0 PAL_LINE(GPIOF, 0U) -#define LINE_FMC_A1 PAL_LINE(GPIOF, 1U) -#define LINE_FMC_A2 PAL_LINE(GPIOF, 2U) -#define LINE_FMC_A3 PAL_LINE(GPIOF, 3U) -#define LINE_FMC_A4 PAL_LINE(GPIOF, 4U) -#define LINE_FMC_A5 PAL_LINE(GPIOF, 5U) -#define LINE_LCD_DCX PAL_LINE(GPIOF, 7U) -#define LINE_SPI5_MISO PAL_LINE(GPIOF, 8U) -#define LINE_SPI5_MOSI PAL_LINE(GPIOF, 9U) -#define LINE_LCD_DE PAL_LINE(GPIOF, 10U) -#define LINE_FMC_SDNRAS PAL_LINE(GPIOF, 11U) -#define LINE_FMC_A6 PAL_LINE(GPIOF, 12U) -#define LINE_FMC_A7 PAL_LINE(GPIOF, 13U) -#define LINE_FMC_A8 PAL_LINE(GPIOF, 14U) -#define LINE_FMC_A9 PAL_LINE(GPIOF, 15U) -#define LINE_FMC_A10 PAL_LINE(GPIOG, 0U) -#define LINE_FMC_A11 PAL_LINE(GPIOG, 1U) -#define LINE_FMC_BA0 PAL_LINE(GPIOG, 4U) -#define LINE_FMC_BA1 PAL_LINE(GPIOG, 5U) -#define LINE_LCD_R7 PAL_LINE(GPIOG, 6U) -#define LINE_LCD_CLK PAL_LINE(GPIOG, 7U) -#define LINE_FMC_SDCLK PAL_LINE(GPIOG, 8U) -#define LINE_LCD_G3 PAL_LINE(GPIOG, 10U) -#define LINE_LCD_B3 PAL_LINE(GPIOG, 11U) -#define LINE_LCD_B4 PAL_LINE(GPIOG, 12U) -#define LINE_LED3_GREEN PAL_LINE(GPIOG, 13U) -#define LINE_LED4_RED PAL_LINE(GPIOG, 14U) -#define LINE_FMC_SDNCAS PAL_LINE(GPIOG, 15U) -#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) -#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/* - * I/O ports initial setup, this configuration is established soon after reset - * in the initialization code. - * Please refer to the STM32 Reference Manual for details. - */ -#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) -#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) -#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) -#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) -#define PIN_ODR_LOW(n) (0U << (n)) -#define PIN_ODR_HIGH(n) (1U << (n)) -#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) -#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) -#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) -#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) -#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) -#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) -#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) -#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) -#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) -#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) - -/* - * GPIOA setup: - * - * PA0 - BUTTON (input floating). - * PA1 - MEMS_INT1 (input floating). - * PA2 - MEMS_INT2 (input floating). - * PA3 - LCD_B5 (alternate 14). - * PA4 - LCD_VSYNC (alternate 14). - * PA5 - PIN5 (input pullup). - * PA6 - LCD_G2 (alternate 14). - * PA7 - ACP_RST (input pullup). - * PA8 - I2C3_SCL (alternate 4). - * PA9 - UART_TX (alternate 7). - * PA10 - OTG_FS_ID (alternate 10). - * PA11 - OTG_FS_DM (alternate 10). - * PA12 - OTG_FS_DP (alternate 10). - * PA13 - SWDIO (alternate 0). - * PA14 - SWCLK (alternate 0). - * PA15 - TP_INT (input floating). - */ -#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ - PIN_MODE_INPUT(GPIOA_MEMS_INT1) | \ - PIN_MODE_INPUT(GPIOA_MEMS_INT2) | \ - PIN_MODE_ALTERNATE(GPIOA_LCD_B5) | \ - PIN_MODE_ALTERNATE(GPIOA_LCD_VSYNC) | \ - PIN_MODE_INPUT(GPIOA_PIN5) | \ - PIN_MODE_ALTERNATE(GPIOA_LCD_G2) | \ - PIN_MODE_INPUT(GPIOA_ACP_RST) | \ - PIN_MODE_ALTERNATE(GPIOA_I2C3_SCL) | \ - PIN_MODE_ALTERNATE(GPIOA_UART_TX) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ - PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ - PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ - PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ - PIN_MODE_INPUT(GPIOA_TP_INT)) -#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ - PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT1) | \ - PIN_OTYPE_PUSHPULL(GPIOA_MEMS_INT2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_LCD_B5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_LCD_VSYNC) | \ - PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOA_LCD_G2) | \ - PIN_OTYPE_PUSHPULL(GPIOA_ACP_RST) | \ - PIN_OTYPE_OPENDRAIN(GPIOA_I2C3_SCL) | \ - PIN_OTYPE_PUSHPULL(GPIOA_UART_TX) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOA_TP_INT)) -#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_BUTTON) | \ - PIN_OSPEED_VERYLOW(GPIOA_MEMS_INT1) | \ - PIN_OSPEED_VERYLOW(GPIOA_MEMS_INT2) | \ - PIN_OSPEED_HIGH(GPIOA_LCD_B5) | \ - PIN_OSPEED_HIGH(GPIOA_LCD_VSYNC) | \ - PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \ - PIN_OSPEED_HIGH(GPIOA_LCD_G2) | \ - PIN_OSPEED_VERYLOW(GPIOA_ACP_RST) | \ - PIN_OSPEED_HIGH(GPIOA_I2C3_SCL) | \ - PIN_OSPEED_VERYLOW(GPIOA_UART_TX) | \ - PIN_OSPEED_VERYLOW(GPIOA_OTG_FS_ID) | \ - PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ - PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ - PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ - PIN_OSPEED_VERYLOW(GPIOA_TP_INT)) -#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ - PIN_PUPDR_FLOATING(GPIOA_MEMS_INT1) | \ - PIN_PUPDR_FLOATING(GPIOA_MEMS_INT2) | \ - PIN_PUPDR_FLOATING(GPIOA_LCD_B5) | \ - PIN_PUPDR_FLOATING(GPIOA_LCD_VSYNC) | \ - PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOA_LCD_G2) | \ - PIN_PUPDR_PULLUP(GPIOA_ACP_RST) | \ - PIN_PUPDR_FLOATING(GPIOA_I2C3_SCL) | \ - PIN_PUPDR_PULLUP(GPIOA_UART_TX) | \ - PIN_PUPDR_PULLUP(GPIOA_OTG_FS_ID) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ - PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ - PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ - PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ - PIN_PUPDR_FLOATING(GPIOA_TP_INT)) -#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ - PIN_ODR_HIGH(GPIOA_MEMS_INT1) | \ - PIN_ODR_HIGH(GPIOA_MEMS_INT2) | \ - PIN_ODR_HIGH(GPIOA_LCD_B5) | \ - PIN_ODR_HIGH(GPIOA_LCD_VSYNC) | \ - PIN_ODR_HIGH(GPIOA_PIN5) | \ - PIN_ODR_HIGH(GPIOA_LCD_G2) | \ - PIN_ODR_HIGH(GPIOA_ACP_RST) | \ - PIN_ODR_HIGH(GPIOA_I2C3_SCL) | \ - PIN_ODR_HIGH(GPIOA_UART_TX) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ - PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ - PIN_ODR_HIGH(GPIOA_SWDIO) | \ - PIN_ODR_HIGH(GPIOA_SWCLK) | \ - PIN_ODR_HIGH(GPIOA_TP_INT)) -#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \ - PIN_AFIO_AF(GPIOA_MEMS_INT1, 0U) | \ - PIN_AFIO_AF(GPIOA_MEMS_INT2, 0U) | \ - PIN_AFIO_AF(GPIOA_LCD_B5, 14U) | \ - PIN_AFIO_AF(GPIOA_LCD_VSYNC, 14U) | \ - PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOA_LCD_G2, 14U) | \ - PIN_AFIO_AF(GPIOA_ACP_RST, 0U)) -#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C3_SCL, 4U) | \ - PIN_AFIO_AF(GPIOA_UART_TX, 7U) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ - PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ - PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ - PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ - PIN_AFIO_AF(GPIOA_TP_INT, 0U)) - -/* - * GPIOB setup: - * - * PB0 - LCD_R3 (alternate 14). - * PB1 - LCD_R6 (alternate 14). - * PB2 - BOOT1 (input pullup). - * PB3 - SWO (alternate 0). - * PB4 - PIN4 (input pullup). - * PB5 - PIN5 (input pullup). - * PB6 - PIN6 (input pullup). - * PB7 - PIN7 (input pullup). - * PB8 - LCD_B6 (alternate 14). - * PB9 - LCD_B7 (alternate 14). - * PB10 - LCD_G4 (alternate 14). - * PB11 - LED1 (output push-pull). - * PB12 - OTG_HS_ID (alternate 12). - * PB13 - OTG_HS_VBUS (input pulldown). - * PB14 - OTG_HS_DM (alternate 12). - * PB15 - OTG_HS_DP (alternate 12). - */ -#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_LCD_R3) | \ - PIN_MODE_ALTERNATE(GPIOB_LCD_R6) | \ - PIN_MODE_INPUT(GPIOB_BOOT1) | \ - PIN_MODE_ALTERNATE(GPIOB_SWO) | \ - PIN_MODE_INPUT(GPIOB_PIN4) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_INPUT(GPIOB_PIN6) | \ - PIN_MODE_INPUT(GPIOB_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOB_LCD_B6) | \ - PIN_MODE_ALTERNATE(GPIOB_LCD_B7) | \ - PIN_MODE_ALTERNATE(GPIOB_LCD_G4) | \ - PIN_MODE_OUTPUT(GPIOB_LED1) | \ - PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \ - PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \ - PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ - PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LCD_R3) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LCD_R6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LCD_B6) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LCD_B7) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LCD_G4) | \ - PIN_OTYPE_PUSHPULL(GPIOB_LED1) | \ - PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \ - PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\ - PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ - PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_LCD_R3) | \ - PIN_OSPEED_HIGH(GPIOB_LCD_R6) | \ - PIN_OSPEED_HIGH(GPIOB_BOOT1) | \ - PIN_OSPEED_HIGH(GPIOB_SWO) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOB_PIN7) | \ - PIN_OSPEED_HIGH(GPIOB_LCD_B6) | \ - PIN_OSPEED_HIGH(GPIOB_LCD_B7) | \ - PIN_OSPEED_HIGH(GPIOB_LCD_G4) | \ - PIN_OSPEED_VERYLOW(GPIOB_LED1) | \ - PIN_OSPEED_HIGH(GPIOB_OTG_HS_ID) | \ - PIN_OSPEED_VERYLOW(GPIOB_OTG_HS_VBUS) |\ - PIN_OSPEED_HIGH(GPIOB_OTG_HS_DM) | \ - PIN_OSPEED_HIGH(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LCD_R3) | \ - PIN_PUPDR_FLOATING(GPIOB_LCD_R6) | \ - PIN_PUPDR_PULLUP(GPIOB_BOOT1) | \ - PIN_PUPDR_FLOATING(GPIOB_SWO) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOB_LCD_B6) | \ - PIN_PUPDR_FLOATING(GPIOB_LCD_B7) | \ - PIN_PUPDR_FLOATING(GPIOB_LCD_G4) | \ - PIN_PUPDR_FLOATING(GPIOB_LED1) | \ - PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \ - PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\ - PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ - PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_LCD_R3) | \ - PIN_ODR_HIGH(GPIOB_LCD_R6) | \ - PIN_ODR_HIGH(GPIOB_BOOT1) | \ - PIN_ODR_HIGH(GPIOB_SWO) | \ - PIN_ODR_HIGH(GPIOB_PIN4) | \ - PIN_ODR_HIGH(GPIOB_PIN5) | \ - PIN_ODR_HIGH(GPIOB_PIN6) | \ - PIN_ODR_HIGH(GPIOB_PIN7) | \ - PIN_ODR_HIGH(GPIOB_LCD_B6) | \ - PIN_ODR_HIGH(GPIOB_LCD_B7) | \ - PIN_ODR_HIGH(GPIOB_LCD_G4) | \ - PIN_ODR_HIGH(GPIOB_LED1) | \ - PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \ - PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \ - PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \ - PIN_ODR_HIGH(GPIOB_OTG_HS_DP)) -#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LCD_R3, 14U) | \ - PIN_AFIO_AF(GPIOB_LCD_R6, 14U) | \ - PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \ - PIN_AFIO_AF(GPIOB_SWO, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOB_PIN7, 0U)) -#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_LCD_B6, 14U) | \ - PIN_AFIO_AF(GPIOB_LCD_B7, 14U) | \ - PIN_AFIO_AF(GPIOB_LCD_G4, 14U) | \ - PIN_AFIO_AF(GPIOB_LED1, 0U) | \ - PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12U) | \ - PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0U) | \ - PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12U) | \ - PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12U)) - -/* - * GPIOC setup: - * - * PC0 - PIN0 (input pullup). - * PC1 - SPI5_MEMS_CS (output pushpull maximum). - * PC2 - SPI5_LCD_CS (output pushpull maximum). - * PC3 - PIN3 (input pullup). - * PC4 - OTG_HS_PSO (output pushpull maximum). - * PC5 - OTG_HS_OC (input floating). - * PC6 - LCD_HSYNC (alternate 14). - * PC7 - LCD_G6 (alternate 14). - * PC8 - PIN8 (input pullup). - * PC9 - I2C3_SDA (alternate 4). - * PC10 - LCD_R2 (alternate 14). - * PC11 - PIN11 (input pullup). - * PC12 - PIN12 (input pullup). - * PC13 - PIN13 (input pullup). - * PC14 - OSC32_IN (input floating). - * PC15 - OSC32_OUT (input floating). - */ -#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_FMC_SDNWE) | \ - PIN_MODE_OUTPUT(GPIOC_SPI5_MEMS_CS) | \ - PIN_MODE_OUTPUT(GPIOC_SPI5_LCD_CS) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_OUTPUT(GPIOC_OTG_HS_PSO) | \ - PIN_MODE_INPUT(GPIOC_OTG_HS_OC) | \ - PIN_MODE_ALTERNATE(GPIOC_LCD_HSYNC) | \ - PIN_MODE_ALTERNATE(GPIOC_LCD_G6) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_ALTERNATE(GPIOC_I2C3_SDA) | \ - PIN_MODE_ALTERNATE(GPIOC_LCD_R2) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ - PIN_MODE_INPUT(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_FMC_SDNWE) | \ - PIN_OTYPE_PUSHPULL(GPIOC_SPI5_MEMS_CS) |\ - PIN_OTYPE_PUSHPULL(GPIOC_SPI5_LCD_CS) |\ - PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_PSO) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OTG_HS_OC) | \ - PIN_OTYPE_PUSHPULL(GPIOC_LCD_HSYNC) | \ - PIN_OTYPE_PUSHPULL(GPIOC_LCD_G6) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ - PIN_OTYPE_OPENDRAIN(GPIOC_I2C3_SDA) | \ - PIN_OTYPE_PUSHPULL(GPIOC_LCD_R2) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_FMC_SDNWE) | \ - PIN_OSPEED_HIGH(GPIOC_SPI5_MEMS_CS) | \ - PIN_OSPEED_HIGH(GPIOC_SPI5_LCD_CS) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \ - PIN_OSPEED_HIGH(GPIOC_OTG_HS_PSO) | \ - PIN_OSPEED_HIGH(GPIOC_OTG_HS_OC) | \ - PIN_OSPEED_HIGH(GPIOC_LCD_HSYNC) | \ - PIN_OSPEED_HIGH(GPIOC_LCD_G6) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \ - PIN_OSPEED_HIGH(GPIOC_I2C3_SDA) | \ - PIN_OSPEED_HIGH(GPIOC_LCD_R2) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOC_PIN13) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ - PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_FMC_SDNWE) | \ - PIN_PUPDR_FLOATING(GPIOC_SPI5_MEMS_CS) |\ - PIN_PUPDR_FLOATING(GPIOC_SPI5_LCD_CS) |\ - PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOC_OTG_HS_PSO) | \ - PIN_PUPDR_FLOATING(GPIOC_OTG_HS_OC) | \ - PIN_PUPDR_FLOATING(GPIOC_LCD_HSYNC) | \ - PIN_PUPDR_FLOATING(GPIOC_LCD_G6) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ - PIN_PUPDR_FLOATING(GPIOC_I2C3_SDA) | \ - PIN_PUPDR_FLOATING(GPIOC_LCD_R2) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ - PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_FMC_SDNWE) | \ - PIN_ODR_HIGH(GPIOC_SPI5_MEMS_CS) | \ - PIN_ODR_HIGH(GPIOC_SPI5_LCD_CS) | \ - PIN_ODR_HIGH(GPIOC_PIN3) | \ - PIN_ODR_HIGH(GPIOC_OTG_HS_PSO) | \ - PIN_ODR_HIGH(GPIOC_OTG_HS_OC) | \ - PIN_ODR_HIGH(GPIOC_LCD_HSYNC) | \ - PIN_ODR_HIGH(GPIOC_LCD_G6) | \ - PIN_ODR_HIGH(GPIOC_PIN8) | \ - PIN_ODR_HIGH(GPIOC_I2C3_SDA) | \ - PIN_ODR_HIGH(GPIOC_LCD_R2) | \ - PIN_ODR_HIGH(GPIOC_PIN11) | \ - PIN_ODR_HIGH(GPIOC_PIN12) | \ - PIN_ODR_HIGH(GPIOC_PIN13) | \ - PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ - PIN_ODR_HIGH(GPIOC_OSC32_OUT)) -#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_FMC_SDNWE, 12U) | \ - PIN_AFIO_AF(GPIOC_SPI5_MEMS_CS, 0U) | \ - PIN_AFIO_AF(GPIOC_SPI5_LCD_CS, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOC_OTG_HS_PSO, 0U) | \ - PIN_AFIO_AF(GPIOC_OTG_HS_OC, 0U) | \ - PIN_AFIO_AF(GPIOC_LCD_HSYNC, 14U) | \ - PIN_AFIO_AF(GPIOC_LCD_G6, 14U)) -#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOC_I2C3_SDA, 4U) | \ - PIN_AFIO_AF(GPIOC_LCD_R2, 14U) | \ - PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ - PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) - -/* - * GPIOD setup: - * - * PD0 - FMC_D2 (alternate 12). - * PD1 - FMC_D3 (alternate 12). - * PD2 - PIN2 (input pullup). - * PD3 - LCD_G7 (alternate 14). - * PD4 - PIN4 (input pullup). - * PD5 - PIN5 (input pullup). - * PD6 - LCD_B2 (alternate 14). - * PD7 - PIN7 (input pullup). - * PD8 - FMC_D13 (alternate 12). - * PD9 - FMC_D14 (alternate 12). - * PD10 - FMC_D15 (alternate 12). - * PD11 - LCD_TE (input floating). - * PD12 - LCD_RDX (output pushpull maximum). - * PD13 - LCD_WRX (output pushpull maximum). - * PD14 - FMC_D0 (alternate 12). - * PD15 - FMC_D1 (alternate 12). - */ -#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D3) | \ - PIN_MODE_INPUT(GPIOD_PIN2) | \ - PIN_MODE_ALTERNATE(GPIOD_LCD_G7) | \ - PIN_MODE_INPUT(GPIOD_PIN4) | \ - PIN_MODE_INPUT(GPIOD_PIN5) | \ - PIN_MODE_ALTERNATE(GPIOD_LCD_B2) | \ - PIN_MODE_INPUT(GPIOD_PIN7) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D13) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D14) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D15) | \ - PIN_MODE_INPUT(GPIOD_LCD_TE) | \ - PIN_MODE_OUTPUT(GPIOD_LCD_RDX) | \ - PIN_MODE_OUTPUT(GPIOD_LCD_WRX) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D0) | \ - PIN_MODE_ALTERNATE(GPIOD_FMC_D1)) -#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LCD_G7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LCD_B2) | \ - PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LCD_TE) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LCD_RDX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_LCD_WRX) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) | \ - PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1)) -#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FMC_D2) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D3) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \ - PIN_OSPEED_HIGH(GPIOD_LCD_G7) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \ - PIN_OSPEED_HIGH(GPIOD_LCD_B2) | \ - PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D13) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D14) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D15) | \ - PIN_OSPEED_HIGH(GPIOD_LCD_TE) | \ - PIN_OSPEED_HIGH(GPIOD_LCD_RDX) | \ - PIN_OSPEED_HIGH(GPIOD_LCD_WRX) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D0) | \ - PIN_OSPEED_HIGH(GPIOD_FMC_D1)) -#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D3) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ - PIN_PUPDR_FLOATING(GPIOD_LCD_G7) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ - PIN_PUPDR_FLOATING(GPIOD_LCD_B2) | \ - PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D13) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D14) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D15) | \ - PIN_PUPDR_FLOATING(GPIOD_LCD_TE) | \ - PIN_PUPDR_FLOATING(GPIOD_LCD_RDX) | \ - PIN_PUPDR_FLOATING(GPIOD_LCD_WRX) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D0) | \ - PIN_PUPDR_FLOATING(GPIOD_FMC_D1)) -#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FMC_D2) | \ - PIN_ODR_HIGH(GPIOD_FMC_D3) | \ - PIN_ODR_HIGH(GPIOD_PIN2) | \ - PIN_ODR_HIGH(GPIOD_LCD_G7) | \ - PIN_ODR_HIGH(GPIOD_PIN4) | \ - PIN_ODR_HIGH(GPIOD_PIN5) | \ - PIN_ODR_HIGH(GPIOD_LCD_B2) | \ - PIN_ODR_HIGH(GPIOD_PIN7) | \ - PIN_ODR_HIGH(GPIOD_FMC_D13) | \ - PIN_ODR_HIGH(GPIOD_FMC_D14) | \ - PIN_ODR_HIGH(GPIOD_FMC_D15) | \ - PIN_ODR_HIGH(GPIOD_LCD_TE) | \ - PIN_ODR_HIGH(GPIOD_LCD_RDX) | \ - PIN_ODR_HIGH(GPIOD_LCD_WRX) | \ - PIN_ODR_HIGH(GPIOD_FMC_D0) | \ - PIN_ODR_HIGH(GPIOD_FMC_D1)) -#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FMC_D2, 12U) | \ - PIN_AFIO_AF(GPIOD_FMC_D3, 12U) | \ - PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOD_LCD_G7, 14U) | \ - PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOD_LCD_B2, 14U) | \ - PIN_AFIO_AF(GPIOD_PIN7, 0U)) -#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FMC_D13, 12U) | \ - PIN_AFIO_AF(GPIOD_FMC_D14, 12U) | \ - PIN_AFIO_AF(GPIOD_FMC_D15, 12U) | \ - PIN_AFIO_AF(GPIOD_LCD_TE, 0U) | \ - PIN_AFIO_AF(GPIOD_LCD_RDX, 0U) | \ - PIN_AFIO_AF(GPIOD_LCD_WRX, 0U) | \ - PIN_AFIO_AF(GPIOD_FMC_D0, 12U) | \ - PIN_AFIO_AF(GPIOD_FMC_D1, 12U)) - -/* - * GPIOE setup: - * - * PE0 - FMC_NBL0 (alternate 12). - * PE1 - FMC_NBL1 (alternate 12). - * PE2 - PIN2 (input pullup). - * PE3 - PIN3 (input pullup). - * PE4 - PIN4 (input pullup). - * PE5 - PIN5 (input pullup). - * PE6 - PIN6 (input pullup). - * PE7 - FMC_D4 (alternate 12). - * PE8 - FMC_D5 (alternate 12). - * PE9 - FMC_D6 (alternate 12). - * PE10 - FMC_D7 (alternate 12). - * PE11 - FMC_D8 (alternate 12). - * PE12 - FMC_D9 (alternate 12). - * PE13 - FMC_D10 (alternate 12). - * PE14 - FMC_D11 (alternate 12). - * PE15 - FMC_D12 (alternate 12). - */ -#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ - PIN_MODE_INPUT(GPIOE_PIN2) | \ - PIN_MODE_INPUT(GPIOE_PIN3) | \ - PIN_MODE_INPUT(GPIOE_PIN4) | \ - PIN_MODE_INPUT(GPIOE_PIN5) | \ - PIN_MODE_INPUT(GPIOE_PIN6) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D4) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D5) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D6) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D7) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D8) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D9) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D10) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D11) | \ - PIN_MODE_ALTERNATE(GPIOE_FMC_D12)) -#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D11) | \ - PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12)) -#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_FMC_NBL0) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_NBL1) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D4) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D5) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D6) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D7) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D8) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D9) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D10) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D11) | \ - PIN_OSPEED_HIGH(GPIOE_FMC_D12)) -#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D4) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D5) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D6) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D7) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D8) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D9) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D10) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D11) | \ - PIN_PUPDR_FLOATING(GPIOE_FMC_D12)) -#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ - PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ - PIN_ODR_HIGH(GPIOE_PIN2) | \ - PIN_ODR_HIGH(GPIOE_PIN3) | \ - PIN_ODR_HIGH(GPIOE_PIN4) | \ - PIN_ODR_HIGH(GPIOE_PIN5) | \ - PIN_ODR_HIGH(GPIOE_PIN6) | \ - PIN_ODR_HIGH(GPIOE_FMC_D4) | \ - PIN_ODR_HIGH(GPIOE_FMC_D5) | \ - PIN_ODR_HIGH(GPIOE_FMC_D6) | \ - PIN_ODR_HIGH(GPIOE_FMC_D7) | \ - PIN_ODR_HIGH(GPIOE_FMC_D8) | \ - PIN_ODR_HIGH(GPIOE_FMC_D9) | \ - PIN_ODR_HIGH(GPIOE_FMC_D10) | \ - PIN_ODR_HIGH(GPIOE_FMC_D11) | \ - PIN_ODR_HIGH(GPIOE_FMC_D12)) -#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_NBL1, 12U) | \ - PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOE_FMC_D4, 12U)) -#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FMC_D5, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D6, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D7, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D8, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D9, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D10, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D11, 12U) | \ - PIN_AFIO_AF(GPIOE_FMC_D12, 12U)) - -/* - * GPIOF setup: - * - * PF0 - FMC_A0 (alternate 12). - * PF1 - FMC_A1 (alternate 12). - * PF2 - FMC_A2 (alternate 12). - * PF3 - FMC_A3 (alternate 12). - * PF4 - FMC_A4 (alternate 12). - * PF5 - FMC_A5 (alternate 12). - * PF6 - PIN6 (input pullup). - * PF7 - LCD_DCX (alternate 5). - * PF8 - SPI5_MISO (alternate 5). - * PF9 - SPI5_MOSI (alternate 5). - * PF10 - LCD_DE (alternate 14). - * PF11 - FMC_SDNRAS (alternate 12). - * PF12 - FMC_A6 (alternate 12). - * PF13 - FMC_A7 (alternate 12). - * PF14 - FMC_A8 (alternate 12). - * PF15 - FMC_A9 (alternate 12). - */ -#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A1) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A2) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A3) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ - PIN_MODE_INPUT(GPIOF_PIN6) | \ - PIN_MODE_ALTERNATE(GPIOF_LCD_DCX) | \ - PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) | \ - PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) | \ - PIN_MODE_ALTERNATE(GPIOF_LCD_DE) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A8) | \ - PIN_MODE_ALTERNATE(GPIOF_FMC_A9)) -#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) | \ - PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_LCD_DCX) | \ - PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MISO) | \ - PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MOSI) | \ - PIN_OTYPE_PUSHPULL(GPIOF_LCD_DE) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) | \ - PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9)) -#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_FMC_A0) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A1) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A2) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A3) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A4) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A5) | \ - PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ - PIN_OSPEED_HIGH(GPIOF_LCD_DCX) | \ - PIN_OSPEED_HIGH(GPIOF_SPI5_MISO) | \ - PIN_OSPEED_HIGH(GPIOF_SPI5_MOSI) | \ - PIN_OSPEED_HIGH(GPIOF_LCD_DE) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_SDNRAS) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A6) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A7) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A8) | \ - PIN_OSPEED_HIGH(GPIOF_FMC_A9)) -#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A1) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A2) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A3) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A4) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A5) | \ - PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ - PIN_PUPDR_FLOATING(GPIOF_LCD_DCX) | \ - PIN_PUPDR_FLOATING(GPIOF_SPI5_MISO) | \ - PIN_PUPDR_FLOATING(GPIOF_SPI5_MOSI) | \ - PIN_PUPDR_FLOATING(GPIOF_LCD_DE) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A6) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A7) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A8) | \ - PIN_PUPDR_FLOATING(GPIOF_FMC_A9)) -#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FMC_A0) | \ - PIN_ODR_HIGH(GPIOF_FMC_A1) | \ - PIN_ODR_HIGH(GPIOF_FMC_A2) | \ - PIN_ODR_HIGH(GPIOF_FMC_A3) | \ - PIN_ODR_HIGH(GPIOF_FMC_A4) | \ - PIN_ODR_HIGH(GPIOF_FMC_A5) | \ - PIN_ODR_HIGH(GPIOF_PIN6) | \ - PIN_ODR_HIGH(GPIOF_LCD_DCX) | \ - PIN_ODR_HIGH(GPIOF_SPI5_MISO) | \ - PIN_ODR_HIGH(GPIOF_SPI5_MOSI) | \ - PIN_ODR_HIGH(GPIOF_LCD_DE) | \ - PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) | \ - PIN_ODR_HIGH(GPIOF_FMC_A6) | \ - PIN_ODR_HIGH(GPIOF_FMC_A7) | \ - PIN_ODR_HIGH(GPIOF_FMC_A8) | \ - PIN_ODR_HIGH(GPIOF_FMC_A9)) -#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FMC_A0, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A1, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A2, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A3, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A4, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A5, 12U) | \ - PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOF_LCD_DCX, 5U)) -#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5U) | \ - PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5U) | \ - PIN_AFIO_AF(GPIOF_LCD_DE, 14U) | \ - PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A6, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A7, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A8, 12U) | \ - PIN_AFIO_AF(GPIOF_FMC_A9, 12U)) - -/* - * GPIOG setup: - * - * PG0 - FMC_A10 (alternate 12). - * PG1 - FMC_A11 (alternate 12). - * PG2 - PIN2 (input pullup). - * PG3 - PIN3 (input pullup). - * PG4 - FMC_BA0 (alternate 12). - * PG5 - FMC_BA1 (alternate 12). - * PG6 - LCD_R7 (alternate 14). - * PG7 - LCD_CLK (alternate 14). - * PG8 - FMC_SDCLK (alternate 12). - * PG9 - PIN9 (input pullup). - * PG10 - LCD_G3 (alternate 14). - * PG11 - LCD_B3 (alternate 14). - * PG12 - LCD_B4 (alternate 14). - * PG13 - LED3_GREEN (output pushpull maximum). - * PG14 - LED4_RED (output pushpull maximum). - * PG15 - FMC_SDNCAS (alternate 12). - */ -#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_A11) | \ - PIN_MODE_INPUT(GPIOG_PIN2) | \ - PIN_MODE_INPUT(GPIOG_PIN3) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) | \ - PIN_MODE_ALTERNATE(GPIOG_LCD_R7) | \ - PIN_MODE_ALTERNATE(GPIOG_LCD_CLK) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_SDCLK) | \ - PIN_MODE_INPUT(GPIOG_PIN9) | \ - PIN_MODE_ALTERNATE(GPIOG_LCD_G3) | \ - PIN_MODE_ALTERNATE(GPIOG_LCD_B3) | \ - PIN_MODE_ALTERNATE(GPIOG_LCD_B4) | \ - PIN_MODE_OUTPUT(GPIOG_LED3_GREEN) | \ - PIN_MODE_OUTPUT(GPIOG_LED4_RED) | \ - PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) | \ - PIN_OTYPE_PUSHPULL(GPIOG_LCD_R7) | \ - PIN_OTYPE_PUSHPULL(GPIOG_LCD_CLK) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) | \ - PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOG_LCD_G3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_LCD_B3) | \ - PIN_OTYPE_PUSHPULL(GPIOG_LCD_B4) | \ - PIN_OTYPE_PUSHPULL(GPIOG_LED3_GREEN) | \ - PIN_OTYPE_PUSHPULL(GPIOG_LED4_RED) | \ - PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_FMC_A10) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_A11) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_BA0) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_BA1) | \ - PIN_OSPEED_HIGH(GPIOG_LCD_R7) | \ - PIN_OSPEED_HIGH(GPIOG_LCD_CLK) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_SDCLK) | \ - PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \ - PIN_OSPEED_HIGH(GPIOG_LCD_G3) | \ - PIN_OSPEED_HIGH(GPIOG_LCD_B3) | \ - PIN_OSPEED_HIGH(GPIOG_LCD_B4) | \ - PIN_OSPEED_HIGH(GPIOG_LED3_GREEN) | \ - PIN_OSPEED_HIGH(GPIOG_LED4_RED) | \ - PIN_OSPEED_HIGH(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_A11) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) | \ - PIN_PUPDR_FLOATING(GPIOG_LCD_R7) | \ - PIN_PUPDR_FLOATING(GPIOG_LCD_CLK) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) | \ - PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ - PIN_PUPDR_FLOATING(GPIOG_LCD_G3) | \ - PIN_PUPDR_FLOATING(GPIOG_LCD_B3) | \ - PIN_PUPDR_FLOATING(GPIOG_LCD_B4) | \ - PIN_PUPDR_FLOATING(GPIOG_LED3_GREEN) | \ - PIN_PUPDR_FLOATING(GPIOG_LED4_RED) | \ - PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FMC_A10) | \ - PIN_ODR_HIGH(GPIOG_FMC_A11) | \ - PIN_ODR_HIGH(GPIOG_PIN2) | \ - PIN_ODR_HIGH(GPIOG_PIN3) | \ - PIN_ODR_HIGH(GPIOG_FMC_BA0) | \ - PIN_ODR_HIGH(GPIOG_FMC_BA1) | \ - PIN_ODR_HIGH(GPIOG_LCD_R7) | \ - PIN_ODR_HIGH(GPIOG_LCD_CLK) | \ - PIN_ODR_HIGH(GPIOG_FMC_SDCLK) | \ - PIN_ODR_HIGH(GPIOG_PIN9) | \ - PIN_ODR_HIGH(GPIOG_LCD_G3) | \ - PIN_ODR_HIGH(GPIOG_LCD_B3) | \ - PIN_ODR_HIGH(GPIOG_LCD_B4) | \ - PIN_ODR_LOW(GPIOG_LED3_GREEN) | \ - PIN_ODR_LOW(GPIOG_LED4_RED) | \ - PIN_ODR_HIGH(GPIOG_FMC_SDNCAS)) -#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FMC_A10, 12U) | \ - PIN_AFIO_AF(GPIOG_FMC_A11, 12U) | \ - PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOG_FMC_BA0, 12U) | \ - PIN_AFIO_AF(GPIOG_FMC_BA1, 12U) | \ - PIN_AFIO_AF(GPIOG_LCD_R7, 14U) | \ - PIN_AFIO_AF(GPIOG_LCD_CLK, 14U)) -#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 12U) | \ - PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOG_LCD_G3, 14U) | \ - PIN_AFIO_AF(GPIOG_LCD_B3, 14U) | \ - PIN_AFIO_AF(GPIOG_LCD_B4, 14U) | \ - PIN_AFIO_AF(GPIOG_LED3_GREEN, 0U) | \ - PIN_AFIO_AF(GPIOG_LED4_RED, 0U) | \ - PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12U)) - -/* - * GPIOH setup: - * - * PH0 - OSC_IN (input floating). - * PH1 - OSC_OUT (input floating). - * PH2 - PIN2 (input pullup). - * PH3 - PIN3 (input pullup). - * PH4 - PIN4 (input pullup). - * PH5 - FMC_SDNWE (alternate 12). - * PH6 - FMC_SDNE1 (alternate 12). - * PH7 - FMC_SDCKE1 (alternate 12). - * PH8 - PIN8 (input pullup). - * PH9 - PIN9 (input pullup). - * PH10 - PIN10 (input pullup). - * PH11 - PIN11 (input pullup). - * PH12 - PIN12 (input pullup). - * PH13 - PIN13 (input pullup). - * PH14 - PIN14 (input pullup). - * PH15 - PIN15 (input pullup). - */ -#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ - PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ - PIN_MODE_INPUT(GPIOH_PIN2) | \ - PIN_MODE_INPUT(GPIOH_PIN3) | \ - PIN_MODE_INPUT(GPIOH_PIN4) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_SDNWE) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_SDNE1) | \ - PIN_MODE_ALTERNATE(GPIOH_FMC_SDCKE1) | \ - PIN_MODE_INPUT(GPIOH_PIN8) | \ - PIN_MODE_INPUT(GPIOH_PIN9) | \ - PIN_MODE_INPUT(GPIOH_PIN10) | \ - PIN_MODE_INPUT(GPIOH_PIN11) | \ - PIN_MODE_INPUT(GPIOH_PIN12) | \ - PIN_MODE_INPUT(GPIOH_PIN13) | \ - PIN_MODE_INPUT(GPIOH_PIN14) | \ - PIN_MODE_INPUT(GPIOH_PIN15)) -#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ - PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNWE) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNE1) | \ - PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDCKE1) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) -#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ - PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_SDNWE) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_SDNE1) | \ - PIN_OSPEED_HIGH(GPIOH_FMC_SDCKE1) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOH_PIN15)) -#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ - PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_SDNWE) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_SDNE1) | \ - PIN_PUPDR_FLOATING(GPIOH_FMC_SDCKE1) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOH_PIN15)) -#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ - PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ - PIN_ODR_HIGH(GPIOH_PIN2) | \ - PIN_ODR_HIGH(GPIOH_PIN3) | \ - PIN_ODR_HIGH(GPIOH_PIN4) | \ - PIN_ODR_HIGH(GPIOH_FMC_SDNWE) | \ - PIN_ODR_HIGH(GPIOH_FMC_SDNE1) | \ - PIN_ODR_HIGH(GPIOH_FMC_SDCKE1) | \ - PIN_ODR_HIGH(GPIOH_PIN8) | \ - PIN_ODR_HIGH(GPIOH_PIN9) | \ - PIN_ODR_HIGH(GPIOH_PIN10) | \ - PIN_ODR_HIGH(GPIOH_PIN11) | \ - PIN_ODR_HIGH(GPIOH_PIN12) | \ - PIN_ODR_HIGH(GPIOH_PIN13) | \ - PIN_ODR_HIGH(GPIOH_PIN14) | \ - PIN_ODR_HIGH(GPIOH_PIN15)) -#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ - PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOH_FMC_SDNWE, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_SDNE1, 12U) | \ - PIN_AFIO_AF(GPIOH_FMC_SDCKE1, 12U)) -#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOH_PIN15, 0U)) - -/* - * GPIOI setup: - * - * PI0 - PIN0 (input pullup). - * PI1 - PIN1 (input pullup). - * PI2 - PIN2 (input pullup). - * PI3 - PIN3 (input pullup). - * PI4 - PIN4 (input pullup). - * PI5 - PIN5 (input pullup). - * PI6 - PIN6 (input pullup). - * PI7 - PIN7 (input pullup). - * PI8 - PIN8 (input pullup). - * PI9 - PIN9 (input pullup). - * PI10 - PIN10 (input pullup). - * PI11 - PIN11 (input pullup). - * PI12 - PIN12 (input pullup). - * PI13 - PIN13 (input pullup). - * PI14 - PIN14 (input pullup). - * PI15 - PIN15 (input pullup). - */ -#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ - PIN_MODE_INPUT(GPIOI_PIN1) | \ - PIN_MODE_INPUT(GPIOI_PIN2) | \ - PIN_MODE_INPUT(GPIOI_PIN3) | \ - PIN_MODE_INPUT(GPIOI_PIN4) | \ - PIN_MODE_INPUT(GPIOI_PIN5) | \ - PIN_MODE_INPUT(GPIOI_PIN6) | \ - PIN_MODE_INPUT(GPIOI_PIN7) | \ - PIN_MODE_INPUT(GPIOI_PIN8) | \ - PIN_MODE_INPUT(GPIOI_PIN9) | \ - PIN_MODE_INPUT(GPIOI_PIN10) | \ - PIN_MODE_INPUT(GPIOI_PIN11) | \ - PIN_MODE_INPUT(GPIOI_PIN12) | \ - PIN_MODE_INPUT(GPIOI_PIN13) | \ - PIN_MODE_INPUT(GPIOI_PIN14) | \ - PIN_MODE_INPUT(GPIOI_PIN15)) -#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ - PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) -#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ - PIN_OSPEED_VERYLOW(GPIOI_PIN15)) -#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ - PIN_PUPDR_PULLUP(GPIOI_PIN15)) -#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ - PIN_ODR_HIGH(GPIOI_PIN1) | \ - PIN_ODR_HIGH(GPIOI_PIN2) | \ - PIN_ODR_HIGH(GPIOI_PIN3) | \ - PIN_ODR_HIGH(GPIOI_PIN4) | \ - PIN_ODR_HIGH(GPIOI_PIN5) | \ - PIN_ODR_HIGH(GPIOI_PIN6) | \ - PIN_ODR_HIGH(GPIOI_PIN7) | \ - PIN_ODR_HIGH(GPIOI_PIN8) | \ - PIN_ODR_HIGH(GPIOI_PIN9) | \ - PIN_ODR_HIGH(GPIOI_PIN10) | \ - PIN_ODR_HIGH(GPIOI_PIN11) | \ - PIN_ODR_HIGH(GPIOI_PIN12) | \ - PIN_ODR_HIGH(GPIOI_PIN13) | \ - PIN_ODR_HIGH(GPIOI_PIN14) | \ - PIN_ODR_HIGH(GPIOI_PIN15)) -#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN7, 0U)) -#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ - PIN_AFIO_AF(GPIOI_PIN15, 0U)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif /* BOARD_H */ diff --git a/firmware/config/boards/f429-208/board.mk b/firmware/config/boards/f429-208/board.mk deleted file mode 100644 index 4b6583f2ee..0000000000 --- a/firmware/config/boards/f429-208/board.mk +++ /dev/null @@ -1,24 +0,0 @@ -HALCONFDIR = $(BOARD_DIR) - -# List of all the board related files. -BOARDCPPSRC = $(BOARD_DIR)/board_configuration.cpp - -# Required include directories -# STM32F429 has FSMC with SDRAM support -DDEFS += -DFIRMWARE_ID=\"stm32f429\" -IS_STM32F429 = yes -EFI_HAS_EXT_SDRAM = yes - -#LED -DDEFS += -DLED_CRITICAL_ERROR_BRAIN_PIN=Gpio::B11 - -DDEFS += -DSTM32_FSMC_USE_FSMC1=TRUE -DSTM32_SDRAM_USE_SDRAM2=TRUE - -DDEFS += -DHAL_USE_SDRAM=TRUE -DDEFS += -DHAL_USE_FSMC=TRUE - -# see signature_haba208.h -DDEFS += -DSHORT_BOARD_NAME=haba208 - -# Shared variables -ALLINC += $(BOARDINC) diff --git a/firmware/config/boards/f429-208/board_configuration.cpp b/firmware/config/boards/f429-208/board_configuration.cpp deleted file mode 100644 index 06f1e78106..0000000000 --- a/firmware/config/boards/f429-208/board_configuration.cpp +++ /dev/null @@ -1,20 +0,0 @@ -#include "pch.h" - -/** - * @brief Board-specific initialization code. - * @todo Add your board-specific code, if any. - */ -void boardInit(void) -{ - /* NOP */ -} - -/** - * @brief Board-specific configuration defaults. - * @todo Add your board-specific code, if any. - */ -void setBoardDefaultConfiguration() { - engineConfiguration->communicationLedPin = Gpio::Unassigned; - engineConfiguration->runningLedPin = Gpio::G13; /* LD3 - green */ - engineConfiguration->warningLedPin = Gpio::Unassigned; -} diff --git a/firmware/config/boards/f429-208/compile_f429-208.sh b/firmware/config/boards/f429-208/compile_f429-208.sh deleted file mode 100755 index d24962c9e4..0000000000 --- a/firmware/config/boards/f429-208/compile_f429-208.sh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/bash - -#-DDUMMY -DEFI_ENABLE_ASSERTS=FALSE -DCH_DBG_ENABLE_ASSERTS=FALSE -DCH_DBG_ENABLE_STACK_CHECK=FALSE -DCH_DBG_FILL_THREADS=FALSE -DCH_DBG_THREADS_PROFILING=FALSE" - -bash ../common_make.sh f429-208 ARCH_STM32F4 diff --git a/firmware/config/boards/f429-208/prepend.txt b/firmware/config/boards/f429-208/prepend.txt deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/firmware/config/boards/hellen/hellen88bmw/compile_hellen88bmw_avr.sh b/firmware/config/boards/hellen/hellen88bmw/compile_hellen88bmw_avr.sh deleted file mode 100644 index 151140bc33..0000000000 --- a/firmware/config/boards/hellen/hellen88bmw/compile_hellen88bmw_avr.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/bash - -cd .. - -export EXTRA_PARAMS="-DDUMMY \ --DEFI_SOFTWARE_KNOCK=FALSE \ --DHAL_TRIGGER_USE_ADC=TRUE \ --DSTM32_ADC_USE_ADC3=TRUE \ -" - - -bash ../common_make.sh hellen/hellen88bmw ARCH_STM32F4 diff --git a/firmware/config/boards/microrusefi/!compile_mre_f4_hardware_QC_special_build.bat b/firmware/config/boards/microrusefi/!compile_mre_f4_hardware_QC_special_build.bat deleted file mode 100644 index 888da1a27c..0000000000 --- a/firmware/config/boards/microrusefi/!compile_mre_f4_hardware_QC_special_build.bat +++ /dev/null @@ -1,2 +0,0 @@ -@echo off -bash.exe compile_mre_f4_hardware_QC_special_build.sh diff --git a/firmware/config/boards/microrusefi/board_configuration.cpp b/firmware/config/boards/microrusefi/board_configuration.cpp index 6a7b1c3371..04950f70a2 100644 --- a/firmware/config/boards/microrusefi/board_configuration.cpp +++ b/firmware/config/boards/microrusefi/board_configuration.cpp @@ -130,11 +130,6 @@ static void setupDefaultSensorInputs() { setCommonNTCSensor(&engineConfiguration->auxTempSensor1, 2700); setCommonNTCSensor(&engineConfiguration->auxTempSensor2, 2700); - -#if HW_CHECK_MODE - engineConfiguration->auxTempSensor1.adcChannel = EFI_ADC_2; - engineConfiguration->auxTempSensor2.adcChannel = EFI_ADC_3; -#endif // HW_CHECK_MODE } void setBoardConfigOverrides() { diff --git a/firmware/config/boards/microrusefi/compile_mre_f4_hardware_QC_special_build.sh b/firmware/config/boards/microrusefi/compile_mre_f4_hardware_QC_special_build.sh deleted file mode 100755 index 219245a9b6..0000000000 --- a/firmware/config/boards/microrusefi/compile_mre_f4_hardware_QC_special_build.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/bash - -export EXTRA_PARAMS="-DDUMMY \ - -DHW_CHECK_MODE=TRUE \ - -DANALOG_HW_CHECK_MODE=TRUE \ - -DEFI_HPFP=FALSE \ - -DEFI_ALTERNATOR_CONTROL=FALSE \ - -DEFI_LOGIC_ANALYZER=FALSE \ - -DEFI_TOOTH_LOGGER=FALSE \ - -DEFI_LUA=FALSE \ - -DEFI_MALFUNCTION_INDICATOR=FALSE \ - -DEFI_AUX_PID=FALSE \ - -DEFI_MAX_31855=FALSE \ - -DEFI_ENGINE_SNIFFER=FALSE \ - -DEFI_STORAGE_INT_FLASH=FALSE \ - -DEFI_LAUNCH_CONTROL=FALSE \ - -DEFI_LAUNCH_CONTROL=FALSE \ - -DHW_CHECK_ALWAYS_STIMULATE=TRUE \ - -DRAMDISK_INVALID" - -export VAR_DEF_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=MRE_BOARD_NEW_TEST - -# this QC configuration is used to assert our status with debug info -export DEBUG_LEVEL_OPT="-O0 -ggdb -g" - -bash ../common_make.sh microrusefi ARCH_STM32F4 diff --git a/firmware/config/boards/proteus/board_configuration.cpp b/firmware/config/boards/proteus/board_configuration.cpp index d22d8703af..fdd8424317 100644 --- a/firmware/config/boards/proteus/board_configuration.cpp +++ b/firmware/config/boards/proteus/board_configuration.cpp @@ -102,18 +102,8 @@ static void setupEtb() { static void setupDefaultSensorInputs() { // trigger inputs -#if VR_HW_CHECK_MODE - // set_trigger_input_pin 0 PE7 - engineConfiguration->triggerInputPins[0] = PROTEUS_VR_1; - engineConfiguration->camInputs[0] = PROTEUS_VR_2; -#else // Digital channel 1 as default - others not set engineConfiguration->triggerInputPins[0] = PROTEUS_DIGITAL_1; - engineConfiguration->camInputs[0] = Gpio::Unassigned; -#endif - - engineConfiguration->triggerInputPins[1] = Gpio::Unassigned; - engineConfiguration->clt.adcChannel = PROTEUS_IN_CLT; engineConfiguration->iat.adcChannel = PROTEUS_IN_IAT; diff --git a/firmware/config/boards/proteus/compile_proteus_f4_hardware_QC_special_build.sh b/firmware/config/boards/proteus/compile_proteus_f4_hardware_QC_special_build.sh deleted file mode 100755 index 419a36b490..0000000000 --- a/firmware/config/boards/proteus/compile_proteus_f4_hardware_QC_special_build.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/bash - -export EXTRA_PARAMS="-DVR_HW_CHECK_MODE=TRUE -DHW_CHECK_MODE=TRUE -DHW_CHECK_SD=TRUE -DHW_CHECK_ALWAYS_STIMULATE=TRUE" - -export VAR_DEF_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=PROTEUS_QC_TEST_BOARD - -# export DEBUG_LEVEL_OPT="-O0 -ggdb -g" - -bash ../common_make.sh proteus ARCH_STM32F4 diff --git a/firmware/config/boards/proteus/compile_proteus_f7_hardware_QC_special_build.sh b/firmware/config/boards/proteus/compile_proteus_f7_hardware_QC_special_build.sh deleted file mode 100755 index ada3743ee2..0000000000 --- a/firmware/config/boards/proteus/compile_proteus_f7_hardware_QC_special_build.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/bash - -export EXTRA_PARAMS="-DVR_HW_CHECK_MODE=TRUE -DHW_CHECK_MODE=TRUE -DHW_CHECK_SD=TRUE -DHW_CHECK_ALWAYS_STIMULATE=TRUE" - -export VAR_DEF_ENGINE_TYPE=-DDEFAULT_ENGINE_TYPE=PROTEUS_QC_TEST_BOARD - -# export DEBUG_LEVEL_OPT="-O0 -ggdb -g" - -bash ../common_make.sh proteus ARCH_STM32F7 diff --git a/firmware/config/boards/readme.md b/firmware/config/boards/readme.md index d3c6eba847..dde27814d3 100644 --- a/firmware/config/boards/readme.md +++ b/firmware/config/boards/readme.md @@ -4,10 +4,6 @@ rusEFI supports quite a wide array of hardware - we support stm32f4 and we suppo For best user experience we have more than a dozen of different _binaries_ which are all compiled from same _firmware_ files with different configuration. This folder is all about that process. - -See [misc/jenkins/compile_other_versions/run.bat](misc/jenkins/compile_other_versions/run.bat) which is executed by build server. - - See https://rusefi.com/build_server/ By definition, BOARD_NAME is a folder in firmware\config\boards diff --git a/firmware/console/binary/tunerstudio.cpp b/firmware/console/binary/tunerstudio.cpp index b9e17b3104..2ae8daa8ea 100644 --- a/firmware/console/binary/tunerstudio.cpp +++ b/firmware/console/binary/tunerstudio.cpp @@ -826,12 +826,6 @@ int TunerStudio::handleCrcCommand(TsChannelBase* tsChannel, char *data, int inco #endif /* ENABLE_PERF_TRACE */ case TS_GET_CONFIG_ERROR: { const char* configError = getCriticalErrorMessage(); -#if HW_CHECK_MODE - // analog input errors are returned as firmware error in QC mode - if (!hasFirmwareError()) { - strcpy((char*)configError, "FACTORY_MODE_PLEASE_CONTACT_SUPPORT"); - } -#endif // HW_CHECK_MODE tsChannel->sendResponse(TS_CRC, reinterpret_cast(configError), strlen(configError), true); break; } diff --git a/firmware/console/status_loop.cpp b/firmware/console/status_loop.cpp index 00b43ddb01..81a63c747f 100644 --- a/firmware/console/status_loop.cpp +++ b/firmware/console/status_loop.cpp @@ -313,18 +313,7 @@ class CommunicationBlinkingTask : public PeriodicTimerController { setAllLeds(0); } else if (counter % 2 == 0) { enginePins.communicationLedPin.setValue(0); -#if HW_CHECK_SD -extern int totalLoggedBytes; - if (totalLoggedBytes > 2000) { - enginePins.communicationLedPin.setValue(1); - } -#endif // HW_CHECK_SD -//#if HW_CHECK_MODE -// // we have to do anything possible to help users notice FACTORY MODE -// enginePins.errorLedPin.setValue(1); -// enginePins.runningLedPin.setValue(1); -//#endif // HW_CHECK_MODE if (!lowVBatt) { enginePins.warningLedPin.setValue(0); } @@ -354,11 +343,6 @@ extern int totalLoggedBytes; } enginePins.communicationLedPin.setValue(1); -//#if HW_CHECK_MODE -// // we have to do anything possible to help users notice FACTORY MODE -// enginePins.errorLedPin.setValue(0); -// enginePins.runningLedPin.setValue(0); -//#endif // HW_CHECK_MODE #if EFI_ENGINE_CONTROL if (lowVBatt || isTriggerErrorNow() || isIgnitionTimingError()) { @@ -696,11 +680,7 @@ DcHardware *getdcHardware(); extern FrequencySensor vehicleSpeedSensor; tsOutputChannels->vssEdgeCounter = vehicleSpeedSensor.eventCounter; -#if HW_CHECK_MODE - tsOutputChannels->hasCriticalError = 1; -#else tsOutputChannels->hasCriticalError = hasFirmwareError(); -#endif // HW_CHECK_MODE tsOutputChannels->isWarnNow = engine->engineState.warnings.isWarningNow(); diff --git a/firmware/controllers/algo/engine.cpp b/firmware/controllers/algo/engine.cpp index 9efb0a46f8..902e47bffb 100644 --- a/firmware/controllers/algo/engine.cpp +++ b/firmware/controllers/algo/engine.cpp @@ -121,14 +121,6 @@ void Engine::updateTriggerWaveform() { #endif /* EFI_ENGINE_CONTROL && EFI_SHAFT_POSITION_INPUT */ } -#if ANALOG_HW_CHECK_MODE -static void assertCloseTo(const char* msg, float actual, float expected) { - if (actual < 0.95f * expected || actual > 1.05f * expected) { - firmwareError(OBD_PCM_Processor_Fault, "%s validation failed actual=%f vs expected=%f", msg, actual, expected); - } -} -#endif // ANALOG_HW_CHECK_MODE - void Engine::periodicSlowCallback() { ScopePerf perf(PE::EnginePeriodicSlowCallback); @@ -175,32 +167,6 @@ void Engine::periodicSlowCallback() { void baroLps25Update(); baroLps25Update(); #endif // EFI_PROD_CODE - -#if ANALOG_HW_CHECK_MODE - efiAssertVoid(OBD_PCM_Processor_Fault, isAdcChannelValid(engineConfiguration->clt.adcChannel), "No CLT setting"); - efitimesec_t secondsNow = getTimeNowS(); - -#if ! HW_CHECK_ALWAYS_STIMULATE - fail("HW_CHECK_ALWAYS_STIMULATE required to have self-stimulation") -#endif - - int hwCheckRpm = 204; - if (secondsNow > 2 && secondsNow < 180) { - assertCloseTo("RPM", Sensor::get(SensorType::Rpm).Value, hwCheckRpm); - } else if (!hasFirmwareError() && secondsNow > 180) { - static bool isHappyTest = false; - if (!isHappyTest) { - setTriggerEmulatorRPM(5 * hwCheckRpm); - efiPrintf("TEST PASSED"); - isHappyTest = true; - } - } - - assertCloseTo("clt", Sensor::getRaw(SensorType::Clt), 1.351f); - assertCloseTo("iat", Sensor::getRaw(SensorType::Iat), 2.245f); - assertCloseTo("aut1", Sensor::getRaw(SensorType::AuxTemp1), 2.750f); - assertCloseTo("aut2", Sensor::getRaw(SensorType::AuxTemp2), 3.176f); -#endif // ANALOG_HW_CHECK_MODE } /** diff --git a/firmware/controllers/engine_cycle/main_trigger_callback.cpp b/firmware/controllers/engine_cycle/main_trigger_callback.cpp index 461112b1df..08f94a4129 100644 --- a/firmware/controllers/engine_cycle/main_trigger_callback.cpp +++ b/firmware/controllers/engine_cycle/main_trigger_callback.cpp @@ -238,7 +238,6 @@ static void handleFuel(int rpm, efitick_t nowNt, float currentPhase, float nextP void mainTriggerCallback(uint32_t trgEventIndex, efitick_t edgeTimestamp, angle_t currentPhase, angle_t nextPhase) { ScopePerf perf(PE::MainTriggerCallback); -#if ! HW_CHECK_MODE if (hasFirmwareError()) { /** * In case on a major error we should not process any more events. @@ -246,7 +245,6 @@ void mainTriggerCallback(uint32_t trgEventIndex, efitick_t edgeTimestamp, angle_ */ return; } -#endif // HW_CHECK_MODE int rpm = engine->rpmCalculator.getCachedRpm(); if (rpm == 0) { diff --git a/firmware/controllers/flash_main.cpp b/firmware/controllers/flash_main.cpp index 5114c6b551..cd63a17157 100644 --- a/firmware/controllers/flash_main.cpp +++ b/firmware/controllers/flash_main.cpp @@ -294,21 +294,7 @@ static FlashState readConfiguration() { } void readFromFlash() { -#if HW_CHECK_MODE - /* - * getFlashAddr does device validation, we want validation to be invoked even while we are - * HW_CHECK_MODE mode where we would not need actual address - * todo: rename method to emphasis the fact of validation check? - */ - getFlashAddrFirstCopy(); - getFlashAddrSecondCopy(); - - resetConfigurationExt(DEFAULT_ENGINE_TYPE); - - FlashState result = FlashState::Ok; -#else FlashState result = readConfiguration(); -#endif switch (result) { case FlashState::CrcFailed: diff --git a/firmware/controllers/trigger/trigger_central.cpp b/firmware/controllers/trigger/trigger_central.cpp index 1495a05450..1cf9ed2a53 100644 --- a/firmware/controllers/trigger/trigger_central.cpp +++ b/firmware/controllers/trigger/trigger_central.cpp @@ -260,20 +260,6 @@ void hwHandleVvtCamSignal(TriggerValue front, efitick_t nowNt, int index) { warning(CUSTOM_VVT_MODE_NOT_SELECTED, "VVT: event on %d but no mode", camIndex); } -#if VR_HW_CHECK_MODE - // some boards do not have hardware VR input LEDs which makes such boards harder to validate - // from experience we know that assembly mistakes happen and quality control is required - extern ioportid_t criticalErrorLedPort; - extern ioportmask_t criticalErrorLedPin; - - for (int i = 0 ; i < 100 ; i++) { - // turning pin ON and busy-waiting a bit - palWritePad(criticalErrorLedPort, criticalErrorLedPin, 1); - } - - palWritePad(criticalErrorLedPort, criticalErrorLedPin, 0); -#endif // VR_HW_CHECK_MODE - const auto& vvtShape = tc->vvtShape[camIndex]; bool isVvtWithRealDecoder = vvtWithRealDecoder(engineConfiguration->vvtMode[camIndex]); @@ -404,24 +390,6 @@ uint32_t triggerMaxDuration = 0; void hwHandleShaftSignal(int signalIndex, bool isRising, efitick_t timestamp) { TriggerCentral *tc = getTriggerCentral(); ScopePerf perf(PE::HandleShaftSignal); -#if VR_HW_CHECK_MODE - // some boards do not have hardware VR input LEDs which makes such boards harder to validate - // from experience we know that assembly mistakes happen and quality control is required - extern ioportid_t criticalErrorLedPort; - extern ioportmask_t criticalErrorLedPin; - -#if HW_CHECK_ALWAYS_STIMULATE - disableTriggerStimulator(); -#endif // HW_CHECK_ALWAYS_STIMULATE - - - for (int i = 0 ; i < 100 ; i++) { - // turning pin ON and busy-waiting a bit - palWritePad(criticalErrorLedPort, criticalErrorLedPin, 1); - } - - palWritePad(criticalErrorLedPort, criticalErrorLedPin, 0); -#endif // VR_HW_CHECK_MODE if (tc->directSelfStimulation || !tc->hwTriggerInputEnabled) { // sensor noise + self-stim = loss of trigger sync diff --git a/firmware/rusefi.cpp b/firmware/rusefi.cpp index d4d279a81b..70f19a4b4f 100644 --- a/firmware/rusefi.cpp +++ b/firmware/rusefi.cpp @@ -268,12 +268,6 @@ void runRusEfiWithConfig() { startCanConsole(); #endif /* EFI_CAN_SERIAL */ -#if HW_CHECK_ALWAYS_STIMULATE - // we need a special binary for final assembly check. We cannot afford to require too much software or too many steps - // to be executed at the place of assembly - enableTriggerStimulator(); -#endif // HW_CHECK_ALWAYS_STIMULATE - #if EFI_LUA startLua(); #endif // EFI_LUA diff --git a/misc/jenkins/compile_other_versions/compile_and_upload.bat b/misc/jenkins/compile_other_versions/compile_and_upload.bat deleted file mode 100644 index ade38a12ec..0000000000 --- a/misc/jenkins/compile_other_versions/compile_and_upload.bat +++ /dev/null @@ -1,3 +0,0 @@ -@echo off -bash.exe misc\jenkins\compile_other_versions\compile.sh %1 %2 %3 %4 -bash.exe misc\jenkins\compile_other_versions\prepare_bundle.sh %1 %2 %3 %4 diff --git a/misc/jenkins/compile_other_versions/run.bat b/misc/jenkins/compile_other_versions/run.bat deleted file mode 100644 index bd6032ddf3..0000000000 --- a/misc/jenkins/compile_other_versions/run.bat +++ /dev/null @@ -1,97 +0,0 @@ -set script_name=run.bat -echo Entering %script_name% -echo "RUSEFI_BUILD_FTP_USER=%RUSEFI_BUILD_FTP_USER%" - -pwd - -call misc\jenkins\build_java_console.bat -if not exist java_console_binary/rusefi_console.jar exit -1 - -call misc\jenkins\build_simulator.bat -if not exist simulator/build/rusefi_simulator.exe exit -1 - -rem # -rem # see gen_config.sh where short<>long name dictionary is hard-coded -rem # - -call misc\jenkins\compile_other_versions\compile_and_upload.bat frankenso frankenso_na6 -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - -call misc\jenkins\compile_other_versions\compile_and_upload.bat kinetis kinetis -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 - -call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f4 rusefi_mre_f4.ini -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - -rem call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f4_slave rusefi_mre_f7.ini -rem IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -rem IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -rem pwd - -call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f4_hardware_QC_special_build rusefi_microrusefi.ini -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - -set f7_console_setting=firmware\config\boards\nucleo_f767\rusefi_console_properties.xml - -rem folter_name configuration_name [optional .ini file name] - -call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f7 rusefi_microrusefi.ini %f7_console_setting% -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - -rem call misc\jenkins\compile_other_versions\compile_and_upload.bat microrusefi mre_f7_test rusefi_microrusefi.ini %f7_console_setting% -rem IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -rem IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -rem pwd - -call misc\jenkins\compile_other_versions\compile_and_upload.bat prometheus prometheus_405 prometheus_405.ini -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - - -call misc\jenkins\compile_other_versions\compile_and_upload.bat prometheus prometheus_469 prometheus_469.ini -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - -call misc\jenkins\compile_other_versions\compile_and_upload.bat proteus proteus_f4 rusefi_proteus_f4.ini -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - -call misc\jenkins\compile_other_versions\compile_and_upload.bat proteus proteus_f7 rusefi_proteus_f7.ini -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - - -call misc\jenkins\compile_other_versions\compile_and_upload.bat nucleo_f767 stm32f767_nucleo no %f7_console_setting% -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - - -rem call misc\jenkins\compile_other_versions\compile_and_upload.bat nucleo_f767 stm32f767_osc no %f7_console_setting% -rem IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -rem IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -rem pwd - -call misc\jenkins\compile_other_versions\compile_and_upload.bat prometheus prometheus_405 rusefi_prometheus_405.ini -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd - - -call misc\jenkins\compile_other_versions\compile_and_upload.bat prometheus prometheus_469 rusefi_prometheus_469.ini -IF %ERRORLEVEL% NEQ 0 echo ERROR invoking compile_and_upload.bat -IF %ERRORLEVEL% NEQ 0 EXIT /B 1 -pwd diff --git a/simulator/simulator/efifeatures.h b/simulator/simulator/efifeatures.h index 562662ffd4..8a06b949ee 100644 --- a/simulator/simulator/efifeatures.h +++ b/simulator/simulator/efifeatures.h @@ -24,8 +24,6 @@ #define EFI_ENABLE_CRITICAL_ENGINE_STOP TRUE #define EFI_ENABLE_ENGINE_WARNING TRUE -#define HW_CHECK_MODE FALSE - #define SC_BUFFER_SIZE 4000 #define EFI_ACTIVE_CONFIGURATION_IN_FLASH FALSE