mirror of https://github.com/FOME-Tech/fome-fw.git
539 lines
12 KiB
C++
Executable File
539 lines
12 KiB
C++
Executable File
/**
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*
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* \file
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*
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* \brief This module contains NMC1000 UART protocol bus APIs implementation.
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include "common/include/nm_common.h"
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#ifdef CONF_WINC_USE_UART
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#include "driver/source/nmuart.h"
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#include "bus_wrapper/include/nm_bus_wrapper.h"
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#define HDR_SZ 12
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static uint8 get_cs(uint8* b, uint8 sz){
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int i;
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uint8 cs = 0;
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for(i = 0; i < sz; i++)
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cs ^= b[i];
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return cs;
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}
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/*
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* @fn nm_uart_sync_cmd
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* @brief Check COM Port
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* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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* @author Dina El Sissy
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* @date 13 AUG 2012
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* @version 1.0
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*/
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sint8 nm_uart_sync_cmd(void)
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{
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tstrNmUartDefault strUart;
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sint8 s8Ret = -1;
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uint8 b [HDR_SZ+1];
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uint8 rsz;
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uint8 retries = 1;
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/*read reg*/
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while (retries--)
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{
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b[0] = 0x12;
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rsz = 1;
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strUart.pu8Buf = b;
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strUart.u16Sz = 1;
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if (M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
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{
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strUart.u16Sz = rsz;
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b[0] = 0;
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// Pull all chars from buffer, we only care about the last
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while (M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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strUart.u16Sz = rsz;
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}
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if (b[0] == 0x5a)
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{
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s8Ret = 1; // found on-chip (no bridge)
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M2M_INFO("Built-in WINC1500 UART Found\n");
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}
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else if (b[0] == 0x5b)
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{
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s8Ret = 0; // found off-chip (std serial bridge)
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M2M_INFO("WINC1500 Serial Bridge Found\n");
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}
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else if (b[0] == 0x5c)
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{
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s8Ret = 0; // found of-chip (at cmd app serial bridge)
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M2M_INFO("WINC1500 Serial Bridge Found + AT CMD app Found\n");
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}
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else
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{
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continue;
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}
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break;
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}
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else
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{
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M2M_ERR("failed to send cfg bytes\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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return s8Ret;
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}
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sint8 nm_uart_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal)
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{
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tstrNmUartDefault strUart;
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sint8 s8Ret = M2M_SUCCESS;
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uint8 b [HDR_SZ+1];
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uint8 rsz;
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/*read reg*/
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b[0] = 0xa5;
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b[1] = 0;
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b[2] = 0;
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b[3] = 0;
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b[4] = 0;
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b[5] = (uint8)(u32Addr & 0x000000ff);
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b[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
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b[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
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b[8] = (uint8)((u32Addr & 0xff000000)>>24);
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b[9] = 0;
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b[10] = 0;
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b[11] = 0;
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b[12] = 0;
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b[2] = get_cs(&b[1],HDR_SZ);
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rsz = 4;
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strUart.pu8Buf = b;
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strUart.u16Sz = sizeof(b);
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if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
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{
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if(!nm_bus_get_chip_type())
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{
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strUart.u16Sz = 1;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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if(b[0] == 0xAC)
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{
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M2M_DBG("Successfully sent the command\n");
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strUart.u16Sz = rsz;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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else
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{
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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else
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{
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strUart.u16Sz = rsz;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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}
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else
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{
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M2M_ERR("failed to send cfg bytes\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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*pu32RetVal = ((uint32)b[0] << 24) | ((uint32)b[1] << 16) | ((uint32)b[2] << 8) | b[3];
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return s8Ret;
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}
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/*
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* @fn nm_uart_read_reg
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* @brief Read register
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* @param [in] u32Addr
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* Register address
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* @return Register value
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* @author Dina El Sissy
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* @date 13 AUG 2012
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* @version 1.0
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*/
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uint32 nm_uart_read_reg(uint32 u32Addr)
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{
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uint32 val;
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nm_uart_read_reg_with_ret(u32Addr , &val);
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return val;
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}
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/*
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* @fn nm_uart_write_reg
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* @brief write register
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* @param [in] u32Addr
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* Register address
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* @param [in] u32Val
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* Value to be written to the register
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* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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* @author Dina El Sissy
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* @date 13 AUG 2012
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* @version 1.0
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*/
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sint8 nm_uart_write_reg(uint32 u32Addr, uint32 u32Val)
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{
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tstrNmUartDefault strUart;
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sint8 s8Ret = M2M_SUCCESS;
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uint8 b[HDR_SZ+1];
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/*write reg*/
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b[0] = 0xa5;
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b[1] = 1;
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b[2] = 0;
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b[3] = 0;
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b[4] = 0;
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b[5] = (uint8)(u32Addr & 0x000000ff);
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b[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
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b[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
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b[8] = (uint8)((u32Addr & 0xff000000)>>24);
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b[9] = (uint8)(u32Val & 0x000000ff);
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b[10] = (uint8)((u32Val & 0x0000ff00)>>8);
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b[11] = (uint8)((u32Val & 0x00ff0000)>>16);
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b[12] = (uint8)((u32Val & 0xff000000)>>24);
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b[2] = get_cs(&b[1],HDR_SZ);
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get_cs(&b[1],HDR_SZ);
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strUart.pu8Buf = b;
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strUart.u16Sz = sizeof(b);
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
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{
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M2M_ERR("write error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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else
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{
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if(!nm_bus_get_chip_type())
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{
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//check for the ack from the SAMD21 for the packet reception.
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strUart.u16Sz = 1;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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if(b[0] == 0xAC)
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{
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M2M_DBG("Successfully sent the reg write command\n");
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}
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else
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{
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M2M_ERR("write error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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}
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return s8Ret;
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}
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/**
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* @fn nm_uart_read_block
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* @brief Read block of data
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* @param [in] u32Addr
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* Start address
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* @param [out] puBuf
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* Pointer to a buffer used to return the read data
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* @param [in] u16Sz
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* Number of bytes to read. The buffer size must be >= u16Sz
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* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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* @author Dina El Sissy
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* @date 13 AUG 2012
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* @version 1.0
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*/
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sint8 nm_uart_read_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz)
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{
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tstrNmUartDefault strUart;
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sint8 s8Ret = M2M_SUCCESS;
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uint8 au8Buf[HDR_SZ+1];
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au8Buf[0] = 0xa5;
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au8Buf[1] = 2;
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au8Buf[2] = 0;
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au8Buf[3] = (uint8)(u16Sz & 0x00ff);
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au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8);
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au8Buf[5] = (uint8)(u32Addr & 0x000000ff);
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au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
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au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
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au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24);
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au8Buf[9] = 0;
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au8Buf[10] = 0;
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au8Buf[11] = 0;
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au8Buf[12] = 0;
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au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ);
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strUart.pu8Buf = au8Buf;
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strUart.u16Sz = sizeof(au8Buf);
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
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{
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M2M_ERR("write error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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else
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{
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if(!nm_bus_get_chip_type())
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{
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//check for the ack from the SAMD21 for the packet reception.
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strUart.u16Sz = 1;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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if(au8Buf[0] == 0xAC)
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{
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M2M_DBG("Successfully sent the block read command\n");
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strUart.pu8Buf = pu8Buf;
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strUart.u16Sz = u16Sz;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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M2M_ERR("read error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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else
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{
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M2M_ERR("write error (Error sending the block read command)\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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else
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{
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strUart.pu8Buf = pu8Buf;
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strUart.u16Sz = u16Sz;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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M2M_ERR("read error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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}
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return s8Ret;
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}
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/**
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* @fn nm_uart_write_block
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* @brief Write block of data
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* @param [in] u32Addr
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* Start address
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* @param [in] puBuf
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* Pointer to the buffer holding the data to be written
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* @param [in] u16Sz
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* Number of bytes to write. The buffer size must be >= u16Sz
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* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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* @author Dina El Sissy
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* @date 13 AUG 2012
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* @version 1.0
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*/
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sint8 nm_uart_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
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{
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tstrNmUartDefault strUart;
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sint8 s8Ret = M2M_SUCCESS;
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static uint8 au8Buf[HDR_SZ+1];
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au8Buf[0] = 0xa5;
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au8Buf[1] = 3;
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au8Buf[2] = 0;
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au8Buf[3] = (uint8)(u16Sz & 0x00ff);
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au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8);
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au8Buf[5] = (uint8)(u32Addr & 0x000000ff);
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au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
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au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
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au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24);
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au8Buf[9] = 0;
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au8Buf[10] = 0;
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au8Buf[11] = 0;
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au8Buf[12] = 0;
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au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ);
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strUart.pu8Buf = au8Buf;
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strUart.u16Sz = sizeof(au8Buf);
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
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{
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M2M_ERR("write error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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else
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{
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if(!nm_bus_get_chip_type())
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{
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//check for the ack from the SAMD21 for the packet reception.
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strUart.u16Sz = 1;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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if(au8Buf[0] == 0xAC)
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{
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M2M_DBG("Successfully sent the block Write command\n");
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strUart.pu8Buf = puBuf;
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strUart.u16Sz = u16Sz;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
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{
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M2M_ERR("write error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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else
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{
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//check for the ack from the SAMD21 for the payload reception.
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strUart.pu8Buf = au8Buf;
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strUart.u16Sz = 1;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
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{
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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if(au8Buf[0] == 0xAC)
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{
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M2M_DBG("Successfully sent the data payload\n");
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}
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else
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{
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M2M_ERR("write error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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}
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else
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{
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M2M_ERR("write error (Error sending the block write command)\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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else
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{
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strUart.pu8Buf = puBuf;
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strUart.u16Sz = u16Sz;
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if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
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{
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M2M_ERR("write error\n");
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s8Ret = M2M_ERR_BUS_FAIL;
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}
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}
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}
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return s8Ret;
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}
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/**
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* @fn nm_uart_reconfigure
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* @brief Reconfigures the UART interface
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* @param [in] ptr
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* Pointer to a DWORD containing baudrate at this moment.
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* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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* @author Viswanathan Murugesan
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* @date 22 OCT 2014
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* @version 1.0
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*/
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sint8 nm_uart_reconfigure(void *ptr)
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{
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tstrNmUartDefault strUart;
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sint8 s8Ret = M2M_SUCCESS;
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uint8 b[HDR_SZ+1];
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/*write reg*/
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b[0] = 0xa5;
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b[1] = 5;
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b[2] = 0;
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b[3] = 0;
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b[4] = 0;
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b[5] = 0;
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b[6] = 0;
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b[7] = 0;
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b[8] = 0;
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b[9] = (uint8)((*(unsigned long *)ptr) & 0x000000ff);
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|
b[10] = (uint8)(((*(unsigned long *)ptr) & 0x0000ff00)>>8);
|
|
b[11] = (uint8)(((*(unsigned long *)ptr) & 0x00ff0000)>>16);
|
|
b[12] = (uint8)(((*(unsigned long *)ptr) & 0xff000000)>>24);
|
|
|
|
b[2] = get_cs(&b[1],HDR_SZ);
|
|
|
|
get_cs(&b[1],HDR_SZ);
|
|
|
|
strUart.pu8Buf = b;
|
|
strUart.u16Sz = sizeof(b);
|
|
|
|
if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
|
|
{
|
|
M2M_ERR("write error\n");
|
|
s8Ret = M2M_ERR_BUS_FAIL;
|
|
}
|
|
else
|
|
{
|
|
if(!nm_bus_get_chip_type())
|
|
{
|
|
//check for the ack from the SAMD21 for the packet reception.
|
|
strUart.u16Sz = 1;
|
|
if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
|
|
{
|
|
s8Ret = M2M_ERR_BUS_FAIL;
|
|
}
|
|
if(b[0] == 0xAC)
|
|
{
|
|
M2M_DBG("Successfully sent the UART reconfigure command\n");
|
|
}
|
|
else
|
|
{
|
|
M2M_ERR("write error\n");
|
|
s8Ret = M2M_ERR_BUS_FAIL;
|
|
}
|
|
}
|
|
}
|
|
|
|
return s8Ret;
|
|
}
|
|
#endif
|
|
/* EOF */
|