mirror of https://github.com/FOME-Tech/fome-fw.git
203 lines
13 KiB
Plaintext
203 lines
13 KiB
Plaintext
********************************************************************************
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* Example Code
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*
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* Copyright(C) 2019 NXP Semiconductors
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* NXP Semiconductors Confidential and Proprietary
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*
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* NXP products. This software is supplied "AS IS" without any warranties
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* of any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights
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* under any patent, copyright, mask work right, or any other intellectual
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* property rights in or to any products. NXP Semiconductors reserves the
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* right to make changes in the software without notification. NXP
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* Semiconductors also makes no representation or warranty that such
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* application will be suitable for the specified use without further testing
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* or modification.
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*
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* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT,
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* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL
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* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY
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* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST
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* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED
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* BY LAW. NXP SEMICONDUCTOR???S TOTAL LIABILITY FOR ALL COSTS, DAMAGES,
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* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS
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* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
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*
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided
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* that it is used in conjunction with NXP Semiconductors devices. This
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* copyright, permission, and disclaimer notice must appear in all copies
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* of this code.
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********************************************************************************
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#include "dram1.def";
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* ### Channel 1 - uCore0 controls the injectors 1 and 2 ###
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* ### Variables declaration ###
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* Note: The data are stored into the dataRAM of the channel 1.
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* Note: The Thold_tot variable defines the current profile time out.
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* The active STARTx pin is expected to toggle in is low state before this time out.
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* ### Initialization phase ###
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init0: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1
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ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1
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ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2
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cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
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* ### Idle phase- the uPC loops here until start signal is present ###
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idle0: cwer CheckStart start row2; * Define entry table for high start pin
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stoc on sssc; * Turn ON offset compensation
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WaitLoop: wait row2; * uPC is stuck here for almost the whole idle time
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CheckStart: joslr inj1_start start1; * Jump to inj1 if start 1 is high
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joslr inj2_start start2; * Jump to inj2 if start 2 is high
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jmpr WaitLoop;
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* ### Shortcuts definition per the injector to be actuated ###
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inj1_start: dfsct hs1 hs2 ls1; * Set the 3 shortcuts: VBAT, VBOOST, LS
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jmpr boost0; * Jump to launch phase
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inj2_start: dfsct hs1 hs2 ls2; * Set the 3 shortcuts: VBAT, VBOOST, LS
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jmpr boost0; * Jump to launch phase
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* ### Launch phase enable boost ###
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boost0: stoc off sssc; * Turn OFF offset compensation
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bias all on; * Enable all biasing structures, kept ON even during actuation
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load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
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cwer peak0 ocur row2; * Jump to peak phase when current is over threshold
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stf low b0; * set flag0 low to force the DC-DC converter in idle mode
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stos off on on; * Turn VBAT off, BOOST on, LS on
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wait row12; * Wait for one of the previously defined conditions
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* ### Peak phase continue on Vbat ###
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peak0: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
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load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
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cwer bypass0 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
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cwer peak_on0 tc2 row3; * Jump to peak_on when tc2 reaches end of count
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cwer peak_off0 ocur row4; * Jump to peak_off when current is over threshold
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stf high b0; * set flag0 high to release the DC-DC converter idle mode
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peak_on0: stos on off on; * Turn VBAT on, BOOST off, LS on
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wait row124; * Wait for one of the previously defined conditions
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peak_off0: ldcd rst ofs keep keep Tpeak_off c2; * Load in the counter 2 the length of the peak_off phase
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stos off off on; * Turn VBAT off, BOOST off, LS on
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wait row123; * Wait for one of the previously defined conditions
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* ### Bypass phase ###
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bypass0: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase
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stos off off off; * Turn VBAT off, BOOST off, LS off
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cwer hold0 tc3 row4; * Jump to hold when tc3 reaches end of count
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wait row14; * Wait for one of the previously defined conditions
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* ### Hold phase on Vbat ###
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hold0: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2
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load Ihold dac_sssc _ofs; * Load the hold current threshold in the DAC
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cwer eoinj0 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
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cwer hold_on0 tc2 row3; * Jump to hold_on when tc2 reaches end of count
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cwer hold_off0 ocur row4; * Jump to hold_off when current is over threshold
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hold_on0: stos on off on; * Turn VBAT on, BOOST off, LS on
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wait row124; * Wait for one of the previously defined conditions
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hold_off0: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hold_off phase in counter 1
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stos off off on; * Turn VBAT off, BOOST off, LS on
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wait row123; * Wait for one of the previously defined conditions
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* ### End of injection phase ###
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eoinj0: stos off off off; * Turn VBAT off, BOOST off, LS off
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stf high b0; * set flag0 to high to release the DC-DC converter idle mode
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jmpf jr2; * Jump back to idle phase
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* ### End of Channel 1 - uCore0 code ###
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*********************************************************************************
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* ### Channel 1 - uCore1 controls the injectors 3 and 4 ###
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* ### Variables declaration ###
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* Note: The data that defines the profiles are shared between the two microcores.
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* ### Initialization phase ###
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init1: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1
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ldjr1 eoinj1; * Load the eoinj line label Code RAM address into the register jr1
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ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2
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cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
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* ### Idle phase- the uPC loops here until start signal is present ###
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idle1: cwer CheckStart1 start row2; * Define entry table for high start pin
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stoc on sssc; * Turn ON offset compensation
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WaitLoop1: wait row2; * uPC is stuck here for almost the whole idle time
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CheckStart1:joslr inj3_start start3; * Jump to inj1 if start 1 is high
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joslr inj4_start start4; * Jump to inj2 if start 2 is high
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jmpr WaitLoop1;
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* ### Shortcuts definition per the injector to be actuated ###
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inj3_start: dfsct hs3 hs4 ls3; * Set the 3 shortcuts: VBAT, VBOOST, LS
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jmpr boost1; * Jump to launch phase
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inj4_start: dfsct hs3 hs4 ls4; * Set the 3 shortcuts: VBAT, VBOOST, LS
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jmpr boost1; * Jump to launch phase
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* ### Launch phase enable boost ###
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boost1: stoc off sssc; * Turn OFF offset compensation
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load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
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cwer peak1 ocur row2; * Jump to peak phase when current is over threshold
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stf low b0; * set flag0 low to force the DC-DC converter in idle mode
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stos off on on; * Turn VBAT off, BOOST on, LS on
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wait row12; * Wait for one of the previously defined conditions
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* ### Peak phase continue on Vbat ###
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peak1: ldcd rst _ofs keep keep Tpeak_tot c1; * Load the length of the total peak phase in counter 1
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load Ipeak dac_sssc _ofs; * Load the peak current threshold in the current DAC
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cwer bypass1 tc1 row2; * Jump to bypass phase when tc1 reaches end of count
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cwer peak_on1 tc2 row3; * Jump to peak_on when tc2 reaches end of count
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cwer peak_off1 ocur row4; * Jump to peak_off when current is over threshold
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stf high b0; * set flag0 high to release the DC-DC converter idle mode
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peak_on1: stos on off on; * Turn VBAT on, BOOST off, LS on
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wait row124; * Wait for one of the previously defined conditions
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peak_off1: ldcd rst ofs keep keep Tpeak_off c2; * Load in the counter 2 the length of the peak_off phase
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stos off off on; * Turn VBAT off, BOOST off, LS on
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wait row123; * Wait for one of the previously defined conditions
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* ### Bypass phase ###
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bypass1: ldcd rst ofs keep keep Tbypass c3; * Load in the counter 3 the length of the off_phase phase
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stos off off off; * Turn VBAT off, BOOST off, LS off
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cwer hold1 tc3 row4; * Jump to hold when tc3 reaches end of count
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wait row14; * Wait for one of the previously defined conditions
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* ### Hold phase on Vbat ###
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hold1: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2
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load Ihold dac_sssc _ofs; * Load the hold current threshold in the DAC
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cwer eoinj1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
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cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count
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cwer hold_off1 ocur row4; * Jump to hold_off when current is over threshold
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hold_on1: stos on off on; * Turn VBAT on, BOOST off, LS on
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wait row124; * Wait for one of the previously defined conditions
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hold_off1: ldcd rst _ofs keep keep Thold_off c2; * Load the length of the hold_off phase in counter 1
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stos off off on; * Turn VBAT off, BOOST off, LS on
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wait row123; * Wait for one of the previously defined conditions
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* ### End of injection phase ###
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eoinj1: stos off off off; * Turn VBAT off, BOOST off, LS off
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stf high b0; * set flag0 to high to release the DC-DC converter idle mode
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jmpf jr2; * Jump back to idle phase
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* ### End of Channel 1 - uCore1 code ###
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