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Refs #980. Merging branch with AURIX TriCore TC3 port development back into the trunk. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@998 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2022-11-07 17:40:46 +00:00
parent 45a94641d2
commit a858a21bad
1129 changed files with 932815 additions and 0 deletions
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27
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/.ads/backup-libraries.json Normal file
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{
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{
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"to": "/Lcf_Tasking_Tricore_Tc.lsl"
},
{
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23
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/.ads/clean-libraries.json Normal file
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{
"name" : "Clean AURIX Project",
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{
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{
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}

131
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/.ads/install-libraries.json Normal file
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{
"name" : "Install AURIX Libraries and Linker scripts",
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{"variable": "device", "from": "TC21xL_A-Step", "to": "TC21A"},
{"variable": "device", "from": "TC22xL_A-Step", "to": "TC22A"},
{"variable": "device", "from": "TC23xLP_A-Step", "to": "TC23A"},
{"variable": "device", "from": "TC23xLA/LX_A-Step", "to": "TC23A"},
{"variable": "device", "from": "TC26xD_B-Step", "to": "TC26B"},
{"variable": "device", "from": "TC26xDA_B-Step", "to": "TC26B"},
{"variable": "device", "from": "TC27xTP_D-Step", "to": "TC27D"},
{"variable": "device", "from": "TC27xTF_D-Step", "to": "TC27D"},
{"variable": "device", "from": "TC29xTP_B-Step", "to": "TC29B"},
{"variable": "device", "from": "TC29xTA/TX_B-Step", "to": "TC29B"},
{"variable": "device", "from": "TC39xXX_B-Step", "to": "TC39B"},
{"variable": "device", "from": "TC39xXP_B-Step", "to": "TC39B"},
{"variable": "device", "from": "TC38xQP_A-Step", "to": "TC38A"},
{"variable": "device", "from": "TC37xTX_A-Step", "to": "TC37AED"},
{"variable": "device", "from": "TC37xTP_A-Step", "to": "TC37A"},
{"variable": "device", "from": "TC36xDP_A-Step", "to": "TC36A"},
{"variable": "device", "from": "TC35xTA_A-Step", "to": "TC35A"},
{"variable": "device", "from": "TC33xLP_A-Step", "to": "TC33A"},
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12
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/.ads/package.json Normal file
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17
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/.ads/rollback-libraries.json Normal file
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261
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/.cproject Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
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</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
<project-mappings>
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.dbg.ctc.clanguage"/>
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<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="External GCC - Debug">
<resource resourceType="PROJECT" workspacePath="/Boot"/>
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<configuration configurationName="External GCC - Release">
<resource resourceType="PROJECT" workspacePath="/Boot"/>
</configuration>
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/Boot"/>
</configuration>
<configuration configurationName="Release">
<resource resourceType="PROJECT" workspacePath="/Boot"/>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
</cproject>

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>Boot</name>
<comment></comment>
<projects>
</projects>
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AURIX-LIBRARY-PATH=/Libraries/iLLD\#/Libraries/Infra\#/Libraries/Service\#/Libraries/.ads
DEVICE-ID=TC37A
DEVICE-ID-FULL=TC37xTP_A-Step
ILLD-SET=full
IncludesAutodiscovery=true
LIBRARIES-ROOT-PATH=Libraries
NEVER-EXCLUDE-FROM-BUILD=/Configurations\#/Configurations/Debug\#/Libraries/iLLD/TC37A/Tricore/Cpu/CStart\#/Libraries/iLLD/TC37A/Tricore/Cpu/Trap
PROJECT-VERSION=1.0
aurixDevice=TC37xTP_A-Step
aurixPlatform=KIT_A2G_TC375_LITE
eclipse.preferences.version=1

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doxygen/doxygen_new_line_after_brief=true
doxygen/doxygen_use_brief_tag=false
doxygen/doxygen_use_javadoc_tags=true
doxygen/doxygen_use_pre_tag=false
doxygen/doxygen_use_structural_commands=false
eclipse.preferences.version=1

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/************************************************************************************//**
* \file Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/App/app.c
* \brief Bootloader application source file.
* \ingroup Boot_TRICORE_TC3_TC375_Lite_Kit_ADS
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2022 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "IfxPort.h" /* GPIO driver */
#include "IfxAsclin.h" /* ASCLIN basic driver */
#include "IfxCan.h" /* MSMCAN basic driver */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
/************************************************************************************//**
** \brief Initializes the bootloader application. Should be called once during
** software program initialization.
** \return none.
**
****************************************************************************************/
void AppInit(void)
{
/* Initialize the microcontroller. */
Init();
/* Initialize the bootloader */
BootInit();
} /*** end of AppInit ***/
/************************************************************************************//**
** \brief Task function of the bootloader application. Should be called continuously
** in the program loop.
** \return none.
**
****************************************************************************************/
void AppTask(void)
{
/* Run the bootloader task. */
BootTask();
} /*** end of AppTask ***/
/************************************************************************************//**
** \brief Initializes the microcontroller.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
/* Configure the LED GPIO pin P00.5. */
IfxPort_setPinModeOutput(&MODULE_P00, 5U, IfxPort_OutputMode_pushPull,
IfxPort_OutputIdx_general);
/* Configure the pushbutton GPIO pin P00.7. */
IfxPort_setPinMode(&MODULE_P00, 7U, IfxPort_Mode_inputPullUp);
#if (BOOT_COM_RS232_ENABLE > 0)
/* Enable the ASCLIN0 module. */
IfxAsclin_enableModule(&MODULE_ASCLIN0);
/* Disable the clock before configuring the GPIO pins. */
IfxAsclin_setClockSource(&MODULE_ASCLIN0, IfxAsclin_ClockSource_noClock);
/* Configure the ASCLIN0 GPIO pins P14.1 Rx and P14.0 Tx. */
IfxAsclin_initRxPin(&IfxAsclin0_RXA_P14_1_IN, IfxPort_InputMode_pullUp,
IfxPort_PadDriver_cmosAutomotiveSpeed1);
IfxAsclin_initTxPin(&IfxAsclin0_TX_P14_0_OUT, IfxPort_OutputMode_pushPull,
IfxPort_PadDriver_cmosAutomotiveSpeed1);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* Configure the STBY GPIO pin P20.6 as a digital output. */
IfxPort_setPinModeOutput(&MODULE_P20, 6U, IfxPort_OutputMode_pushPull,
IfxPort_OutputIdx_general);
/* Switch the CAN transceiver to normal mode by setting the STBY GPIO pin logic low. */
IfxPort_setPinLow(&MODULE_P20, 6U);
/* Enable the MODULE_CAN0 module. */
IfxCan_enableModule(&MODULE_CAN0);
/* Configure MCMCAN0 GPIO pins P20.8 Tx and P20.7 Rx (node 0). */
IfxCan_Node_initTxPin(&IfxCan_TXD00_P20_8_OUT, IfxPort_OutputMode_pushPull,
IfxPort_PadDriver_cmosAutomotiveSpeed1);
IfxCan_Node_initRxPin(&MODULE_CAN0.N[IfxCan_NodeId_0], &IfxCan_RXD00B_P20_7_IN,
IfxPort_InputMode_pullUp,
IfxPort_PadDriver_cmosAutomotiveSpeed1);
#endif
} /*** end of Init ***/
/*********************************** end of app.c **************************************/

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/************************************************************************************//**
* \file Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/App/app.h
* \brief Bootloader application header file.
* \ingroup Boot_TRICORE_TC3_TC375_Lite_Kit_ADS
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2022 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef APP_H
#define APP_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void AppInit(void);
void AppTask(void);
#endif /* APP_H */
/*********************************** end of app.h **************************************/

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/************************************************************************************//**
* \file Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/App/blt_conf.h
* \brief Bootloader configuration header file.
* \ingroup Boot_TRICORE_TC3_TC375_Lite_Kit_ADS
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2022 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BLT_CONF_H
#define BLT_CONF_H
/****************************************************************************************
* C P U D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* To properly initialize the baudrate clocks of the communication interface, typically
* the speed of the crystal oscillator and/or the speed at which the system runs is
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
* little endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
/** \brief Frequency of the external crystal oscillator. */
#define BOOT_CPU_XTAL_SPEED_KHZ (20000)
/** \brief Desired system speed. */
#define BOOT_CPU_SYSTEM_SPEED_KHZ (300000)
/** \brief Motorola or Intel style byte ordering. */
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
/** \brief Enable/disable hook function call right before user program start. */
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by
* OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
/* The RS232 communication interface is selected by setting the BOOT_COM_RS232_ENABLE
* configurable to 1. Configurable BOOT_COM_RS232_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission
* and reception is set through BOOT_COM_RS232_TX_MAX_DATA and BOOT_COM_RS232_RX_MAX_DATA,
* respectively. It is common for a microcontroller to have more than 1 UART interface
* on board. The zero-based BOOT_COM_RS232_CHANNEL_INDEX selects the UART interface.
*
*/
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_RS232_ENABLE (1)
/** \brief Configure the desired communication speed. */
#define BOOT_COM_RS232_BAUDRATE (57600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_RS232_TX_MAX_DATA (129)
/** \brief Configure number of bytes in the host->target data packet. */
#define BOOT_COM_RS232_RX_MAX_DATA (129)
/** \brief Select the desired UART peripheral as a zero based index. */
#define BOOT_COM_RS232_CHANNEL_INDEX (0)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/
/* It is possible to implement an application specific method to force the bootloader to
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
* situations where the user program does not run properly and therefore cannot
* reactivate the bootloader. By enabling these hook functions, the application can
* implement the backdoor, which overrides the default backdoor entry that is programmed
* into the bootloader. When desired for security purposes, these hook functions can
* also be implemented in a way that disables the backdoor entry altogether.
*/
/** \brief Enable/disable the backdoor override hook functions. */
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The NVM driver typically supports erase and program operations of the internal memory
* present on the microcontroller. Through these hook functions the NVM driver can be
* extended to support additional memory types such as external flash memory and serial
* eeproms. The size of the internal memory in kilobytes is specified with configurable
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
* be overridden with a application specific method by enabling configuration switch
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
*/
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
#define BOOT_NVM_HOOKS_ENABLE (0)
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
#define BOOT_NVM_SIZE_KB (6144)
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
/****************************************************************************************
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The COP driver cannot be configured internally in the bootloader, because its use
* and configuration is application specific. The bootloader does need to service the
* watchdog in case it is used. When the application requires the use of a watchdog,
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
* hook functions.
*/
/** \brief Enable/disable the hook functions for controlling the watchdog. */
#define BOOT_COP_HOOKS_ENABLE (1)
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
****************************************************************************************/
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
* operations can be performed, access to this resource need to be unlocked.
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
* implements the unlocking algorithm. The demo programs are configured for the (simple)
* algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
* customized to your needs.
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
* a key, which is also a byte array, and sends this back to the bootloader. The
* bootloader then verifies this key to determine if programming and erase operations are
* permitted.
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
* are called by the bootloader to obtain the seed and to verify the key, respectively.
*/
#define BOOT_XCP_SEED_KEY_ENABLE (0)
#endif /* BLT_CONF_H */
/*********************************** end of blt_conf.h *********************************/

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/************************************************************************************//**
* \file Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/App/hooks.c
* \brief Bootloader callback source file.
* \ingroup Boot_TRICORE_TC3_TC375_Lite_Kit_ADS
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2022 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* LED driver header */
#include "IfxPort.h" /* GPIO driver */
/****************************************************************************************
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Initializes the backdoor entry option.
** \return none.
**
****************************************************************************************/
void BackDoorInitHook(void)
{
} /*** end of BackDoorInitHook ***/
/************************************************************************************//**
** \brief Checks if a backdoor entry is requested.
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool BackDoorEntryHook(void)
{
/* default implementation always activates the bootloader after a reset */
return BLT_TRUE;
} /*** end of BackDoorEntryHook ***/
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/************************************************************************************//**
** \brief Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* additional and optional backdoor entry through the pushbutton on the board. to
* force the bootloader to stay active after reset, keep it pressed during reset.
*/
if (IfxPort_getPinState(&MODULE_P00, 7U) == 0U)
{
/* pushbutton pressed, so do not start the user program and keep the
* bootloader active instead.
*/
return BLT_FALSE;
}
/* clean up the LED driver */
LedBlinkExit();
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_COP_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** initialization routine. It can be used to configure and enable the
** watchdog.
** \return none.
**
****************************************************************************************/
void CopInitHook(void)
{
/* this function is called upon initialization. might as well use it to initialize
* the LED driver. It is kind of a visual watchdog anyways.
*/
LedBlinkInit(100);
} /*** end of CopInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** service routine. This gets called upon initialization and during
** potential long lasting loops and routine. It can be used to service
** the watchdog to prevent a watchdog reset.
** \return none.
**
****************************************************************************************/
void CopServiceHook(void)
{
/* run the LED blink task. this is a better place to do it than in the main() program
* loop. certain operations such as flash erase can take a long time, which would cause
* a blink interval to be skipped. this function is also called during such operations,
* so no blink intervals will be skipped when calling the LED blink task here.
*/
LedBlinkTask();
} /*** end of CopServiceHook ***/
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the start of the internal NVM driver
** initialization routine.
** \return none.
**
****************************************************************************************/
void NvmInitHook(void)
{
} /*** end of NvmInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of a firmware update to reinitialize
** the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmReinitHook(void)
{
} /*** end of NvmReinitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver write
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
** been written yet.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmWriteHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver erase
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
** hasn't been erased yet.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmEraseHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the NVM programming session.
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDoneHook(void)
{
return BLT_TRUE;
} /*** end of NvmDoneHook ***/
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksumHook(void)
{
return BLT_TRUE;
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Writes a checksum of the user program to non-volatile memory. This is
** performed once the entire user program has been programmed. Through
** the checksum, the bootloader can check if a valid user programming is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWriteChecksumHook(void)
{
return BLT_TRUE;
}
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
/************************************************************************************//**
** \brief Provides a seed to the XCP master that will be used for the key
** generation when the master attempts to unlock the specified resource.
** Called by the GET_SEED command.
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
** \param seed Pointer to byte buffer wher the seed will be stored.
** \return Length of the seed in bytes.
**
****************************************************************************************/
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
{
/* request seed for unlocking ProGraMming resource */
if ((resource & XCP_RES_PGM) != 0)
{
seed[0] = 0x55;
}
/* return seed length */
return 1;
} /*** end of XcpGetSeedHook ***/
/************************************************************************************//**
** \brief Called by the UNLOCK command and checks if the key to unlock the
** specified resource was correct. If so, then the resource protection
** will be removed.
** \param resource resource to unlock (XCP_RES_XXX).
** \param key pointer to the byte buffer holding the key.
** \param len length of the key in bytes.
** \return 1 if the key was correct, 0 otherwise.
**
****************************************************************************************/
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
{
/* suppress compiler warning for unused parameter */
len = len;
/* the example key algorithm in "libseednkey.dll" works as follows:
* - PGM will be unlocked if key = seed - 1
*/
/* check key for unlocking ProGraMming resource */
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
{
/* correct key received for unlocking PGM resource */
return 1;
}
/* still here so key incorrect */
return 0;
} /*** end of XcpVerifyKeyHook ***/
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
/*********************************** end of hooks.c ************************************/

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/************************************************************************************//**
* \file Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/App/led.c
* \brief LED driver source file.
* \ingroup Boot_TRICORE_TC3_TC375_Lite_Kit_ADS
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2022 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* module header */
#include "IfxPort.h" /* GPIO driver */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Holds the desired LED blink interval time. */
static blt_int16u ledBlinkIntervalMs;
/************************************************************************************//**
** \brief Initializes the LED blink driver.
** \param interval_ms Specifies the desired LED blink interval time in milliseconds.
** \return none.
**
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms)
{
/* make sure the LED is turned off by default. Note that it is low active */
IfxPort_setPinHigh(&MODULE_P00, 5U);
/* store the interval time between LED toggles */
ledBlinkIntervalMs = interval_ms;
} /*** end of LedBlinkInit ***/
/************************************************************************************//**
** \brief Task function for blinking the LED as a fixed timer interval.
** \return none.
**
****************************************************************************************/
void LedBlinkTask(void)
{
static blt_bool ledOn = BLT_FALSE;
static blt_int32u nextBlinkEvent = 0;
/* check for blink event */
if (TimerGet() >= nextBlinkEvent)
{
/* toggle the LED state */
if (ledOn == BLT_FALSE)
{
ledOn = BLT_TRUE;
/* Turn the LED on. */
IfxPort_setPinLow(&MODULE_P00, 5U);
}
else
{
ledOn = BLT_FALSE;
/* Turn the LED off. */
IfxPort_setPinHigh(&MODULE_P00, 5U);
}
/* schedule the next blink event */
nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
}
} /*** end of LedBlinkTask ***/
/************************************************************************************//**
** \brief Cleans up the LED blink driver. This is intended to be used upon program
** exit.
** \return none.
**
****************************************************************************************/
void LedBlinkExit(void)
{
/* Turn the LED off. */
IfxPort_setPinHigh(&MODULE_P00, 5U);
} /*** end of LedBlinkExit ***/
/*********************************** end of led.c **************************************/

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/************************************************************************************//**
* \file Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/App/led.h
* \brief LED driver header file.
* \ingroup Boot_TRICORE_TC3_TC375_Lite_Kit_ADS
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2022 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms);
void LedBlinkTask(void);
void LedBlinkExit(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="Universal Debug Access Server"/>
<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="TC37x"/>
<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
<booleanAttribute key="com.tasking.debug.cdt.core.FLASH_ALLOW_CUSTOMIZATION" value="false"/>
<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
<booleanAttribute key="com.tasking.debug.cdt.core.INIT_TARGET" value="false"/>
<booleanAttribute key="com.tasking.debug.cdt.core.INTERRUPT_AWARE_STEPPING" value="false"/>
<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="Generic Infineon AURIX Board"/>
<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
<stringAttribute key="com.tasking.debug.cdt.core.global_variables" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#13;&#10;&lt;global_variables/&gt;"/>
<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
<stringAttribute key="com.tasking.debug.cdt.core.pins" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#13;&#10;&lt;pins/&gt;"/>
<stringAttribute key="debugger_configuration.debug_instrument_module" value="gdi2mcdtc"/>
<stringAttribute key="debugger_configuration.gdi.DiGdiInitIO" value="tcpip"/>
<stringAttribute key="debugger_configuration.gdi.DiGdiInitIO.tcpip.host" value="localhost"/>
<stringAttribute key="debugger_configuration.gdi.DiGdiInitIO.tcpip.port" value="23"/>
<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value=""/>
<stringAttribute key="debugger_configuration.gdi.resource.AccessPort" value="JTAG0"/>
<stringAttribute key="debugger_configuration.gdi.resource.DASserver" value="UDAS"/>
<stringAttribute key="debugger_configuration.gdi.resource.DasTimeOut" value="0x4000"/>
<stringAttribute key="debugger_configuration.gdi.resource.Frequency" value="30000000"/>
<stringAttribute key="debugger_configuration.gdi.resource.TerminateServer" value="1"/>
<stringAttribute key="debugger_configuration.gdi.resource.gdi2mcd.reset.class_vector" value="0x1"/>
<stringAttribute key="debugger_configuration.gdi.resource.user.ConnectedServerName" value="DAS JDS AURIX LITE KIT V2.0 (TC375) LK6O9N31"/>
<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
<stringAttribute key="debugger_configuration.goto_label" value="core0_main"/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="dwn"/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="false"/>
<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${build_config}\openblt_tc375.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="Boot"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/Boot"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
</launchConfiguration>

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/**************************************************************************
** *
** FILE : sync_on_halt.c *
** *
** DESCRIPTION : *
** Derivative-specific code that is run, every time the target *
** halts, to synchronize the target and the debugger. *
** *
** This code is linked in by default. At the risk of debugging *
** problems resulting from e.g. cache incoherence, it can be *
** left out by right-clicking on the file in the C/C++ Projects *
** view and selecting "Exclude from build...". *
** *
** If a user-defined TriCore processor is being used, this file *
** may have to be adapted. *
** *
** Copyright 1996-2019 TASKING BV *
** *
**************************************************************************/
#if __TASKING__ == 1
#include <stddef.h>
#pragma nomisrac
/* Code compaction, for example, must be avoided because this creates
* function calls and the CSA chain may not be initialized yet when
* this is run.
*
* Inlining must be avoided because it could make the label
* _sync_on_halt_end disappear. */
#pragma optimize acefgIklmNopRsuvwy
/* Because this code is not part of the application program as such,
* it makes no sense to profile it or runtime error check */
#pragma profiling off
#pragma runtime BCM
/* This explicit inclusion is used because the file may be compiled
* without SFR inclusion */
#include __SFRFILE__(__CPU__)
/* As above, but for the assembler. */
#define _SYNC_ON_HALT_STRINGIFY1(x) _SYNC_ON_HALT_STRINGIFY2(x)
#define _SYNC_ON_HALT_STRINGIFY2(y) #y
__asm(".include <sfr/reg" _SYNC_ON_HALT_STRINGIFY1(__CPU__) ".def>");
#if defined(_REGTC27X_H) || defined(_REGTC27XB_H) \
|| defined(_REGTC27XC_H) || defined(_REGTC27XD_H) \
|| defined(_REGTC26X_H) || defined(_REGTC26XB_H) \
|| defined(_REGTC29X_H) || defined(_REGTC29XB_H) \
|| defined(_REGTC21X_H) || defined(_REGTC22X_H) \
|| defined(_REGTC23X_H) || defined(_REGTC23X_ADAS_H) \
|| defined(_REGTC32X_H) || defined(_REGTC33X_H) \
|| defined(_REGTC35X_H) || defined(_REGTC36X_H) \
|| defined(_REGTC37X_H) || defined(_REGTC38X_H) \
|| defined(_REGTC39X_H) || defined(_REGTC39XB_H)
#if defined(__NO_VTC)
#define __CLONE
#else
#define __CLONE __clone
#endif
#define __DSPR_SYNC_ON_HALT_LCX __at(0xd0003f80)
#define __DSPR_SYNC_ON_HALT_UCX __at(0xd0003fc0)
#else
#define __CLONE
#define __DSPR_SYNC_ON_HALT_LCX
#define __DSPR_SYNC_ON_HALT_UCX
#endif
unsigned int __near __CLONE __align(64) _sync_on_halt_lcx[16] __DSPR_SYNC_ON_HALT_LCX;
unsigned int __near __CLONE __align(64) _sync_on_halt_ucx[16] __DSPR_SYNC_ON_HALT_UCX;
/* This function should never be called by the target application itself. */
extern void _sync_on_halt_end(void)
{
__nop();
__debug();
}
/* This function should never be called by the target application itself.
* __protect__ is needed to prevent this from being eliminated through
* unreferenced section removal. */
extern void __protect__ _sync_on_halt(void)
{
#if defined(_REGTC1762_H) || defined(_REGTC1764_H) || defined(_REGTC1766_H) || defined(_REGTC1766B_H) \
|| defined(_REGTC1792_H) || defined(_REGTC1796_H) || defined(_REGTC1796B_H) \
|| defined(_REGTC1164_H) || defined(_REGTC1166_H) \
/* Device has no data cache. */
#elif defined(_REGTC1130_H)
# define _EBU 8
# define _DCACHE_0_ADDRESS 0xc0000000U
# define _DCACHE_0_SIZE 64 /* In kBytes. */
#elif defined(_REGTC1167_H) || defined(_REGTC1197_H) \
|| defined(_REGTC1724_H) || defined(_REGTC1728_H) \
|| defined(_REGTC1184_H) || defined(_REGTC1784_H) \
|| defined(_REGTC1767_H) || defined(_REGTC1768_H) || defined(_REGTC1797_H) \
|| defined(_REGTC1782_H) || defined(_REGTC1783_H) || defined(_REGTC1746_H) \
|| defined(_REGTC1337_H) || defined(_REGTC1367_H) || defined(_REGTC1387_H)
# if !defined(__CORE_TC131__)
# error Internal inconsistency.
# endif
# define _DCACHE_LINES 256
# define _DCACHE_WAYS 2
# define _DCACHE_LINE_INDEX 4
# define _DCACHE_OFFSET 0x80000000U
#elif defined(_REGTC1736_H) || defined(_REGTC21X_H) || defined(_REGTC22X_H) || defined(_REGTC23X_H) || defined(_REGTC23X_ADAS_H)
/* Device has no data cache, but does have a Data Line or Read Buffer (DLB or DRB). We need
* to execute CACHEI.WI at least once. */
# if !defined(__CORE_TC131__) && !defined(__CORE_TC16X__) && !defined(__CORE_TC162__)
# error Internal inconsistency.
# endif
# define _DCACHE_LINES 1
# define _DCACHE_WAYS 1
# ifdef _REGTC1736_H
# define _DCACHE_LINE_INDEX 4
# else
# define _DCACHE_LINE_INDEX 5
# endif
# define _DCACHE_OFFSET 0x80000000U
#elif defined(_REGTC1798_H) || defined(_REGTC1748_H) || defined(_REGTC1791_H) || defined(_REGTC1793_H)
# ifndef __CORE_TC16__
# error Internal inconsistency.
# endif
# define _DCACHE_LINES 128
# define _DCACHE_WAYS 4
# define _DCACHE_LINE_INDEX 5
# define _DCACHE_OFFSET 0x80000000U
#elif defined(_REGTC27X_H) || defined(_REGTC27XB_H) || defined(_REGTC27XC_H) || defined(_REGTC27XD_H)
# if !defined(__CORE_TC16X__) && !defined(__CORE_TC162__)
# error Internal inconsistency.
# endif
/* Cache way number occupies bits 0 and 1, index number occupies bits 5...10. */
# define _DCACHE_LINES 64
# define _DCACHE_WAYS 4
# define _DCACHE_LINE_INDEX 5
# define _DCACHE_OFFSET 0x80000000U
#elif defined(_REGTC26X_H) || defined(_REGTC26XB_H) \
|| defined(_REGTC29X_H) || defined(_REGTC29XB_H) \
|| defined(_REGTC32X_H) || defined(_REGTC33X_H) \
|| defined(_REGTC35X_H) || defined(_REGTC36X_H) \
|| defined(_REGTC37X_H) || defined(_REGTC38X_H) \
|| defined(_REGTC39X_H) || defined(_REGTC39XB_H)
# if !defined(__CORE_TC16X__) && !defined(__CORE_TC162__)
# error Internal inconsistency.
# endif
/* Cache way number occupies bit 0, index number occupies bits 5...11. */
# define _DCACHE_LINES 128
# define _DCACHE_WAYS 2
# define _DCACHE_LINE_INDEX 5
# define _DCACHE_OFFSET 0x80000000U
#else
# error Unknown device. For user-defined devices, this code may have to be adapted.
#endif
#ifdef _DCACHE_LINES
unsigned char * line_addr;
unsigned int line_index;
unsigned int way_index;
#endif
#ifdef _EBU
EBU_ADDRSEL0_type * ebu_addrselx;
ptrdiff_t ebu_addrsel_delta;
int region_index;
unsigned int region_addr_u;
#endif
#if defined(_EBU) || defined(_DCACHE_0_ADDRESS)
unsigned char * line_addr;
unsigned int line_count;
unsigned int line_index;
#endif
/* Determine number of EBU regions. (Note that at the time of this writing at
* least it was not actually possible for there to be 5 or 6, only 4 or 7.) */
#ifndef _EBU
/* (Nothing.) */
#elif defined(EBU_ADDRSEL7) || !defined(EBU_ADDRSEL3)
# error Unexpected number of EBU_ADDRSELx registers.
#elif defined(EBU_ADDRSEL6)
# define _EBU_REGION_COUNT 7
#elif defined(EBU_ADDRSEL5)
# define _EBU_REGION_COUNT 6
#elif defined(EBU_ADDRSEL4)
# define _EBU_REGION_COUNT 5
#else
# define _EBU_REGION_COUNT 4
#endif
/* ***************************************************************************************
* Save PSW and (most of) the address and data registers. (Not all of these will actually
* be used, but that is up to the compiler and cannot be predicted reliably.)
*
* Note that PSW must be saved because of the switch to supervisor mode below, but also
* because the remainder of the code may change the flags.
*
* The st*cx instructions do not affect the CSA list and do not require it to be properly
* initialized (which it might not be at this point). */
__asm("stlcx _sync_on_halt_lcx");
__asm("stucx _sync_on_halt_ucx");
/* Set PSW.IO to 2 (supervisor mode). This is needed for certain operations
* performed below. */
__mtcr(PSW, (int) (((unsigned int) __mfcr(PSW) & 0xfffff3ffU) | 0x800U));
/* ***************************************************************
* Initiate flushing of instruction cache. (Waiting for it to
* complete is done later, i.e. in parallel with the data
* cache flushing.)
*/
#if defined(_REGTC1130_H) \
|| defined(_REGTC1762_H) || defined(_REGTC1764_H) \
|| defined(_REGTC1766_H) || defined(_REGTC1766B_H) \
|| defined(_REGTC1164_H) || defined(_REGTC1166_H) \
|| defined(_REGTC1792_H) || defined(_REGTC1796_H) || defined(_REGTC1796B_H)
/* Instruction cache flushing not supported for these devices. */
#elif defined(_REGTC1167_H) || defined(_REGTC1197_H) \
|| defined(_REGTC1724_H) || defined(_REGTC1728_H) || defined(_REGTC1736_H) \
|| defined(_REGTC1184_H) || defined(_REGTC1784_H) \
|| defined(_REGTC1767_H) || defined(_REGTC1768_H) || defined(_REGTC1797_H) \
|| defined(_REGTC1782_H) || defined(_REGTC1783_H) || defined(_REGTC1746_H) \
|| defined(_REGTC1337_H) || defined(_REGTC1367_H) || defined(_REGTC1387_H)
# define _ICACHE_BIT0 PMI_CON1.B.PCINV
# define _ICACHE_BIT1 PMI_CON1.B.PBINV
#elif defined(_REGTC1798_H) || defined(_REGTC1748_H) || defined(_REGTC1791_H) || defined(_REGTC1793_H) \
|| defined(_REGTC21X_H) || defined(_REGTC22X_H) || defined(_REGTC23X_H) || defined(_REGTC23X_ADAS_H) \
|| defined(_REGTC27X_H) || defined(_REGTC27XB_H) || defined(_REGTC27XC_H) || defined(_REGTC27XD_H) \
|| defined(_REGTC26X_H) || defined(_REGTC26XB_H) || defined(_REGTC29X_H) || defined(_REGTC29XB_H) \
|| defined(_REGTC32X_H) || defined(_REGTC33X_H) || defined(_REGTC35X_H) || defined(_REGTC36X_H) \
|| defined(_REGTC37X_H) || defined(_REGTC38X_H) || defined(_REGTC39X_H) || defined(_REGTC39XB_H)
# define _ICACHE_BIT0_W(bit_val) \
__mtcr(PCON1, (int) (((unsigned int) __mfcr(PCON1) & 0xfffffffeU) | (bit_val ? 1 : 0)))
# define _ICACHE_BIT1_W(bit_val) \
__mtcr(PCON1, (int) (((unsigned int) __mfcr(PCON1) & 0xfffffffdU) | (bit_val ? 2 : 0)))
# define _ICACHE_BIT0_R \
(((unsigned int) __mfcr(PCON1) & 0x1U)!=0U)
# define _ICACHE_BIT1_R \
(((unsigned int) __mfcr(PCON1) & 0x2U)!=0U)
#else
# error Unknown device.
#endif
#ifdef _ICACHE_BIT0
_ICACHE_BIT0 = 1;
_ICACHE_BIT1 = 1;
#endif
#ifdef _ICACHE_BIT0_W
_ICACHE_BIT0_W(1);
_ICACHE_BIT1_W(1);
#endif
/* **********************************************************
* Flush data cache. This will also flush the data line
* buffer, if there is one. */
#ifdef _EBU
ebu_addrselx = &EBU_ADDRSEL0;
ebu_addrsel_delta = ((EBU_ADDRSEL0_type *) &EBU_ADDRSEL1) - &EBU_ADDRSEL0;
for ( region_index = 0; region_index < _EBU_REGION_COUNT;
region_index++, ebu_addrselx += ebu_addrsel_delta )
{
if (!ebu_addrselx->B.REGENAB)
{
continue;
}
if ( (((ebu_addrselx->B.BASE >> 16) & 0xfU) == _EBU)
|| (ebu_addrselx->B.ALTENAB && (ebu_addrselx->B.ALTSEG == _EBU))
)
{
/* EBU region is accessible via segment specified by _EBU. */
/* Calculate start address of region. First, bits 28-31. */
region_addr_u = ((unsigned int) _EBU << 28);
/* Add bits 12-27. */
region_addr_u += ((unsigned int) (ebu_addrselx->B.BASE & 0xffff) << 12)
& (0xffffffffU << (27 - ebu_addrselx->B.MASK));
/* Size measured in 16-byte (128-bit) cache lines.
* For example, when MASK equals 15, the size is
* 4 kBytes, i.e. 256 lines. */
line_count = 1 << (23 - ebu_addrselx->B.MASK);
line_addr = (unsigned char *) region_addr_u;
for (line_index = 0; line_index < line_count; line_index++)
{
__cacheawi(line_addr);
line_addr += 16;
}
}
}
#endif /* #ifdef _EBU */
#ifdef _DCACHE_0_ADDRESS
line_count = (_DCACHE_0_SIZE * 1024) / 16;
line_addr = (unsigned char *) _DCACHE_0_ADDRESS;
for (line_index = 0; line_index < line_count; line_index++)
{
__cacheawi(line_addr);
line_addr += 16;
}
#endif
#ifdef _DCACHE_1_ADDRESS
line_count = (_DCACHE_1_SIZE * 1024) / 16;
line_addr = (unsigned char *) _DCACHE_1_ADDRESS;
for (line_index = 0; line_index < line_count; line_index++)
{
__cacheawi(line_addr);
line_addr += 16;
}
#endif
#ifdef _DCACHE_LINES
/* In the case of a TC1.6E core, there is only a Data Read Buffer (DRB),
* not a real cache, and as a result a single __cacheiwi(...) would
* actually suffice. However, the loop also works. */
line_addr = (unsigned char *) _DCACHE_OFFSET;
for (line_index = 0; line_index < _DCACHE_LINES; line_index++)
{
for (way_index = 0; way_index < _DCACHE_WAYS; way_index++)
{
__cacheiwi( line_addr+way_index );
}
line_addr += (1 << _DCACHE_LINE_INDEX);
}
#endif
/* **********************************************************
* Wait for code cache flushing to complete.
*/
#ifdef _ICACHE_BIT0
while (_ICACHE_BIT0 || _ICACHE_BIT1);
#endif
#ifdef _ICACHE_BIT0_R
while (_ICACHE_BIT0_R || _ICACHE_BIT1_R);
#endif
/* ***************************************************************************************
* Restore registers. */
/* If we switched to supervisor mode above, this restores the prior mode
* as well. */
__mtcr(PSW, _sync_on_halt_ucx[1]);
__asm("lducx _sync_on_halt_ucx");
__asm("ldlcx _sync_on_halt_lcx");
/* ***************************************************************************************
* Flush pipeline. */
__dsync(); /* Synchronize data. */
__isync(); /* Synchronize instructions. */
__nop(); /* */
__nop(); /* TC113_CPU9. */
/* No function call should be used here, because the CSA may not have
* been initialized yet. */
__asm("j _sync_on_halt_end");
return;
}
#endif

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/**********************************************************************************************************************
* \file Ifx_Cfg.h
* \brief Project configuration file.
* \copyright Copyright (C) Infineon Technologies AG 2019
*
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
* are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
* Software is furnished to do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are solely in the form of
* machine-executable object code generated by a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*********************************************************************************************************************/
#ifndef IFX_CFG_H
#define IFX_CFG_H 1
/*********************************************************************************************************************/
/*------------------------------------------Configuration for IfxScu_cfg.h-------------------------------------------*/
/*********************************************************************************************************************/
/* External oscillator frequency in Hz */
#define IFX_CFG_SCU_XTAL_FREQUENCY (20000000) /* Allowed values are: 40000000, 25000000, 20000000, 16000000 */
/* System PLL frequency in Hz */
#define IFX_CFG_SCU_PLL_FREQUENCY (300000000) /* Allowed values are: 300000000, 200000000, 160000000, 133000000
* or 80000000 */
/* Peripheral PLL1 frequency in Hz */
#define IFX_CFG_SCU_PLL1_FREQUENCY (320000000) /* Allowed values are: 320000000, 160000000 */
/* Peripheral PLL2 frequency in Hz */
#define IFX_CFG_SCU_PLL2_FREQUENCY (200000000) /* Allowed values are: 200000000 */
/*********************************************************************************************************************/
/*-----------------------------------Configuration of CPU cores------------------------------------------------------*/
/*********************************************************************************************************************/
/* The OpenBLT bootloader only requires once core. Leave the others in their default state. */
#define IFX_CFG_SSW_ENABLE_TRICORE0 (1U)
#define IFX_CFG_SSW_ENABLE_TRICORE1 (0U)
#define IFX_CFG_SSW_ENABLE_TRICORE2 (0U)
/*********************************************************************************************************************/
/*-----------------------------------Configuration of assertions-----------------------------------------------------*/
/*********************************************************************************************************************/
#include "boot.h"
/* Route all Ifx assertions to the bootloader's assertion module. */
#define IFX_ASSERT(level, expr) ASSERT_RT(expr)
/*********************************************************************************************************************/
/*-----------------------------------Configuration for Software managed interrupt------------------------------------*/
/*********************************************************************************************************************/
/* #define IFX_USE_SW_MANAGED_INT */ /* Decomment this line if the project needs to use Software managed interrupts */
/*********************************************************************************************************************/
/*---------------------------------Configuration for Trap Hook Functions' Extensions---------------------------------*/
/*********************************************************************************************************************/
/* #define IFX_CFG_EXTEND_TRAP_HOOKS */ /* Decomment this line if the project needs to extend trap hook functions */
#endif /* IFX_CFG_H */

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/**********************************************************************************************************************
* \file Ifx_Cfg_Ssw.c
* \brief Configuration file for the Startup Software
* \copyright Copyright (C) Infineon Technologies AG 2019
*
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
* are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
* Software is furnished to do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are solely in the form of
* machine-executable object code generated by a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*********************************************************************************************************************/
/*********************************************************************************************************************/
/*-----------------------------------------------------Includes------------------------------------------------------*/
/*********************************************************************************************************************/
#include "Ifx_Cfg_Ssw.h"
#include "Ifx_Ssw_Infra.h"
/*********************************************************************************************************************/
/*---------------------------------------------Function Implementations----------------------------------------------*/
/*********************************************************************************************************************/
#if defined(__TASKING__)
#pragma optimize RL
#elif defined(__HIGHTEC__)
#pragma GCC optimize ("O1")
#endif
#if (IFX_CFG_SSW_ENABLE_PMS_INIT == 1U)
void Ifx_Ssw_Pms_Init(void)
{
if (IfxPmsEvr_runInitSequence(&IfxPmsEvr_cfgSequenceDefault) == 0)
{
__debug();
/* Application may have call to error handling here */
}
Ifx_Ssw_jumpBackToLink();
}
#if (IFX_CFG_SSW_ENABLE_PMS_INIT_CHECK == 1U)
void Ifx_Ssw_Pms_InitCheck(void)
{
if (IfxPmsEvr_areInitValuesRight(&IfxPmsEvr_checkRegCfgDefault) == 0)
{
__debug();
/* Application may have call to error handling here */
}
Ifx_Ssw_jumpBackToLink();
}
#endif /* End of Ifx_Ssw_Pms_InitCheck() */
#endif /* End of Ifx_Ssw_Pms_Init() */
#if (IFX_CFG_SSW_ENABLE_LBIST == 1)
void Ifx_Ssw_Lbist(void)
{
if (!IfxScuLbist_isDone())
{
if(Ifx_Ssw_isColdPoweronReset())
{
IfxScuLbist_triggerInline(&IfxScuLbist_defaultConfig);
}
}
if (!IfxScuLbist_evaluateResult(IfxScuLbist_defaultConfig.signature))
{
__debug();
/* Application may have call to error handling here */
/* Infinite loop to ensure that the error is notified as 'debugger is not connected at this point of time' */
while(1);
}
Ifx_Ssw_jumpBackToLink();
}
#endif
#if defined(__TASKING__)
#pragma endoptimize
#elif defined(__HIGHTEC__)
#pragma GCC reset_options
#endif

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/**********************************************************************************************************************
* \file Ifx_Cfg_Ssw.h
* \brief Configuration header file for the Startup Software
* \copyright Copyright (C) Infineon Technologies AG 2019
*
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
* are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
* Software is furnished to do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are solely in the form of
* machine-executable object code generated by a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*********************************************************************************************************************/
#ifndef IFX_CFG_SSW_H_
#define IFX_CFG_SSW_H_
/*********************************************************************************************************************/
/*-----------------------------------------------------Includes------------------------------------------------------*/
/*********************************************************************************************************************/
#include "Ifx_Cfg.h"
#include "Ifx_Ssw.h"
/*********************************************************************************************************************/
/*------------------------------------------------------Macros-------------------------------------------------------*/
/*********************************************************************************************************************/
/* Set this macro to 1, to configure the PMS EVR. */
#ifndef IFX_CFG_SSW_ENABLE_PMS_INIT
#define IFX_CFG_SSW_ENABLE_PMS_INIT (1U)
#endif
/* Set this macro to 1, to check the PMS EVR configuration. */
#ifndef IFX_CFG_SSW_ENABLE_PMS_INIT_CHECK
#define IFX_CFG_SSW_ENABLE_PMS_INIT_CHECK (1U)
#endif
/* Set this macro to 1, to do LBIST checks. */
#ifndef IFX_CFG_SSW_ENABLE_LBIST
#define IFX_CFG_SSW_ENABLE_LBIST (0U)
#endif
/* Set this macro to 1, to do MONBIST checks. */
#ifndef IFX_CFG_SSW_ENABLE_MONBIST
#define IFX_CFG_SSW_ENABLE_MONBIST (0U)
#endif
/* Set this macro to 1, to do MMIC checks. */
#ifndef IFX_CFG_SSW_ENABLE_MMIC_CHECK
#define IFX_CFG_SSW_ENABLE_MMIC_CHECK (0U)
#endif
/* Set this macro to 1, to initialize the PLL. */
#ifndef IFX_CFG_SSW_ENABLE_PLL_INIT
#define IFX_CFG_SSW_ENABLE_PLL_INIT (1U)
#endif
/* Set this macro to 1, to do MBIST checks. */
#ifndef IFX_CFG_SSW_ENABLE_MBIST
#define IFX_CFG_SSW_ENABLE_MBIST (0U)
#endif
/* Set this macro to 1, to do SMU Alarm handling. */
#ifndef IFX_CFG_SSW_ENABLE_SMU
#define IFX_CFG_SSW_ENABLE_SMU (0U)
#endif
/* Set this macro to 1, to enable emem initialisation. */
#ifndef IFX_CFG_SSW_ENABLE_EMEM_INIT
#define IFX_CFG_SSW_ENABLE_EMEM_INIT (0U)
#endif
/*********************************************************************************************************************/
/*---------------------------------------------Function Implementations----------------------------------------------*/
/*********************************************************************************************************************/
#if IFX_CFG_SSW_ENABLE_PMS_INIT == 1U
#include "IfxPmsEvr.h"
extern void Ifx_Ssw_Pms_Init(void);
extern void Ifx_Ssw_Pms_InitCheck(void);
/* Callout hook API macro for PMS Initialization.
* This callout hook is referenced in Startup sequence. This need to be configured by application to
* initialize the PMS EVR module. This hook is by default defined to empty call by startup implementation.
* THIS CALLOUT HOOK SHALL NOT BE IMPLEMENTED AS FUNCTION CALL!
*/
#define IFX_CFG_SSW_CALLOUT_PMS_INIT() \
{ \
Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Pms_Init); \
IFX_CFG_SSW_CALLOUT_PMS_CHECK(); \
}
#if IFX_CFG_SSW_ENABLE_PMS_INIT_CHECK == 1U
/* Callout hook API macro for PMS Initialization check.
* This callout hook is referenced in Startup sequence. This need to be configured by application to
* cross verify the PMS configuration with the required values. This hook is by default defined to empty
* call by startup implementation.
* THIS CALLOUT HOOK SHALL NOT BE IMPLEMENTED AS FUNCTION CALL!
*/
#define IFX_CFG_SSW_CALLOUT_PMS_CHECK() \
{ \
Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Pms_InitCheck); \
}
#else
#define IFX_CFG_SSW_CALLOUT_PMS_CHECK()
#endif /* End of IFX_CFG_SSW_ENABLE_PMS_INIT_CHECK */
#endif /* End of IFX_CFG_SSW_ENABLE_PMS_INIT */
/* Callout hook API macro for LBIST check.
* This callout hook is referenced in Startup sequence. This need to be configured by application to
* do LBIST checks. This hook is by default defined to empty call by startup implementation.
* THIS CALLOUT HOOK SHALL NOT BE IMPLEMENTED AS FUNCTION CALL!
*/
#if IFX_CFG_SSW_ENABLE_LBIST == 1U
#include "IfxScuLbist.h"
extern void Ifx_Ssw_Lbist(void);
#define IFX_CFG_SSW_CALLOUT_LBIST() \
{ \
Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Lbist); \
}
#endif /* End of IFX_CFG_SSW_ENABLE_LBIST */
/* Callout hook API macro for MONBIST check.
* This callout hook is referenced in Startup sequence. This need to be configured by application to
* do MONBIST checks. This hook is by default defined to empty call by startup implementation.
* THIS CALLOUT HOOK SHALL NOT BE IMPLEMENTED AS FUNCTION CALL!
*/
#if IFX_CFG_SSW_ENABLE_MONBIST == 1U
#include "IfxSmuStdby.h"
extern void Ifx_Ssw_Monbist(void);
#define IFX_CFG_SSW_CALLOUT_MONBIST() \
{ \
Ifx_Ssw_jumpToFunctionWithLink(&Ifx_Ssw_Monbist); \
}
#endif /* End of IFX_CFG_SSW_ENABLE_MONBIST */
/* Callout hook API macro for PLL initialization.
* This callout hook is referenced in Startup sequence. This need to be configured by application to
* initialize the PLL. This hook is by default defined to empty call by startup implementation.
*/
#if IFX_CFG_SSW_ENABLE_PLL_INIT == 1U
#include "IfxScuCcu.h"
#define IFX_CFG_SSW_CALLOUT_PLL_INIT() \
{ \
if (IfxScuCcu_init(&IfxScuCcu_defaultClockConfig) == 1) \
{ \
__debug(); \
} \
}
#endif /* End of IFX_CFG_SSW_ENABLE_PLL_INIT */
/* Callout hook API macro for MBIST check.
* This callout hook is referenced in Startup sequence. This need to be configured by application to
* do MBIST checks. This hook is by default defined to empty call by startup implementation.
*/
#if IFX_CFG_SSW_ENABLE_MBIST == 1U
#include "IfxMtu.h"
#define IFX_CFG_SSW_CALLOUT_MBIST() \
{ \
IFX_EXTERN const IfxMtu_MbistConfig *const mbistGangConfig[]; \
if (IfxMtu_runMbistAll(mbistGangConfig) == 1U) \
{ \
__debug(); \
} \
}
#endif /* End of IFX_CFG_SSW_ENABLE_MBIST */
/* Callout hook API macro for MMIC check.
* This need to be configured by application to do MMIC checks.
* This hook is by default defined to empty call by startup implementation.
*/
#if IFX_CFG_SSW_ENABLE_MMIC_CHECK == 1U
#define IFX_CFG_SSW_CALLOUT_MMIC_CHECK()
#endif /* End of IFX_CFG_SSW_ENABLE_MMIC_CHECK */
/* Callout hook API macro for SMU alarm handling.
* This need to be configured by application to do SMU alarm handling.
* This hook is by default defined to empty call by startup implementation.
*/
#if IFX_CFG_SSW_ENABLE_SMU == 1U
#define IFX_CFG_SSW_CALLOUT_SMU()
#endif /* End of IFX_CFG_SSW_ENABLE_SMU */
/* Callout hook API macro to unlock EMEM.
* This callout hook is referenced in Startup sequence. This need to be configured by application to
* initialize EMEM. This unlocks the EMEM. This hook is by default defined to empty call by startup implementation.
*/
#if IFX_CFG_SSW_ENABLE_EMEM_INIT == 1U
#include "IfxEmem_reg.h"
extern void Ifx_Ssw_UnlockEmem(void);
#define IFX_CFG_SSW_CALLOUT_EMEM_INIT() \
{ \
Ifx_Ssw_UnlockEmem(); \
}
#endif
#endif /* IFX_CFG_SSW_H_ */

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/**********************************************************************************************************************
* \file Ifx_Cfg_SswBmhd.c
* \brief This file contains the Bmhd for Aurix TC3XX.
* \copyright Copyright (C) Infineon Technologies AG 2019
*
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
* are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
* Software is furnished to do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are solely in the form of
* machine-executable object code generated by a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*********************************************************************************************************************/
/*********************************************************************************************************************/
/*-----------------------------------------------------Includes------------------------------------------------------*/
/*********************************************************************************************************************/
#include "Ifx_Ssw.h"
/*********************************************************************************************************************/
/*--------------------------------------------------BMHD constants---------------------------------------------------*/
/*********************************************************************************************************************/
#if defined(__HIGHTEC__)
#pragma section
#pragma section ".bmhd_0_orig" a
#endif
#if defined(__TASKING__)
#pragma section farrom "bmhd_0_orig"
#endif
#if defined(__DCC__)
#pragma section CONST ".bmhd_0_orig" far-absolute R
#endif
#if defined(__ghs__)
#pragma ghs section rodata= ".bmhd_0_orig"
#endif
const Ifx_Ssw_Bmhd bmhd_0_orig =
{
0x007E, /* 0x000: .bmi: Boot Mode Index (BMI) */
0xB359, /* 0x002: .bmhdid: Boot Mode Header ID (CODE) = B359H */
0xA0000000, /* 0x004: .stad: User Code start address */
0x809FE5E2, /* 0x008: .crc: Check Result for the BMI Header (offset 000H - 007H) */
0x7F601A1D, /* 0x00C: .crcInv: Inverted Check Result for the BMI Header (offset 000H - 007H) */
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x010: Reserved (0x010 - 0x01F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x020: Reserved (0x020 - 0x02F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x030: Reserved (0x030 - 0x03F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x040: Reserved (0x040 - 0x04F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x050: Reserved (0x050 - 0x05F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x060: Reserved (0x060 - 0x06F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x070: Reserved (0x070 - 0x07F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x080: Reserved (0x080 - 0x08F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x090: Reserved (0x090 - 0x09F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0A0: Reserved (0x0A0 - 0x0AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0B0: Reserved (0x0B0 - 0x0BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0C0: Reserved (0x0C0 - 0x0CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0D0: Reserved (0x0D0 - 0x0DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0E0: Reserved (0x0E0 - 0x0EF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x0F0: Reserved (0x0F0 - 0x0FF) */
},
{
0x00000000, /* 0x100: .pw0: Password protection word 0 (lsw) */
0x00000000, /* 0x104: .pw1: Password protection word 1 */
0x00000000, /* 0x108: .pw2: Password protection word 2 */
0x00000000, /* 0x10C: .pw3: Password protection word 3 */
0x00000000, /* 0x110: .pw4: Password protection word 4 */
0x00000000, /* 0x114: .pw5: Password protection word 5 */
0x00000000, /* 0x118: .pw6: Password protection word 6 */
0x00000000, /* 0x11C: .pw7: Password protection word 7 (msw) */
},
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x120: Reserved (0x120 - 0x12F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x130: Reserved (0x130 - 0x13F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x140: Reserved (0x140 - 0x14F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x150: Reserved (0x150 - 0x15F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x160: Reserved (0x160 - 0x16F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x170: Reserved (0x170 - 0x17F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x180: Reserved (0x180 - 0x18F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x190: Reserved (0x190 - 0x19F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1A0: Reserved (0x1A0 - 0x1AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1B0: Reserved (0x1B0 - 0x1BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1C0: Reserved (0x1C0 - 0x1CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1D0: Reserved (0x1D0 - 0x1DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x1E0: Reserved (0x1E0 - 0x1EF) */
},
0x43211234 /* 0x1F0: .confirmation: 32-bit CODE, (always same) */
};
#if defined(__HIGHTEC__)
#pragma section
#pragma section ".bmhd_0_copy" a
#endif
#if defined(__TASKING__)
#pragma section farrom "bmhd_0_copy"
#endif
#if defined(__DCC__)
#pragma section CONST ".bmhd_0_copy" far-absolute R
#endif
#if defined(__ghs__)
#pragma ghs section rodata= ".bmhd_0_copy"
#endif
const Ifx_Ssw_Bmhd bmhd_0_copy =
{
0x007E, /* 0x000: .bmi: Boot Mode Index (BMI) */
0xB359, /* 0x002: .bmhdid: Boot Mode Header ID (CODE) = B359H */
0xA0000000, /* 0x004: .stad: User Code start address */
0x809FE5E2, /* 0x008: .crc: Check Result for the BMI Header (offset 000H - 007H) */
0x7F601A1D, /* 0x00C: .crcInv: Inverted Check Result for the BMI Header (offset 000H - 007H) */
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x010: Reserved (0x010 - 0x01F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x020: Reserved (0x020 - 0x02F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x030: Reserved (0x030 - 0x03F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x040: Reserved (0x040 - 0x04F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x050: Reserved (0x050 - 0x05F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x060: Reserved (0x060 - 0x06F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x070: Reserved (0x070 - 0x07F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x080: Reserved (0x080 - 0x08F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x090: Reserved (0x090 - 0x09F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0A0: Reserved (0x0A0 - 0x0AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0B0: Reserved (0x0B0 - 0x0BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0C0: Reserved (0x0C0 - 0x0CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0D0: Reserved (0x0D0 - 0x0DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0E0: Reserved (0x0E0 - 0x0EF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x0F0: Reserved (0x0F0 - 0x0FF) */
},
{
0x00000000, /* 0x100: .pw0: Password protection word 0 (lsw) */
0x00000000, /* 0x104: .pw1: Password protection word 1 */
0x00000000, /* 0x108: .pw2: Password protection word 2 */
0x00000000, /* 0x10C: .pw3: Password protection word 3 */
0x00000000, /* 0x110: .pw4: Password protection word 4 */
0x00000000, /* 0x114: .pw5: Password protection word 5 */
0x00000000, /* 0x118: .pw6: Password protection word 6 */
0x00000000, /* 0x11C: .pw7: Password protection word 7 (msw) */
},
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x120: Reserved (0x120 - 0x12F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x130: Reserved (0x120 - 0x13F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x140: Reserved (0x120 - 0x14F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x150: Reserved (0x120 - 0x15F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x160: Reserved (0x120 - 0x16F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x170: Reserved (0x120 - 0x17F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x180: Reserved (0x120 - 0x18F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x190: Reserved (0x120 - 0x19F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1A0: Reserved (0x120 - 0x1AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1B0: Reserved (0x120 - 0x1BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1C0: Reserved (0x120 - 0x1CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1D0: Reserved (0x120 - 0x1DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1E0: Reserved (0x120 - 0x1EF) */
},
0x43211234 /* 0x1F0: .confirmation: 32-bit CODE, (always same) */
};
#if defined(__HIGHTEC__)
#pragma section
#pragma section ".bmhd_1_orig" a
#endif
#if defined(__TASKING__)
#pragma section farrom "bmhd_1_orig"
#endif
#if defined(__DCC__)
#pragma section CONST ".bmhd_1_orig" far-absolute R
#endif
#if defined(__ghs__)
#pragma ghs section rodata= ".bmhd_1_orig"
#endif
const Ifx_Ssw_Bmhd bmhd_1_orig =
{
0x007E, /* 0x000: .bmi: Boot Mode Index (BMI) */
0xB359, /* 0x002: .bmhdid: Boot Mode Header ID (CODE) = B359H */
0xA0000000, /* 0x004: .stad: User Code start address */
0x809FE5E2, /* 0x008: .crc: Check Result for the BMI Header (offset 000H - 007H) */
0x7F601A1D, /* 0x00C: .crcInv: Inverted Check Result for the BMI Header (offset 000H - 007H) */
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x010: Reserved (0x010 - 0x01F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x020: Reserved (0x020 - 0x02F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x030: Reserved (0x030 - 0x03F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x040: Reserved (0x040 - 0x04F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x050: Reserved (0x050 - 0x05F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x060: Reserved (0x060 - 0x06F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x070: Reserved (0x070 - 0x07F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x080: Reserved (0x080 - 0x08F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x090: Reserved (0x090 - 0x09F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0A0: Reserved (0x0A0 - 0x0AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0B0: Reserved (0x0B0 - 0x0BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0C0: Reserved (0x0C0 - 0x0CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0D0: Reserved (0x0D0 - 0x0DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0E0: Reserved (0x0E0 - 0x0EF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x0F0: Reserved (0x0F0 - 0x0FF) */
},
{
0x00000000, /* 0x100: .pw0: Password protection word 0 (lsw) */
0x00000000, /* 0x104: .pw1: Password protection word 1 */
0x00000000, /* 0x108: .pw2: Password protection word 2 */
0x00000000, /* 0x10C: .pw3: Password protection word 3 */
0x00000000, /* 0x110: .pw4: Password protection word 4 */
0x00000000, /* 0x114: .pw5: Password protection word 5 */
0x00000000, /* 0x118: .pw6: Password protection word 6 */
0x00000000, /* 0x11C: .pw7: Password protection word 7 (msw) */
},
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x120: Reserved (0x120 - 0x12F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x130: Reserved (0x130 - 0x13F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x140: Reserved (0x140 - 0x14F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x150: Reserved (0x150 - 0x15F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x160: Reserved (0x160 - 0x16F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x170: Reserved (0x170 - 0x17F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x180: Reserved (0x180 - 0x18F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x190: Reserved (0x190 - 0x19F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1A0: Reserved (0x1A0 - 0x1AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1B0: Reserved (0x1B0 - 0x1BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1C0: Reserved (0x1C0 - 0x1CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1D0: Reserved (0x1D0 - 0x1DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x1E0: Reserved (0x1E0 - 0x1EF) */
},
0x43211234 /* 0x1F0: .confirmation: 32-bit CODE, (always same) */
};
#if defined(__HIGHTEC__)
#pragma section
#pragma section ".bmhd_1_copy" a
#endif
#if defined(__TASKING__)
#pragma section farrom "bmhd_1_copy"
#endif
#if defined(__DCC__)
#pragma section CONST ".bmhd_1_copy" far-absolute R
#endif
#if defined(__ghs__)
#pragma ghs section rodata= ".bmhd_1_copy"
#endif
const Ifx_Ssw_Bmhd bmhd_1_copy =
{
0x007E, /* 0x000: .bmi: Boot Mode Index (BMI) */
0xB359, /* 0x002: .bmhdid: Boot Mode Header ID (CODE) = B359H */
0xA0000000, /* 0x004: .stad: User Code start address */
0x809FE5E2, /* 0x008: .crc: Check Result for the BMI Header (offset 000H - 007H) */
0x7F601A1D, /* 0x00C: .crcInv: Inverted Check Result for the BMI Header (offset 000H - 007H) */
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x010: Reserved (0x010 - 0x01F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x020: Reserved (0x020 - 0x02F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x030: Reserved (0x030 - 0x03F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x040: Reserved (0x040 - 0x04F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x050: Reserved (0x050 - 0x05F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x060: Reserved (0x060 - 0x06F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x070: Reserved (0x070 - 0x07F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x080: Reserved (0x080 - 0x08F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x090: Reserved (0x090 - 0x09F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0A0: Reserved (0x0A0 - 0x0AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0B0: Reserved (0x0B0 - 0x0BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0C0: Reserved (0x0C0 - 0x0CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0D0: Reserved (0x0D0 - 0x0DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0E0: Reserved (0x0E0 - 0x0EF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x0F0: Reserved (0x0F0 - 0x0FF) */
},
{
0x00000000, /* 0x100: .pw0: Password protection word 0 (lsw) */
0x00000000, /* 0x104: .pw1: Password protection word 1 */
0x00000000, /* 0x108: .pw2: Password protection word 2 */
0x00000000, /* 0x10C: .pw3: Password protection word 3 */
0x00000000, /* 0x110: .pw4: Password protection word 4 */
0x00000000, /* 0x114: .pw5: Password protection word 5 */
0x00000000, /* 0x118: .pw6: Password protection word 6 */
0x00000000, /* 0x11C: .pw7: Password protection word 7 (msw) */
},
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x120: Reserved (0x120 - 0x12F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x130: Reserved (0x120 - 0x13F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x140: Reserved (0x120 - 0x14F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x150: Reserved (0x120 - 0x15F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x160: Reserved (0x120 - 0x16F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x170: Reserved (0x120 - 0x17F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x180: Reserved (0x120 - 0x18F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x190: Reserved (0x120 - 0x19F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1A0: Reserved (0x120 - 0x1AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1B0: Reserved (0x120 - 0x1BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1C0: Reserved (0x120 - 0x1CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1D0: Reserved (0x120 - 0x1DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1E0: Reserved (0x120 - 0x1EF) */
},
0x43211234 /* 0x1F0: .confirmation: 32-bit CODE, (always same) */
};
#if defined(__HIGHTEC__)
#pragma section
#pragma section ".bmhd_2_orig" a
#endif
#if defined(__TASKING__)
#pragma section farrom "bmhd_2_orig"
#endif
#if defined(__DCC__)
#pragma section CONST ".bmhd_2_orig" far-absolute R
#endif
#if defined(__ghs__)
#pragma ghs section rodata= ".bmhd_2_orig"
#endif
const Ifx_Ssw_Bmhd bmhd_2_orig =
{
0x007E, /* 0x000: .bmi: Boot Mode Index (BMI) */
0xB359, /* 0x002: .bmhdid: Boot Mode Header ID (CODE) = B359H */
0xA0000000, /* 0x004: .stad: User Code start address */
0x809FE5E2, /* 0x008: .crc: Check Result for the BMI Header (offset 000H - 007H) */
0x7F601A1D, /* 0x00C: .crcInv: Inverted Check Result for the BMI Header (offset 000H - 007H) */
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x010: Reserved (0x010 - 0x01F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x020: Reserved (0x020 - 0x02F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x030: Reserved (0x030 - 0x03F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x040: Reserved (0x040 - 0x04F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x050: Reserved (0x050 - 0x05F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x060: Reserved (0x060 - 0x06F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x070: Reserved (0x070 - 0x07F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x080: Reserved (0x080 - 0x08F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x090: Reserved (0x090 - 0x09F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0A0: Reserved (0x0A0 - 0x0AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0B0: Reserved (0x0B0 - 0x0BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0C0: Reserved (0x0C0 - 0x0CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0D0: Reserved (0x0D0 - 0x0DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0E0: Reserved (0x0E0 - 0x0EF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x0F0: Reserved (0x0F0 - 0x0FF) */
},
{
0x00000000, /* 0x100: .pw0: Password protection word 0 (lsw) */
0x00000000, /* 0x104: .pw1: Password protection word 1 */
0x00000000, /* 0x108: .pw2: Password protection word 2 */
0x00000000, /* 0x10C: .pw3: Password protection word 3 */
0x00000000, /* 0x110: .pw4: Password protection word 4 */
0x00000000, /* 0x114: .pw5: Password protection word 5 */
0x00000000, /* 0x118: .pw6: Password protection word 6 */
0x00000000, /* 0x11C: .pw7: Password protection word 7 (msw) */
},
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x120: Reserved (0x120 - 0x12F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x130: Reserved (0x130 - 0x13F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x140: Reserved (0x140 - 0x14F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x150: Reserved (0x150 - 0x15F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x160: Reserved (0x160 - 0x16F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x170: Reserved (0x170 - 0x17F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x180: Reserved (0x180 - 0x18F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x190: Reserved (0x190 - 0x19F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1A0: Reserved (0x1A0 - 0x1AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1B0: Reserved (0x1B0 - 0x1BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1C0: Reserved (0x1C0 - 0x1CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1D0: Reserved (0x1D0 - 0x1DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x1E0: Reserved (0x1E0 - 0x1EF) */
},
0x43211234 /* 0x1F0: .confirmation: 32-bit CODE, (always same) */
};
#if defined(__HIGHTEC__)
#pragma section
#pragma section ".bmhd_2_copy" a
#endif
#if defined(__TASKING__)
#pragma section farrom "bmhd_2_copy"
#endif
#if defined(__DCC__)
#pragma section CONST ".bmhd_2_copy" far-absolute R
#endif
#if defined(__ghs__)
#pragma ghs section rodata= ".bmhd_2_copy"
#endif
const Ifx_Ssw_Bmhd bmhd_2_copy =
{
0x007E, /* 0x000: .bmi: Boot Mode Index (BMI) */
0xB359, /* 0x002: .bmhdid: Boot Mode Header ID (CODE) = B359H */
0xA0000000, /* 0x004: .stad: User Code start address */
0x809FE5E2, /* 0x008: .crc: Check Result for the BMI Header (offset 000H - 007H) */
0x7F601A1D, /* 0x00C: .crcInv: Inverted Check Result for the BMI Header (offset 000H - 007H) */
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x010: Reserved (0x010 - 0x01F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x020: Reserved (0x020 - 0x02F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x030: Reserved (0x030 - 0x03F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x040: Reserved (0x040 - 0x04F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x050: Reserved (0x050 - 0x05F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x060: Reserved (0x060 - 0x06F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x070: Reserved (0x070 - 0x07F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x080: Reserved (0x080 - 0x08F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x090: Reserved (0x090 - 0x09F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0A0: Reserved (0x0A0 - 0x0AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0B0: Reserved (0x0B0 - 0x0BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0C0: Reserved (0x0C0 - 0x0CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0D0: Reserved (0x0D0 - 0x0DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0E0: Reserved (0x0E0 - 0x0EF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x0F0: Reserved (0x0F0 - 0x0FF) */
},
{
0x00000000, /* 0x100: .pw0: Password protection word 0 (lsw) */
0x00000000, /* 0x104: .pw1: Password protection word 1 */
0x00000000, /* 0x108: .pw2: Password protection word 2 */
0x00000000, /* 0x10C: .pw3: Password protection word 3 */
0x00000000, /* 0x110: .pw4: Password protection word 4 */
0x00000000, /* 0x114: .pw5: Password protection word 5 */
0x00000000, /* 0x118: .pw6: Password protection word 6 */
0x00000000, /* 0x11C: .pw7: Password protection word 7 (msw) */
},
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x120: Reserved (0x120 - 0x12F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x130: Reserved (0x120 - 0x13F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x140: Reserved (0x120 - 0x14F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x150: Reserved (0x120 - 0x15F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x160: Reserved (0x120 - 0x16F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x170: Reserved (0x120 - 0x17F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x180: Reserved (0x120 - 0x18F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x190: Reserved (0x120 - 0x19F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1A0: Reserved (0x120 - 0x1AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1B0: Reserved (0x120 - 0x1BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1C0: Reserved (0x120 - 0x1CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1D0: Reserved (0x120 - 0x1DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1E0: Reserved (0x120 - 0x1EF) */
},
0x43211234 /* 0x1F0: .confirmation: 32-bit CODE, (always same) */
};
#if defined(__HIGHTEC__)
#pragma section
#pragma section ".bmhd_3_orig" a
#endif
#if defined(__TASKING__)
#pragma section farrom "bmhd_3_orig"
#endif
#if defined(__DCC__)
#pragma section CONST ".bmhd_3_orig" far-absolute R
#endif
#if defined(__ghs__)
#pragma ghs section rodata= ".bmhd_3_orig"
#endif
const Ifx_Ssw_Bmhd bmhd_3_orig =
{
0x007E, /* 0x000: .bmi: Boot Mode Index (BMI) */
0xB359, /* 0x002: .bmhdid: Boot Mode Header ID (CODE) = B359H */
0xA0000000, /* 0x004: .stad: User Code start address */
0x809FE5E2, /* 0x008: .crc: Check Result for the BMI Header (offset 000H - 007H) */
0x7F601A1D, /* 0x00C: .crcInv: Inverted Check Result for the BMI Header (offset 000H - 007H) */
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x010: Reserved (0x010 - 0x01F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x020: Reserved (0x020 - 0x02F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x030: Reserved (0x030 - 0x03F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x040: Reserved (0x040 - 0x04F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x050: Reserved (0x050 - 0x05F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x060: Reserved (0x060 - 0x06F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x070: Reserved (0x070 - 0x07F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x080: Reserved (0x080 - 0x08F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x090: Reserved (0x090 - 0x09F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0A0: Reserved (0x0A0 - 0x0AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0B0: Reserved (0x0B0 - 0x0BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0C0: Reserved (0x0C0 - 0x0CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0D0: Reserved (0x0D0 - 0x0DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0E0: Reserved (0x0E0 - 0x0EF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x0F0: Reserved (0x0F0 - 0x0FF) */
},
{
0x00000000, /* 0x100: .pw0: Password protection word 0 (lsw) */
0x00000000, /* 0x104: .pw1: Password protection word 1 */
0x00000000, /* 0x108: .pw2: Password protection word 2 */
0x00000000, /* 0x10C: .pw3: Password protection word 3 */
0x00000000, /* 0x110: .pw4: Password protection word 4 */
0x00000000, /* 0x114: .pw5: Password protection word 5 */
0x00000000, /* 0x118: .pw6: Password protection word 6 */
0x00000000, /* 0x11C: .pw7: Password protection word 7 (msw) */
},
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x120: Reserved (0x120 - 0x12F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x130: Reserved (0x130 - 0x13F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x140: Reserved (0x140 - 0x14F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x150: Reserved (0x150 - 0x15F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x160: Reserved (0x160 - 0x16F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x170: Reserved (0x170 - 0x17F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x180: Reserved (0x180 - 0x18F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x190: Reserved (0x190 - 0x19F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1A0: Reserved (0x1A0 - 0x1AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1B0: Reserved (0x1B0 - 0x1BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1C0: Reserved (0x1C0 - 0x1CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1D0: Reserved (0x1D0 - 0x1DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x1E0: Reserved (0x1E0 - 0x1EF) */
},
0x43211234 /* 0x1F0: .confirmation: 32-bit CODE, (always same) */
};
#if defined(__HIGHTEC__)
#pragma section
#pragma section ".bmhd_3_copy" a
#endif
#if defined(__TASKING__)
#pragma section farrom "bmhd_3_copy"
#endif
#if defined(__DCC__)
#pragma section CONST ".bmhd_3_copy" far-absolute R
#endif
#if defined(__ghs__)
#pragma ghs section rodata= ".bmhd_3_copy"
#endif
const Ifx_Ssw_Bmhd bmhd_3_copy =
{
0x007E, /* 0x000: .bmi: Boot Mode Index (BMI) */
0xB359, /* 0x002: .bmhdid: Boot Mode Header ID (CODE) = B359H */
0xA0000000, /* 0x004: .stad: User Code start address */
0x809FE5E2, /* 0x008: .crc: Check Result for the BMI Header (offset 000H - 007H) */
0x7F601A1D, /* 0x00C: .crcInv: Inverted Check Result for the BMI Header (offset 000H - 007H) */
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x010: Reserved (0x010 - 0x01F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x020: Reserved (0x020 - 0x02F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x030: Reserved (0x030 - 0x03F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x040: Reserved (0x040 - 0x04F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x050: Reserved (0x050 - 0x05F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x060: Reserved (0x060 - 0x06F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x070: Reserved (0x070 - 0x07F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x080: Reserved (0x080 - 0x08F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x090: Reserved (0x090 - 0x09F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0A0: Reserved (0x0A0 - 0x0AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0B0: Reserved (0x0B0 - 0x0BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0C0: Reserved (0x0C0 - 0x0CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0D0: Reserved (0x0D0 - 0x0DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x0E0: Reserved (0x0E0 - 0x0EF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000 /* 0x0F0: Reserved (0x0F0 - 0x0FF) */
},
{
0x00000000, /* 0x100: .pw0: Password protection word 0 (lsw) */
0x00000000, /* 0x104: .pw1: Password protection word 1 */
0x00000000, /* 0x108: .pw2: Password protection word 2 */
0x00000000, /* 0x10C: .pw3: Password protection word 3 */
0x00000000, /* 0x110: .pw4: Password protection word 4 */
0x00000000, /* 0x114: .pw5: Password protection word 5 */
0x00000000, /* 0x118: .pw6: Password protection word 6 */
0x00000000, /* 0x11C: .pw7: Password protection word 7 (msw) */
},
{
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x120: Reserved (0x120 - 0x12F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x130: Reserved (0x120 - 0x13F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x140: Reserved (0x120 - 0x14F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x150: Reserved (0x120 - 0x15F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x160: Reserved (0x120 - 0x16F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x170: Reserved (0x120 - 0x17F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x180: Reserved (0x120 - 0x18F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x190: Reserved (0x120 - 0x19F) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1A0: Reserved (0x120 - 0x1AF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1B0: Reserved (0x120 - 0x1BF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1C0: Reserved (0x120 - 0x1CF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1D0: Reserved (0x120 - 0x1DF) */
0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 0x1E0: Reserved (0x120 - 0x1EF) */
},
0x43211234 /* 0x1F0: .confirmation: 32-bit CODE, (always same) */
};
#if defined(__HIGHTEC__)
#pragma section
#endif

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/**********************************************************************************************************************
* \file Cpu0_Main.c
* \copyright Copyright (C) Infineon Technologies AG 2019
*
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
* are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
* Software is furnished to do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are solely in the form of
* machine-executable object code generated by a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*********************************************************************************************************************/
#include "Ifx_Types.h"
#include "IfxCpu.h"
#include "IfxScuWdt.h"
#include "app.h"
void core0_main(void)
{
/* Disable the CPU0 and safety watchdog. */
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword());
/* Initialize the bootloader application. */
AppInit();
while(1)
{
/* Run the bootloader application. */
AppTask();
}
}

41
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/**********************************************************************************************************************
* \file Cpu1_Main.c
* \copyright Copyright (C) Infineon Technologies AG 2019
*
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
* are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
* Software is furnished to do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are solely in the form of
* machine-executable object code generated by a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*********************************************************************************************************************/
#include "Ifx_Types.h"
#include "IfxCpu.h"
#include "IfxScuWdt.h"
void core1_main(void)
{
/* Note that this CPU core is not used by the bootloader. */
/* Disable the CPU1 watchdog. */
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
while(1)
{
}
}

41
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/**********************************************************************************************************************
* \file Cpu2_Main.c
* \copyright Copyright (C) Infineon Technologies AG 2019
*
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
* are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
* Software is furnished to do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are solely in the form of
* machine-executable object code generated by a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*********************************************************************************************************************/
#include "Ifx_Types.h"
#include "IfxCpu.h"
#include "IfxScuWdt.h"
void core2_main(void)
{
/* Note that this CPU core is not used by the bootloader. */
/* Disable the CPU1 watchdog. */
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
while(1)
{
}
}

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Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/Lcf_Tasking_Tricore_Tc.lsl Normal file
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/**********************************************************************************************************************
* \file Lcf_Tasking_Tricore_Tc.lsl
* \brief Linker command file for Tasking compiler.
* \copyright Copyright (C) Infineon Technologies AG 2019
*
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
* are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
* Software is furnished to do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are solely in the form of
* machine-executable object code generated by a source language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*********************************************************************************************************************/
#define LCF_CSA0_SIZE 8k
#define LCF_USTACK0_SIZE 2k
#define LCF_ISTACK0_SIZE 1k
#define LCF_CSA1_SIZE 8k
#define LCF_USTACK1_SIZE 2k
#define LCF_ISTACK1_SIZE 1k
#define LCF_CSA2_SIZE 8k
#define LCF_USTACK2_SIZE 2k
#define LCF_ISTACK2_SIZE 1k
#define LCF_HEAP_SIZE 4k
#define LCF_CPU0 0
#define LCF_CPU1 1
#define LCF_CPU2 2
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
#define LCF_DEFAULT_HOST LCF_CPU0
/*#define LCF_DEFAULT_HOST LCF_CPU1*/
/*#define LCF_DEFAULT_HOST LCF_CPU2*/
#define LCF_DSPR2_START 0x50000000
#define LCF_DSPR2_SIZE 96k
#define LCF_DSPR1_START 0x60000000
#define LCF_DSPR1_SIZE 240k
#define LCF_DSPR0_START 0x70000000
#define LCF_DSPR0_SIZE 240k
#define LCF_CSA2_OFFSET (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE)
#define LCF_ISTACK2_OFFSET (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE)
#define LCF_USTACK2_OFFSET (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE)
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
#define LCF_HEAP2_OFFSET (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE)
#define LCF_INTVEC0_START 0x802FA000
#define LCF_INTVEC1_START 0x802FC000
#define LCF_INTVEC2_START 0x802FE000
#define LCF_TRAPVEC0_START 0x80000100
#define LCF_TRAPVEC1_START 0x80000200
#define LCF_TRAPVEC2_START 0x80000300
#define LCF_STARTPTR_CPU0 0x80000000
#define LCF_STARTPTR_CPU1 0x80000020
#define LCF_STARTPTR_CPU2 0x80000040
#define LCF_STARTPTR_NC_CPU0 0xA0000000
#define LCF_STARTPTR_NC_CPU1 0xA0000020
#define LCF_STARTPTR_NC_CPU2 0xA0000040
#define INTTAB0 (LCF_INTVEC0_START)
#define INTTAB1 (LCF_INTVEC1_START)
#define INTTAB2 (LCF_INTVEC2_START)
#define TRAPTAB0 (LCF_TRAPVEC0_START)
#define TRAPTAB1 (LCF_TRAPVEC1_START)
#define TRAPTAB2 (LCF_TRAPVEC2_START)
#define RESET LCF_STARTPTR_NC_CPU0
#include "tc1v1_6_2.lsl"
// Specify a multi-core processor environment (mpe)
processor mpe
{
derivative = tc37;
}
derivative tc37
{
core tc0
{
architecture = TC1V1.6.2;
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
}
core tc1 // core 1 TC16E
{
architecture = TC1V1.6.2;
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
}
core tc2 // core 2 TC16P
{
architecture = TC1V1.6.2;
space_id_offset = 300; // add 300 to all space IDs in the architecture definition
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
}
core vtc
{
architecture = TC1V1.6.2;
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
import tc1; // tc1
import tc2; // tc2
}
bus sri
{
mau = 8;
width = 32;
// map shared addresses one-to-one to real cores and virtual cores
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
map (dest=bus:tc2:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
}
memory dsram2 // Data Scratch Pad Ram
{
mau = 8;
size = 96k;
type = ram;
map (dest=bus:tc2:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8);
map (dest=bus:sri, dest_offset=0x50000000, size=96k);
}
memory psram2 // Program Scratch Pad Ram
{
mau = 8;
size = 64k;
type = ram;
map (dest=bus:tc2:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8);
map (dest=bus:sri, dest_offset=0x50100000, size=64k);
}
memory dsram1 // Data Scratch Pad Ram
{
mau = 8;
size = 240k;
type = ram;
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8);
map (dest=bus:sri, dest_offset=0x60000000, size=240k);
}
memory psram1 // Program Scratch Pad Ram
{
mau = 8;
size = 64k;
type = ram;
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8);
map (dest=bus:sri, dest_offset=0x60100000, size=64k);
}
memory dsram0 // Data Scratch Pad Ram
{
mau = 8;
size = 240k;
type = ram;
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8);
map (dest=bus:sri, dest_offset=0x70000000, size=240k);
}
memory psram0 // Program Scratch Pad Ram
{
mau = 8;
size = 64k;
type = ram;
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8);
map (dest=bus:sri, dest_offset=0x70100000, size=64k);
}
memory pfls0
{
mau = 8;
size = 32k; /* Size reserved for the bootloader. Matches flashLayout[]. */
type = rom;
map cached (dest=bus:sri, dest_offset=0x80000000, size=32k);
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=32k);
}
memory dfls0
{
mau = 8;
size = 256K;
type = reserved nvram;
map (dest=bus:sri, dest_offset=0xaf000000, size=256K);
}
memory ucb
{
mau = 8;
size = 24k;
type = rom;
map (dest=bus:sri, dest_offset=0xaf400000, reserved, size=24k);
}
memory cpu0_dlmu
{
mau = 8;
size = 64k;
type = ram;
map cached (dest=bus:sri, dest_offset=0x90000000, size=64k);
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=64k);
}
memory cpu1_dlmu
{
mau = 8;
size = 64k;
type = ram;
map cached (dest=bus:sri, dest_offset=0x90010000, size=64k);
map not_cached (dest=bus:sri, dest_offset=0xb0010000, reserved, size=64k);
}
memory cpu2_dlmu
{
mau = 8;
size = 64k;
type = ram;
map cached (dest=bus:sri, dest_offset=0x90020000, size=64k);
map not_cached (dest=bus:sri, dest_offset=0xb0020000, reserved, size=64k);
}
/*In case of TC37xPD it doesn't contain EMEM, the below memory needs to be commented*/
memory edmem
{
mau = 8;
size = 3M;
type = ram;
map (dest=bus:sri, dest_offset=0x99000000, size=3M);
map (dest=bus:sri, dest_offset=0xb9000000, reserved, size=3M);
}
#if (__VERSION__ >= 6003)
section_setup :vtc:linear
{
heap "heap" (min_size = (1k), fixed, align = 8);
}
#endif
section_setup :vtc:linear
{
start_address
(
symbol = "_START"
);
}
section_setup :vtc:linear
{
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
stack "ustack_tc2" (min_size = 1k, fixed, align = 8);
stack "istack_tc2" (min_size = 1k, fixed, align = 8);
}
/*Section setup for the copy table*/
section_setup :vtc:linear
{
copytable
(
align = 4,
dest = linear,
table
{
symbol = "_lc_ub_table_tc0";
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
},
table
{
symbol = "_lc_ub_table_tc1";
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
},
table
{
symbol = "_lc_ub_table_tc2";
space = :tc2:linear, :tc2:abs24, :tc2:abs18, :tc2:csa;
}
);
}
/*Sections located at absolute fixed address*/
section_layout :vtc:linear
{
/*Fixed memory Allocations for stack memory and CSA*/
group (ordered)
{
group ustack2(align = 8, run_addr = mem:dsram2[LCF_USTACK2_OFFSET])
{
stack "ustack_tc2" (size = LCF_USTACK2_SIZE);
}
"__USTACK2":= sizeof(group:ustack2) > 0 ? "_lc_ue_ustack_tc2" : 0;
"__USTACK2_END"="_lc_gb_ustack2";
group istack2(align = 8, run_addr = mem:dsram2[LCF_ISTACK2_OFFSET])
{
stack "istack_tc2" (size = LCF_ISTACK2_SIZE);
}
"__ISTACK2":= sizeof(group:istack2) > 0 ? "_lc_ue_istack_tc2" : 0;
"__ISTACK2_END"="_lc_gb_istack2";
group (align = 64, attributes=rw, run_addr=mem:dsram2[LCF_CSA2_OFFSET])
reserved "csa_tc2" (size = LCF_CSA2_SIZE);
"__CSA2":= "_lc_ub_csa_tc2";
"__CSA2_END":= "_lc_ue_csa_tc2";
}
group (ordered)
{
group ustack1(align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
{
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
}
"__USTACK1":= sizeof(group:ustack1) > 0 ? "_lc_ue_ustack_tc1" : 0;
"__USTACK1_END"="_lc_gb_ustack1";
group istack1(align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
{
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
}
"__ISTACK1":= sizeof(group:istack1) > 0 ? "_lc_ue_istack_tc1" : 0;
"__ISTACK1_END"="_lc_gb_istack1";
group (align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
"__CSA1":= "_lc_ub_csa_tc1";
"__CSA1_END":= "_lc_ue_csa_tc1";
}
group (ordered)
{
group ustack0(align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
{
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
}
"__USTACK0":= sizeof(group:ustack0) > 0 ? "_lc_ue_ustack_tc0" : 0;
"__USTACK0_END"="_lc_gb_ustack0";
group istack0(align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
{
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
}
"__ISTACK0":= sizeof(group:istack0) > 0 ? "_lc_ue_istack_tc0" : 0;
"__ISTACK0_END"="_lc_gb_istack0";
group (align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
"__CSA0":= "_lc_ub_csa_tc0";
"__CSA0_END":= "_lc_ue_csa_tc0";
}
/*Fixed memory Allocations for _START*/
group (ordered)
{
group reset (run_addr=RESET)
{
section "reset" ( size = 0x20, fill = 0x0800, attributes = r )
{
select ".text.start";
}
}
group interface_const (run_addr=mem:pfls0[0x0060])
{
select "*.interface_const";
}
"__IF_CONST" := addressof(group:interface_const);
"__START0" := LCF_STARTPTR_NC_CPU0;
"__START1" := LCF_STARTPTR_NC_CPU1;
"__START2" := LCF_STARTPTR_NC_CPU2;
}
/*Fixed memory Allocations for Trap Vector Table*/
group (ordered)
{
group trapvec_tc0 (align = 8, run_addr=LCF_TRAPVEC0_START)
{
section "trapvec_tc0" (size=0x100, attributes=rx, fill=0)
{
select "(.text.traptab_cpu0*)";
}
}
group trapvec_tc1 (align = 8, run_addr=LCF_TRAPVEC1_START)
{
section "trapvec_tc1" (size=0x100, attributes=rx, fill=0)
{
select "(.text.traptab_cpu1*)";
}
}
group trapvec_tc2 (align = 8, run_addr=LCF_TRAPVEC2_START)
{
section "trapvec_tc2" (size=0x100, attributes=rx, fill=0)
{
select "(.text.traptab_cpu2*)";
}
}
"__TRAPTAB_CPU0" := TRAPTAB0;
"__TRAPTAB_CPU1" := TRAPTAB1;
"__TRAPTAB_CPU2" := TRAPTAB2;
}
/*Fixed memory Allocations for Start up code*/
group (ordered)
{
group start_tc0 (run_addr=LCF_STARTPTR_NC_CPU0)
{
select "(.text.start_cpu0*)";
}
group start_tc1 (run_addr=LCF_STARTPTR_NC_CPU1)
{
section "start_tc1" (size=0x20, attributes=rx, fill=0)
{
select "(.text.start_cpu1*)";
}
}
group start_tc2 (run_addr=LCF_STARTPTR_NC_CPU2)
{
select "(.text.start_cpu2*)";
}
"__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */
"__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 0;
"__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 0;
}
/*Fixed memory Allocations for Interrupt Vector Table*/
group (ordered)
{
group int_tab_tc0 (ordered)
{
# include "inttab0.lsl"
}
group int_tab_tc1 (ordered)
{
# include "inttab1.lsl"
}
group int_tab_tc2 (ordered)
{
# include "inttab2.lsl"
}
"_lc_u_int_tab" = (LCF_INTVEC0_START);
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
"__INTTAB_CPU1" = (LCF_INTVEC1_START);
"__INTTAB_CPU2" = (LCF_INTVEC2_START);
}
/*Fixed memory Allocations for BMHD*/
group (ordered)
{
group bmh_0_orig (run_addr=mem:ucb[0x0000])
{
select ".rodata.bmhd_0_orig";
}
group bmh_1_orig (run_addr=mem:ucb[0x0200])
{
select ".rodata.bmhd_1_orig";
}
group bmh_2_orig (run_addr=mem:ucb[0x0400])
{
select ".rodata.bmhd_2_orig";
}
group bmh_3_orig (run_addr=mem:ucb[0x0600])
{
select ".rodata.bmhd_3_orig";
}
group bmh_blank (run_addr=mem:ucb[0x0800])
{
}
group bmh_0_copy (run_addr=mem:ucb[0x1000])
{
select ".rodata.bmhd_0_copy";
}
group bmh_1_copy (run_addr=mem:ucb[0x1200])
{
select ".rodata.bmhd_1_copy";
}
group bmh_2_copy (run_addr=mem:ucb[0x1400])
{
select ".rodata.bmhd_2_copy";
}
group bmh_3_copy (run_addr=mem:ucb[0x1600])
{
select ".rodata.bmhd_3_copy";
}
}
}
/*Near Abbsolute Addressable Data Sections*/
section_layout :vtc:abs18
{
/*Near Absolute Data, selectable with patterns and user defined sections*/
group
{
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2)
{
select "(.zdata.zdata_cpu2|.zdata.zdata_cpu2.*)";
select "(.zbss.zbss_cpu2|.zbss.zbss_cpu2.*)";
}
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
{
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1.*)";
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1.*)";
}
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
{
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0.*)";
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0.*)";
}
group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu)
{
select "(.zdata.zlmudata|.zdata.zlmudata.*)";
select "(.zbss.zlmubss|.zbss.zlmubss.*)";
}
}
/*Near Absolute Data, selectable by toolchain*/
# if LCF_DEFAULT_HOST == LCF_CPU2
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU1
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU0
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
# endif
{
group zdata_mcal(attributes=rw)
{
select ".zdata.dsprInit.cpu0.32bit";
select ".zdata.dsprInit.cpu0.16bit";
select ".zdata.dsprInit.cpu0.8bit";
}
group zdata_powerOn(attributes=rw)
{
select ".zdata.dsprPowerOnInit.cpu0.32bit";
select ".zdata.dsprPowerOnInit.cpu0.16bit";
select ".zdata.dsprPowerOnInit.cpu0.8bit";
}
group zbss_mcal(attributes=rw)
{
select ".zbss.dsprClearOnInit.cpu0.32bit";
select ".zbss.dsprClearOnInit.cpu0.16bit";
select ".zbss.dsprClearOnInit.cpu0.8bit";
}
group zbss_noClear(attributes=rw)
{
select ".zbss.dsprNoInit.cpu0.32bit";
select ".zbss.dsprNoInit.cpu0.16bit";
select ".zbss.dsprNoInit.cpu0.8bit";
}
group zbss_powerOn(attributes=rw)
{
select ".zbss.dsprPowerOnClear.cpu0.32bit";
select ".zbss.dsprPowerOnClear.cpu0.16bit";
select ".zbss.dsprPowerOnClear.cpu0.8bit";
}
group zdata(attributes=rw)
{
select "(.zdata|.zdata.*)";
select "(.zbss|.zbss.*)";
}
}
/*Near Absolute Const, selectable with patterns and user defined sections*/
group
{
group (ordered, align = 4, contiguous, run_addr=mem:pfls0)
{
select ".zrodata.Ifx_Ssw_Tc0.*";
select ".zrodata.Ifx_Ssw_Tc1.*";
select ".zrodata.Ifx_Ssw_Tc2.*";
select ".zrodata.Cpu0_Main.*";
select ".zrodata.Cpu1_Main.*";
select ".zrodata.Cpu2_Main.*";
/*Near Absolute Const, selectable by toolchain*/
select ".zrodata.const.cpu0.32bit";
select ".zrodata.const.cpu0.16bit";
select ".zrodata.const.cpu0.8bit";
select ".zrodata.config.cpu0.32bit";
select ".zrodata.config.cpu0.16bit";
select ".zrodata.config.cpu0.8bit";
select "(.zrodata|.zrodata.*)";
}
}
}
/*Relative A0/A1/A8/A9 Addressable Sections*/
section_layout :vtc:linear
{
/*Relative A0 Addressable Data, selectable by toolchain*/
# if LCF_DEFAULT_HOST == LCF_CPU2
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU1
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU0
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
# endif
{
select "(.data_a0.sdata|.data_a0.sdata.*)";
select "(.bss_a0.sbss|.bss_a0.sbss.*)";
}
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k;
"__A0_MEM" = "_SMALL_DATA_";
/*Relative A1 Addressable Const, selectable by toolchain*/
/*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
# if LCF_DEFAULT_HOST == LCF_CPU2
group a1 (ordered, align = 4, run_addr=mem:pfls0)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU1
group a1 (ordered, align = 4, run_addr=mem:pfls0)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU0
group a1 (ordered, align = 4, run_addr=mem:pfls0)
# endif
{
select "(.rodata_a1.srodata|.rodata_a1.srodata.*)";
select "(.ldata|.ldata.*)";
}
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k;
"__A1_MEM" = "_LITERAL_DATA_";
/*Relative A9 Addressable Data, selectable with patterns and user defined sections*/
group a9 (ordered, align = 4, run_addr=mem:cpu0_dlmu)
{
select "(.data_a9.a9sdata|.data_a9.a9sdata.*)";
select "(.bss_a9.a9sbss|.bss_a9.a9sbss.*)";
}
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k;
"__A9_MEM" = "_A9_DATA_";
/*Relative A8 Addressable Const, selectable with patterns and user defined sections*/
# if LCF_DEFAULT_HOST == LCF_CPU2
group a8 (ordered, align = 4, run_addr=mem:pfls0)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU1
group a8 (ordered, align = 4, run_addr=mem:pfls0)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU0
group a8 (ordered, align = 4, run_addr=mem:pfls0)
# endif
{
select "(.rodata_a8.a8srodata|.rodata_a8.a8srodata.*)";
}
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k;
"__A8_MEM" = "_A8_DATA_";
}
/*Far Data / Far Const Sections, selectable with patterns and user defined sections*/
section_layout :vtc:linear
{
/*Far Data Sections, selectable with patterns and user defined sections*/
group
{
/*DSRAM sections*/
group
{
group (ordered, attributes=rw, run_addr=mem:dsram2)
{
select ".data.Ifx_Ssw_Tc2.*";
select ".data.Cpu2_Main.*";
select "(.data.data_cpu2|.data.data_cpu2.*)";
select ".bss.Ifx_Ssw_Tc2.*";
select ".bss.Cpu2_Main.*";
select "(.bss.bss_cpu2|.bss.bss_cpu2.*)";
}
group (ordered, attributes=rw, run_addr=mem:dsram1)
{
select ".data.Ifx_Ssw_Tc1.*";
select ".data.Cpu1_Main.*";
select "(.data.data_cpu1|.data.data_cpu1.*)";
select ".bss.Ifx_Ssw_Tc1.*";
select ".bss.Cpu1_Main.*";
select "(.bss.bss_cpu1|.bss.bss_cpu1.*)";
}
group (ordered, attributes=rw, run_addr=mem:dsram0)
{
select ".data.Ifx_Ssw_Tc0.*";
select ".data.Cpu0_Main.*";
select "(.data.data_cpu0|.data.data_cpu0.*)";
select ".bss.Ifx_Ssw_Tc0.*";
select ".bss.Cpu0_Main.*";
select "(.bss.bss_cpu0|.bss.bss_cpu0.*)";
}
}
/*LMU Data sections*/
group
{
group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu)
{
select "(.data.lmudata_cpu0|.data.lmudata_cpu0.*)";
select "(.bss.lmubss_cpu0|.bss.lmubss_cpu0.*)";
select "(.data.lmudata|.data.lmudata.*)";
select "(.bss.lmubss|.bss.lmubss.*)";
}
group (ordered, attributes=rw, run_addr = mem:cpu1_dlmu)
{
select "(.data.lmudata_cpu1|.data.lmudata_cpu1.*)";
select "(.bss.lmubss_cpu1|.bss.lmubss_cpu1.*)";
}
group (ordered, attributes=rw, run_addr = mem:cpu2_dlmu)
{
select "(.data.lmudata_cpu2|.data.lmudata_cpu2.*)";
select "(.bss.lmubss_cpu2|.bss.lmubss_cpu2.*)";
}
}
}
/*Far Data Sections, selectable by toolchain*/
# if LCF_DEFAULT_HOST == LCF_CPU2
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU1
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU0
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
# endif
{
group data_mcal(attributes=rw)
{
select ".data.farDsprInit.cpu0.32bit";
select ".data.farDsprInit.cpu0.16bit";
select ".data.farDsprInit.cpu0.8bit";
}
group bss_mcal(attributes=rw)
{
select ".bss.farDsprClearOnInit.cpu0.32bit";
select ".bss.farDsprClearOnInit.cpu0.16bit";
select ".bss.farDsprClearOnInit.cpu0.8bit";
}
group bss_noInit(attributes=rw)
{
select ".bss.farDsprNoInit.cpu0.32bit";
select ".bss.farDsprNoInit.cpu0.16bit";
select ".bss.farDsprNoInit.cpu0.8bit";
}
group data(attributes=rw)
{
select "(.data|.data.*)";
select "(.bss|.bss.*)";
}
}
/*Heap allocation*/
# if LCF_DEFAULT_HOST == LCF_CPU2
group (ordered, align = 4, run_addr = mem:dsram2[LCF_HEAP2_OFFSET])
# endif
# if LCF_DEFAULT_HOST == LCF_CPU1
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
# endif
# if LCF_DEFAULT_HOST == LCF_CPU0
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
# endif
{
heap "heap" (size = LCF_HEAP_SIZE);
}
/*Far Const Sections, selectable with patterns and user defined sections*/
group
{
group (ordered, align = 4, run_addr=mem:pfls0)
{
select ".rodata.Ifx_Ssw_Tc0.*";
select ".rodata.Cpu0_Main.*";
select "(.rodata.rodata_cpu0|.rodata.rodata_cpu0.*)";
}
group (ordered, align = 4, run_addr=mem:pfls0)
{
select ".rodata.Cpu1_Main.*";
select ".rodata.Ifx_Ssw_Tc1.*";
select "(.rodata.rodata_cpu1|.rodata.rodata_cpu1.*)";
}
group (ordered, align = 4, run_addr=mem:pfls0)
{
select ".rodata.Ifx_Ssw_Tc2.*";
select ".rodata.Cpu2_Main.*";
select "(.rodata.rodata_cpu2|.rodata.rodata_cpu2.*)";
}
}
/*Far Const Sections, selectable by toolchain*/
# if LCF_DEFAULT_HOST == LCF_CPU2
group (ordered, align = 4, run_addr=mem:pfls0)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU1
group (ordered, align = 4, run_addr=mem:pfls0)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU0
group (ordered, align = 4, run_addr=mem:pfls0)
# endif
{
select ".rodata.farConst.cpu0.32bit";
select ".rodata.farConst.cpu0.16bit";
select ".rodata.farConst.cpu0.8bit";
select "(.rodata|.rodata.*)";
}
}
section_layout :vtc:linear
{
/*Code Sections, selectable with patterns and user defined sections*/
group
{
/*Program Scratchpad Sections*/
group
{
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
{
select "(.text.cpu0_psram|.text.cpu0_psram.*)";
select "(.text.psram_text_cpu0|.text.psram_text_cpu0.*)";
}
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
{
select "(.text.cpu1_psram|.text.cpu1_psram.*)";
select "(.text.psram_text_cpu1|.text.psram_text_cpu1.*)";
}
group code_psram2 (ordered, attributes=rwx, copy, run_addr=mem:psram2)
{
select "(.text.cpu2_psram|.text.cpu2_psram.*)";
select "(.text.psram_text_cpu2|.text.psram_text_cpu2.*)";
}
}
}
}
/* FLS Code selections*/
section_layout :vtc:linear
{
/*Code Sections, selectable with patterns and user defined sections*/
group
{
/*Cpu specific PFLASH Sections*/
group
{
group (ordered, align = 4, run_addr=mem:pfls0)
{
select ".text.Ifx_Ssw_Tc0.*";
select ".text.Cpu0_Main.*";
select ".text.CompilerTasking.Ifx_C_Init";
select "(.text.text_cpu0|.text.text_cpu0.*)";
}
group (ordered, align = 4, run_addr=mem:pfls0)
{
select ".text.Ifx_Ssw_Tc1.*";
select ".text.Cpu1_Main.*";
select "(.text.text_cpu1|.text.text_cpu1.*)";
}
group (ordered, align = 4, run_addr=mem:pfls0)
{
select ".text.Ifx_Ssw_Tc2.*";
select ".text.Cpu2_Main.*";
select "(.text.text_cpu2|.text.text_cpu2.*)";
}
}
}
/*Code Sections, selectable by toolchain*/
# if LCF_DEFAULT_HOST == LCF_CPU2
group (ordered, run_addr=mem:pfls0)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU1
group (ordered, run_addr=mem:pfls0)
# endif
# if LCF_DEFAULT_HOST == LCF_CPU0
group (ordered, run_addr=mem:pfls0)
# endif
{
select ".text.fast.pfls.cpu0";
select ".text.slow.pfls.cpu0";
select ".text.5ms.pfls.cpu0";
select ".text.10ms.pfls.cpu0";
select ".text.callout.pfls.cpu0";
select "(.text|.text.*)";
}
}
}

26
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/Libraries/.ads/backup.json Normal file
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@ -0,0 +1,26 @@
{
"name" : "Backup iLLD",
"commands" : [
{
"type": "CONTENT",
"from": "/iLLD",
"to": "/iLLD"
},
{
"type": "CONTENT",
"from": "/Infra",
"to": "/Infra"
},
{
"type": "CONTENT",
"from": "/Service",
"to": "/Service"
},
{
"type": "CONTENT",
"from": "/.ads",
"to": "/.ads"
}
]
}

33
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/Libraries/.ads/clean.json Normal file
View File

@ -0,0 +1,33 @@
{
"name" : "Clean iLLD",
"commands" : [
{
"type": "DELETE-PROJECT-METADATA",
"entries": [
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/iLLD"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/Infra"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/Service"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/.ads"},
{"key": "NEVER-EXCLUDE-FROM-BUILD", "value": "${dest-path}/iLLD/TC37A/Tricore/Cpu/CStart"},
{"key": "NEVER-EXCLUDE-FROM-BUILD", "value": "${dest-path}/iLLD/TC37A/Tricore/Cpu/Trap"}
]
},
{
"type": "DELETE",
"path": "/iLLD"
},
{
"type": "DELETE",
"path": "/Infra"
},
{
"type": "DELETE",
"path": "/Service"
},
{
"type": "DELETE",
"path": "/.ads"
}
]
}

22
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/Libraries/.ads/install.json Normal file
View File

@ -0,0 +1,22 @@
{
"name" : "Install iLLDs Full Set",
"commands" : [
{
"type": "SAVE-PROJECT-METADATA",
"entries": [
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/iLLD"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/Infra"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/Service"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/.ads"},
{"key": "NEVER-EXCLUDE-FROM-BUILD", "value": "${dest-path}/iLLD/TC37A/Tricore/Cpu/CStart"},
{"key": "NEVER-EXCLUDE-FROM-BUILD", "value": "${dest-path}/iLLD/TC37A/Tricore/Cpu/Trap"}
]
},
{
"type": "CONTENT",
"from": "/",
"to": "/"
}
]
}

17
Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/Libraries/.ads/rollback.json Normal file
View File

@ -0,0 +1,17 @@
{
"name" : "Install iLLDs Full Set",
"commands" : [
{
"type": "SAVE-PROJECT-METADATA",
"entries": [
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/iLLD"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/Infra"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/Service"},
{"key": "AURIX-LIBRARY-PATH", "value": "${dest-path}/.ads"},
{"key": "NEVER-EXCLUDE-FROM-BUILD", "value": "${dest-path}/iLLD/TC37A/Tricore/Cpu/CStart"},
{"key": "NEVER-EXCLUDE-FROM-BUILD", "value": "${dest-path}/iLLD/TC37A/Tricore/Cpu/Trap"}
]
}
]
}

73
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/**
* \file CompilerDcc.c
*
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
* $Date: 2014-02-27 20:08:39 GMT$
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include "Cpu/Std/Ifx_Types.h"
#include "Compilers.h"
#if defined(__DCC__)
/*!
* \brief Initializes C variables
*
* This function is called in the startup. This function initialize the all variables in .data section
* and clears the .bss section
*
* Parameters: Nil
* Return: Nil
*/
void Ifx_C_Init(void)
{
extern void __init_main(void);
__init_main(); /* initialize data */
}
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
/*Dummy main function
* This function is required only for the Windriver, which looks for main while linking
* ! DO NOT USE THIS FUNCTION !*/
int main(void)
{
return 0;
}
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER */
#endif

167
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/**
* \file CompilerDcc.h
*
* \version iLLD_New
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#ifndef COMPILERDCC_H
#define COMPILERDCC_H 1
/******************************************************************************/
#include <stddef.h>
/*Linker definitions which are specific to Dcc */
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
* to use the default compiler linker varaibles and startup */
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
/*Start: Core 0 definitions ********************************************** */
/*C extern defintions */
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
extern unsigned int __INTTAB_CPU##cpu[]; /**< interrupt vector table */ \
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap vector table */ \
extern unsigned int __CSA##cpu[]; /**< context save area begin */ \
extern unsigned int __CSA##cpu##_END[]; /**< context save area end */
#define __USTACK(cpu) __USTACK##cpu
#define __ISTACK(cpu) __ISTACK##cpu
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
#define __CSA(cpu) __CSA##cpu
#define __CSA_END(cpu) __CSA##cpu##_END
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
__asm("\t .weak __A8_MEM, __A9_MEM"); /**< ASM extern definitions */
/*Wrapper macros for the tool specific definitions */
#if defined(IFX_USE_SW_MANAGED_INT)
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
#else
#define __INTTAB(cpu) __INTTAB_CPU##cpu
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
#define __SDATA1(cpu) _SMALL_DATA_
#define __SDATA2(cpu) _LITERAL_DATA_
#define __SDATA3(cpu) __A8_MEM
#define __SDATA4(cpu) __A9_MEM
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
/******************************************************************************/
#define IFX_INLINE static __inline__
/* FXIME check how to pack structure members */
#define IFX_PACKED
#define COMPILER_NAME "DCC"
#define COMPILER_VERSION __VERSION__
#define COMPILER_REVISION 0
#define IFX_INTERRUPT_FAST IFX_INTERRUPT
#if defined(IFX_USE_SW_MANAGED_INT)
#ifndef IFX_INTERRUPT
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
#endif
#else
/* *INDENT-OFF* */
#ifndef IFX_INTERRUPT
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
#endif
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
#ifndef IFX_INTERRUPT_INTERNAL
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
void __interrupt(prio) __vector_table(vectabNum) isr(void)
#endif
/*Macro IFX_INTERRUPT_LEGACY is to be used for compiler version pror to 5.9.3.0*/
#define IFX_INTERRUPT_LEGACY(isr, vectabNum, prio) \
__asm ("\t.align\t 5\n\t\
.section .int."#prio"\n \t.sectionlink .inttab"#vectabNum".intvec."#prio"\n\
#$$bf\n\
__intvec_tc"#vectabNum"_"#prio":\n\
movh.a\t %a14,"#isr"@ha\n\
lea\t %a14,[%a14]"#isr"@l\n\
ji\t %a14\n\
#$$ef\n\t\
.section .intend."#prio"\n \t.sectionlink .text");\
__interrupt__ void isr (void)
/* *INDENT-ON* */
/******************************************************************************/
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
/******************************************************************************/
/*Memory qualifiers*/
#ifndef IFX_FAR_ABS
#define IFX_FAR_ABS
#endif
#ifndef IFX_NEAR_ABS
#define IFX_NEAR_ABS
#endif
#ifndef IFX_REL_A0
#define IFX_REL_A0
#endif
#ifndef IFX_REL_A1
#define IFX_REL_A1
#endif
#ifndef IFX_REL_A8
#define IFX_REL_A8
#endif
#ifndef IFX_REL_A9
#define IFX_REL_A9
#endif
/******************************************************************************/
#endif /* COMPILERDCC_H */

110
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/**
* \file CompilerGhs.c
*
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
* $Date: 2014-02-27 20:08:40 GMT$
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include "Cpu/Std/Ifx_Types.h"
#include "Compilers.h"
#if defined(__ghs__) && !defined(WIN32)
typedef int ptrdiff_t;
typedef unsigned int syze_t;
typedef signed int signed_size_t;
#define size_t syze_t
extern void *memcpy(void *s1, const void *s2, syze_t n);
extern void *memset(void *s, int c, syze_t n);
/* rodata is absolute */
typedef const char rodata_ptr[];
# define PIRBASE 0
#define CONST_FUNCP *const
/*!
* \brief Initializes C variables.
*
* This function is called in the startup. This function initialize the all variables in .data section
* and clears the .bss section
*
* Parameters: Nil
* Return: Nil
*/
void Ifx_C_Init(void)
{
/*----------------------------------------------------------------------*/
/* */
/* Clear BSS */
/* */
/*----------------------------------------------------------------------*/
{ /* The .secinfo section is in text; declare functions to force PIC */
#pragma ghs rodata
extern rodata_ptr __ghsbinfo_clear;
#pragma ghs rodata
extern rodata_ptr __ghseinfo_clear;
void **b = (void **) ((char *)__ghsbinfo_clear);
void **e = (void **) ((char *)__ghseinfo_clear);
while (b != e) {
void * t; /* target pointer */
ptrdiff_t v; /* value to set */
size_t n; /* set n bytes */
t = (char *)(*b++);
v = *((ptrdiff_t *) b); b++;
n = *((size_t *) b); b++;
memset(t, v, n);
}
}
/*----------------*/
/* initialize iob */
/*----------------*/
{
#pragma weak __gh_iob_init
extern void __gh_iob_init(void);
static void (CONST_FUNCP iob_init_funcp)(void) = __gh_iob_init;
/* if cciob.c is loaded, initialize _iob for stdin,stdout,stderr */
if (iob_init_funcp) __gh_iob_init();
}
}
#endif

170
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/**
* \file CompilerGhs.h
*
* \version iLLD_New
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#ifndef COMPILERGHS_H
#define COMPILERGHS_H 1
/******************************************************************************/
// #include <stddef.h>
/*Linker definitions which are specific to Ghs */
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
* to use the default compiler linker varaibles and startup */
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
/*Start: Common definitions ********************************************** */
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
extern unsigned int __A0_MEM[]; /**< center of A0 addressable area */ \
extern unsigned int __A1_MEM[]; /**< center of A1 addressable area */ \
extern unsigned int __A8_MEM[]; /**< center of A8 addressable area */ \
extern unsigned int __A9_MEM[]; /**< center of A9 addressable area */
/*End: Common definitions ************************************************ */
/*Start: Core 0 definitions ********************************************** */
/*C extern defintions */
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
extern unsigned int __INTTAB_CPU##cpu[]; /**< Interrupt vector table */ \
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */ \
extern unsigned int __CSA##cpu[]; /**< context save area 1 begin */ \
extern unsigned int __CSA##cpu##_END[]; /**< context save area 1 begin */
#define __USTACK(cpu) __USTACK##cpu
#define __ISTACK(cpu) __ISTACK##cpu
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
#define __CSA(cpu) __CSA##cpu
#define __CSA_END(cpu) __CSA##cpu##_END
/*Wrapper macros for the tool specific definitions */
#if defined(IFX_USE_SW_MANAGED_INT)
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
#else
#define __INTTAB(cpu) __INTTAB_CPU##cpu
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
#define __SDATA1(cpu) __A0_MEM
#define __SDATA2(cpu) __A1_MEM
#define __SDATA3(cpu) __A8_MEM
#define __SDATA4(cpu) __A9_MEM
/* MHWS+
#define __SDATA1(cpu) __A0_MEM
#define __SDATA2(cpu) __A1_MEM
#define __SDATA3(cpu) __A8_MEM
#define __SDATA4(cpu) __A9_MEM
MHWS- */
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
/******************************************************************************/
#ifndef IFX_INLINE
#define IFX_INLINE static inline __attribute__ ((always_inline)) /*Makes the function always inlined */
#endif
#define IFX_PACKED __packed
#define COMPILER_NAME "GHS"
#define COMPILER_VERSION __GHS_VERSION_NUMBER
#define COMPILER_REVISION __GHS_REVISION_VALUE
#if defined(IFX_USE_SW_MANAGED_INT)
#ifndef IFX_INTERRUPT
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
#endif
#else
/* *INDENT-OFF* */
#ifndef IFX_INTERRUPT
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
#endif
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
__attribute__((section(".intvec_tc"#vectabNum"_"#prio))) void iVecEntry##vectabNum##_##prio(void) \
{ \
__asm__("movh.a a14, %hi("#isr") \n" \
"lea a14, [a14]%lo("#isr")\n" \
"ji a14"); \
} \
__interrupt void isr(void)
/* *INDENT-ON* */
/******************************************************************************/
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
/******************************************************************************/
/*Memory qualifiers*/
#ifndef IFX_FAR_ABS
#define IFX_FAR_ABS __attribute__((fardata))
#endif
#ifndef IFX_NEAR_ABS
#define IFX_NEAR_ABS
#endif
#ifndef IFX_REL_A0
#define IFX_REL_A0
#endif
#ifndef IFX_REL_A1
#define IFX_REL_A1
#endif
#ifndef IFX_REL_A8
#define IFX_REL_A8
#endif
#ifndef IFX_REL_A9
#define IFX_REL_A9
#endif
/******************************************************************************/
#endif /* COMPILERGHS_H */

150
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/**
* \file CompilerGnuc.c
*
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
* $Date: 2014-02-27 20:08:40 GMT$
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include "Cpu/Std/Ifx_Types.h"
#include "Compilers.h"
#if defined(__HIGHTEC__) && !defined(WIN32)
/*!
* \brief Data s C variables.
*/
extern uint32 __clear_table[]; /**< clear table entry */
extern uint32 __copy_table[]; /**< copy table entry */
typedef volatile union
{
uint8 *ucPtr;
uint16 *usPtr;
uint32 *uiPtr;
unsigned long long *ullPtr;
} IfxStart_CTablePtr;
/*!
* \brief Initializes C variables.
*
* This function is called in the startup. This function initialize the all variables in .data section
* and clears the .bss section
*
* Parameters: Nil
* Return: Nil
*/
void Ifx_C_Init(void)
{
IfxStart_CTablePtr pBlockDest, pBlockSrc;
uint32 uiLength, uiCnt;
uint32 *pTable;
/* clear table */
pTable = (uint32 *)&__clear_table;
while (pTable)
{
pBlockDest.uiPtr = (uint32 *)*pTable++;
uiLength = *pTable++;
/* we are finished when length == -1 */
if (uiLength == 0xFFFFFFFF)
{
break;
}
uiCnt = uiLength / 8;
while (uiCnt--)
{
*pBlockDest.ullPtr++ = 0;
}
if (uiLength & 0x4)
{
*pBlockDest.uiPtr++ = 0;
}
if (uiLength & 0x2)
{
*pBlockDest.usPtr++ = 0;
}
if (uiLength & 0x1)
{
*pBlockDest.ucPtr = 0;
}
}
/* copy table */
pTable = (uint32 *)&__copy_table;
while (pTable)
{
pBlockSrc.uiPtr = (uint32 *)*pTable++;
pBlockDest.uiPtr = (uint32 *)*pTable++;
uiLength = *pTable++;
/* we are finished when length == -1 */
if (uiLength == 0xFFFFFFFF)
{
break;
}
uiCnt = uiLength / 8;
while (uiCnt--)
{
*pBlockDest.ullPtr++ = *pBlockSrc.ullPtr++;
}
if (uiLength & 0x4)
{
*pBlockDest.uiPtr++ = *pBlockSrc.uiPtr++;
}
if (uiLength & 0x2)
{
*pBlockDest.usPtr++ = *pBlockSrc.usPtr++;
}
if (uiLength & 0x1)
{
*pBlockDest.ucPtr = *pBlockSrc.ucPtr;
}
}
}
#endif

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/**
* \file CompilerGnuc.h
*
* \version iLLD_New
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#ifndef COMPILERGNUC_H
#define COMPILERGNUC_H 1
/******************************************************************************/
#include <stddef.h>
/*Linker definitions which are specific to Gnuc */
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
* to use the default compiler linker varaibles and startup */
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
/*Start: Common definitions ********************************************** */
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
extern unsigned int __A0_MEM[]; /**< center of A0 addressable area */ \
extern unsigned int __A1_MEM[]; /**< center of A1 addressable area */ \
extern unsigned int __A8_MEM[]; /**< center of A8 addressable area */ \
extern unsigned int __A9_MEM[]; /**< center of A9 addressable area */
/*End: Common definitions ************************************************ */
/*Start: Core 0 definitions ********************************************** */
/*C extern defintions */
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
extern unsigned int __INTTAB_CPU##cpu[]; /**< Interrupt vector table */ \
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */ \
extern unsigned int __CSA##cpu[]; /**< context save area 1 begin */ \
extern unsigned int __CSA##cpu##_END[]; /**< context save area 1 begin */
#define __USTACK(cpu) __USTACK##cpu
#define __ISTACK(cpu) __ISTACK##cpu
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
#define __CSA(cpu) __CSA##cpu
#define __CSA_END(cpu) __CSA##cpu##_END
/*Wrapper macros for the tool specific definitions */
#if defined(IFX_USE_SW_MANAGED_INT)
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
#else
#define __INTTAB(cpu) __INTTAB_CPU##cpu
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
#define __SDATA1(cpu) __A0_MEM
#define __SDATA2(cpu) __A1_MEM
#define __SDATA3(cpu) __A8_MEM
#define __SDATA4(cpu) __A9_MEM
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
/******************************************************************************/
#ifndef IFX_INLINE
#define IFX_INLINE static inline __attribute__ ((always_inline)) /*Makes the function always inlined */
#endif
#define IFX_PACKED __attribute__ ((packed))
#define COMPILER_NAME "GNUC"
#define COMPILER_VERSION __VERSION__
#define COMPILER_REVISION 0
#define IFX_INTERRUPT_FAST IFX_INTERRUPT
#if defined(IFX_USE_SW_MANAGED_INT)
#ifndef IFX_INTERRUPT
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
#endif
#else
/* *INDENT-OFF* */
#ifndef IFX_INTERRUPT
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
#endif
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
#ifndef IFX_INTERRUPT_INTERNAL
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
__asm__ (".ifndef .intr.entry.include \n"\
".altmacro \n"\
".macro .int_entry.2 intEntryLabel, name # define the section and inttab entry code \n"\
" .pushsection .\\intEntryLabel,\"ax\",@progbits \n"\
" __\\intEntryLabel : \n"\
" svlcx \n"\
" movh.a %a14, hi:\\name \n"\
" lea %a14, [%a14]lo:\\name \n"\
" ji %a14 \n"\
" .popsection \n"\
".endm \n"\
".macro .int_entry.1 prio,vectabNum,u,name \n"\
".int_entry.2 intvec_tc\\vectabNum\\u\\prio,(name) # build the unique name \n"\
".endm \n"\
" \n"\
".macro .intr.entry name,vectabNum,prio \n"\
".int_entry.1 %(prio),%(vectabNum),_,name # evaluate the priority and the cpu number \n"\
".endm \n"\
".intr.entry.include: \n"\
".endif \n"\
".intr.entry "#isr","#vectabNum","#prio );\
IFX_EXTERN void __attribute__ ((interrupt_handler)) isr(); \
void isr (void)
#endif /* IFX_INTERRUPT_INTERNAL */
/* *INDENT-ON* */
/******************************************************************************/
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
/******************************************************************************/
/*Memory qualifiers*/
#ifndef IFX_FAR_ABS
#define IFX_FAR_ABS __attribute__((fardata))
#endif
#ifndef IFX_NEAR_ABS
#define IFX_NEAR_ABS
#endif
#ifndef IFX_REL_A0
#define IFX_REL_A0
#endif
#ifndef IFX_REL_A1
#define IFX_REL_A1
#endif
#ifndef IFX_REL_A8
#define IFX_REL_A8
#endif
#ifndef IFX_REL_A9
#define IFX_REL_A9
#endif
/******************************************************************************/
#endif /* COMPILERGNUC_H */

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/**
* \file CompilerTasking.c
*
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
* $Date: 2014-02-27 20:08:41 GMT$
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include "Cpu/Std/Ifx_Types.h"
#include "Compilers.h"
#if defined(__TASKING__)
/*!
* \brief Initializes C variables
*
* This function is called in the startup. This function initialize the all variables in .data section
* and clears the .bss section
*
* Parameters: Nil
* Return: Nil
*/
void Ifx_C_Init(void)
{
extern void _c_init(void);
_c_init(); /* initialize data */
}
#endif

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/**
* \file CompilerTasking.h
*
* \version iLLD_New
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#ifndef COMPILERTASKING_H
#define COMPILERTASKING_H 1
/******************************************************************************/
#include <stddef.h>
/*Linker definitions which are specific to Tasking */
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
* to use the default compiler linker varaibles and startup */
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
#ifndef __cplusplus
/*Start: Common definitions ********************************************** */
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
__asm("\t .extern _SMALL_DATA_, _LITERAL_DATA_, _A8_DATA_, _A9_DATA_");
/*End: Common definitions ********************************************** */
/*Start: Core 0 definitions ********************************************** */
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
__asm("\t .extern __USTACK"#cpu); /**< user stack end is required as asm to be used with setreg macro */ \
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
extern unsigned int __INTTAB_CPU##cpu[]; /**< interrupt vector table */ \
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap vector table */ \
extern unsigned int __CSA##cpu[]; /**< context save area begin */ \
extern unsigned int __CSA##cpu##_END[]; /**< context save area end */
#endif
#define __USTACK(cpu) __USTACK##cpu
#define __ISTACK(cpu) __ISTACK##cpu
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
#define __CSA(cpu) __CSA##cpu
#define __CSA_END(cpu) __CSA##cpu##_END
/*Wrapper macros for the tool specific definitions */
#if defined(IFX_USE_SW_MANAGED_INT)
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
#else
#define __INTTAB(cpu) __INTTAB_CPU##cpu
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
#define __SDATA1(cpu) _SMALL_DATA_
#define __SDATA2(cpu) _LITERAL_DATA_
#define __SDATA3(cpu) _A8_DATA_
#define __SDATA4(cpu) _A9_DATA_
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
/******************************************************************************/
#ifdef __cplusplus
#define IFX_INLINE static inline
#else
#define IFX_INLINE static inline
#endif
/* FXIME check how to pack structure members */
#define IFX_PACKED
#define COMPILER_NAME "TASKING"
#define COMPILER_VERSION __VERSION__
/* Note that __REVISION__ is only available for tasking compiler! */
#define COMPILER_REVISION __REVISION__
/******************************************************************************/
#if defined(IFX_USE_SW_MANAGED_INT)
#ifndef IFX_INTERRUPT
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
#endif
#else
/* *INDENT-OFF* */
#ifndef IFX_INTERRUPT
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
#endif
#define IFX_INTERRUPT_FAST(isr, vectabNum, prio) void __interrupt_fast(prio) __vector_table(vectabNum) isr(void)
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) void __interrupt(prio) __vector_table(vectabNum) isr(void)
/* *INDENT-ON* */
/******************************************************************************/
#define IFX_ALIGN(n) __attribute__ ((__align(n)))
/******************************************************************************/
/*Memory qualifiers*/
#ifndef IFX_FAR_ABS
#define IFX_FAR_ABS __far
#endif
#ifndef IFX_NEAR_ABS
#define IFX_NEAR_ABS __near
#endif
#ifndef IFX_REL_A0
#define IFX_REL_A0 __a0
#endif
#ifndef IFX_REL_A1
#define IFX_REL_A1 __a1
#endif
#ifndef IFX_REL_A8
#define IFX_REL_A8 __a8
#endif
#ifndef IFX_REL_A9
#define IFX_REL_A9 __a9
#endif
/******************************************************************************/
#endif /* COMPILERTASKING_H */

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/**
* \file Compilers.h
*
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
*
* $Date: 2014-04-07 12:13:19 GMT$
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#ifndef COMPILERS_H
#define COMPILERS_H 1
/******************************************************************************/
#include "Ifx_Cfg.h"
/*this file shall not be modified by the user, IFX_XXXX defines shall be defined in Ifx_Cfg.h */
#ifndef IFX_STATIC
#define IFX_STATIC static
#endif
#ifndef IFX_CONST
#define IFX_CONST const
#endif
#ifndef CONST_CFG
#define CONST_CFG const /* configuration constants are stored in ROM */
#endif
#ifdef __cplusplus
#define IFX_EXTERN extern "C"
#else
#define IFX_EXTERN extern
#endif
#ifndef NULL_PTR
#ifdef __cplusplus
#define NULL_PTR (0)
#else /*#ifdef __cplusplus */
#define NULL_PTR ((void *)0)
#endif /*#ifdef __cplusplus */
#endif /*#ifndef NULL_PTR */
#ifndef CFG_LONG_SIZE_T
#define CFG_LONG_SIZE_T (0)
#endif
#if defined(__DCC__)
#include "CompilerDcc.h"
#elif defined(__HIGHTEC__)
#include "CompilerGnuc.h"
#elif defined(__TASKING__)
#include "CompilerTasking.h"
#elif defined(__ghs__)
#include "CompilerGhs.h"
#elif defined(__MSVC__)
#include "CompilerMsvc.h"
#else
/** \addtogroup IfxLld_Cpu_Std_Interrupt
* \{ */
/** \brief Macro to define Interrupt Service Routine.
* This macro makes following definitions:\n
* 1) Define linker section as .intvec_tc<vector number>_<interrupt priority>.\n
* 2) define compiler specific attribute for the interrupt functions.\n
* 3) define the Interrupt service routine as Isr function.\n
* To get details about usage of this macro, refer \ref IfxLld_Cpu_Irq_Usage
*
* \param isr Name of the Isr function.
* \param vectabNum Vector table number.
* \param prio Interrupt priority. Refer Usage of Interrupt Macro for more details.
*/
#define IFX_INTERRUPT(isr, vectabNum, prio)
/** \} */
#error "Compiler unsupported"
#endif
#if defined(__HIGHTEC__)
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec aw 4)
#define DATA_SECTION(sec) _Pragma(#sec)
#define END_DATA_SECTION DATA_SECTION(section)
#elif defined(__TASKING__)
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section farbss #sec)
#define DATA_SECTION(sec) _Pragma(#sec)
#define END_DATA_SECTION DATA_SECTION(section farbss align restore) \
DATA_SECTION(section farbss)
#elif defined(__DCC__)
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec WX)
#define DATA_SECTION(sec) _Pragma(#sec)
#define END_DATA_SECTION DATA_SECTION(section DATA X)
#elif defined(__ghs__)
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec WX)
#define DATA_SECTION(sec) _Pragma(#sec)
#define END_DATA_SECTION DATA_SECTION(section DATA X)
#else
#error "Please specify compiler."
#endif
/* Functions prototypes */
/******************************************************************************/
void Ifx_C_Init(void);
/******************************************************************************/
#endif /* COMPILERS_H */

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/**
* \file IfxAsclin_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Asclin_Registers Asclin Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Asclin_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Asclin_Registers
*
* \defgroup IfxSfr_Asclin_Registers_union Register unions
* \ingroup IfxSfr_Asclin_Registers
*
* \defgroup IfxSfr_Asclin_Registers_struct Memory map
* \ingroup IfxSfr_Asclin_Registers
*/
#ifndef IFXASCLIN_REGDEF_H
#define IFXASCLIN_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Asclin_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_ASCLIN_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_ASCLIN_ACCEN0_Bits;
/** \brief Access Enable Register 1 */
typedef struct _Ifx_ASCLIN_ACCEN1_Bits
{
Ifx_UReg_32Bit reserved_0:32; /**< \brief [31:0] \internal Reserved */
} Ifx_ASCLIN_ACCEN1_Bits;
/** \brief Bit Configuration Register */
typedef struct _Ifx_ASCLIN_BITCON_Bits
{
Ifx_UReg_32Bit PRESCALER:12; /**< \brief [11:0] Prescaling of the Fractional Divider - PRESCALER (rw) */
Ifx_UReg_32Bit reserved_12:4; /**< \brief [15:12] \internal Reserved */
Ifx_UReg_32Bit OVERSAMPLING:4; /**< \brief [19:16] Oversampling Factor - OVERSAMPLING (rw) */
Ifx_UReg_32Bit reserved_20:4; /**< \brief [23:20] \internal Reserved */
Ifx_UReg_32Bit SAMPLEPOINT:4; /**< \brief [27:24] Sample Point Position - SAMPLEPOINT (rw) */
Ifx_UReg_32Bit reserved_28:3; /**< \brief [30:28] \internal Reserved */
Ifx_UReg_32Bit SM:1; /**< \brief [31:31] Sample Mode - SM (rw) */
} Ifx_ASCLIN_BITCON_Bits;
/** \brief Baud Rate Detection Register */
typedef struct _Ifx_ASCLIN_BRD_Bits
{
Ifx_UReg_32Bit LOWERLIMIT:8; /**< \brief [7:0] Lower Limit - LOWERLIMIT (rw) */
Ifx_UReg_32Bit UPPERLIMIT:8; /**< \brief [15:8] Upper Limit - UPPERLIMIT (rw) */
Ifx_UReg_32Bit MEASURED:12; /**< \brief [27:16] Measured Value of 8-bits from Sync Field - MEASURED (rh) */
Ifx_UReg_32Bit reserved_28:4; /**< \brief [31:28] \internal Reserved */
} Ifx_ASCLIN_BRD_Bits;
/** \brief Baud Rate Generation Register */
typedef struct _Ifx_ASCLIN_BRG_Bits
{
Ifx_UReg_32Bit DENOMINATOR:12; /**< \brief [11:0] Denominator - DENOMINATOR (rw) */
Ifx_UReg_32Bit reserved_12:4; /**< \brief [15:12] \internal Reserved */
Ifx_UReg_32Bit NUMERATOR:12; /**< \brief [27:16] Numerator - NUMERATOR (rw) */
Ifx_UReg_32Bit reserved_28:4; /**< \brief [31:28] \internal Reserved */
} Ifx_ASCLIN_BRG_Bits;
/** \brief Clock Control Register */
typedef struct _Ifx_ASCLIN_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (rh) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control - EDIS (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_ASCLIN_CLC_Bits;
/** \brief Clock Selection Register */
typedef struct _Ifx_ASCLIN_CSR_Bits
{
Ifx_UReg_32Bit CLKSEL:5; /**< \brief [4:0] Baud Rate Logic Clock Select - CLKSEL (rw) */
Ifx_UReg_32Bit reserved_5:26; /**< \brief [30:5] \internal Reserved */
Ifx_UReg_32Bit CON:1; /**< \brief [31:31] Clock On Flag - CON (rh) */
} Ifx_ASCLIN_CSR_Bits;
/** \brief Data Configuration Register */
typedef struct _Ifx_ASCLIN_DATCON_Bits
{
Ifx_UReg_32Bit DATLEN:4; /**< \brief [3:0] Data Length - DATLEN (rw) */
Ifx_UReg_32Bit reserved_4:9; /**< \brief [12:4] \internal Reserved */
Ifx_UReg_32Bit HO:1; /**< \brief [13:13] Header Only - HO (rw) */
Ifx_UReg_32Bit RM:1; /**< \brief [14:14] Response Mode - RM (rw) */
Ifx_UReg_32Bit CSM:1; /**< \brief [15:15] Checksum Mode - CSM (rw) */
Ifx_UReg_32Bit RESPONSE:8; /**< \brief [23:16] Response Timeout Threshold Value - RESPONSE (rw) */
Ifx_UReg_32Bit reserved_24:8; /**< \brief [31:24] \internal Reserved */
} Ifx_ASCLIN_DATCON_Bits;
/** \brief Flags Register */
typedef struct _Ifx_ASCLIN_FLAGS_Bits
{
Ifx_UReg_32Bit TH:1; /**< \brief [0:0] Transmit Header End Flag - TH (rh) */
Ifx_UReg_32Bit TR:1; /**< \brief [1:1] Transmit Response End Flag - TR (rh) */
Ifx_UReg_32Bit RH:1; /**< \brief [2:2] Receive Header End Flag - RH (rh) */
Ifx_UReg_32Bit RR:1; /**< \brief [3:3] Receive Response End Flag - RR (rh) */
Ifx_UReg_32Bit reserved_4:1; /**< \brief [4:4] \internal Reserved */
Ifx_UReg_32Bit FED:1; /**< \brief [5:5] Falling Edge from Level 1 to Level 0 Detected - FED (rh) */
Ifx_UReg_32Bit RED:1; /**< \brief [6:6] Rising Edge from Level 0 to Level 1 Detected - RED (rh) */
Ifx_UReg_32Bit reserved_7:6; /**< \brief [12:7] \internal Reserved */
Ifx_UReg_32Bit TWRQ:1; /**< \brief [13:13] Transmit Wake Request Flag - TWRQ (rh) */
Ifx_UReg_32Bit THRQ:1; /**< \brief [14:14] Transmit Header Request Flag - THRQ (rh) */
Ifx_UReg_32Bit TRRQ:1; /**< \brief [15:15] Transmit Response Request Flag - TRRQ (rh) */
Ifx_UReg_32Bit PE:1; /**< \brief [16:16] Parity Error Flag - PE (rh) */
Ifx_UReg_32Bit TC:1; /**< \brief [17:17] Transmission Completed Flag - TC (rh) */
Ifx_UReg_32Bit FE:1; /**< \brief [18:18] Framing Error Flag - FE (rh) */
Ifx_UReg_32Bit HT:1; /**< \brief [19:19] Header Timeout Flag - HT (rh) */
Ifx_UReg_32Bit RT:1; /**< \brief [20:20] Response Timeout Flag - RT (rh) */
Ifx_UReg_32Bit BD:1; /**< \brief [21:21] Break Detected Flag - BD (rh) */
Ifx_UReg_32Bit LP:1; /**< \brief [22:22] LIN Parity Error Flag - LP (rh) */
Ifx_UReg_32Bit LA:1; /**< \brief [23:23] LIN Autobaud Detection Error Flag - LA (rh) */
Ifx_UReg_32Bit LC:1; /**< \brief [24:24] LIN Checksum Error Flag - LC (rh) */
Ifx_UReg_32Bit CE:1; /**< \brief [25:25] Collision Detection Error Flag - CE (rh) */
Ifx_UReg_32Bit RFO:1; /**< \brief [26:26] Receive FIFO Overflow Flag - RFO (rh) */
Ifx_UReg_32Bit RFU:1; /**< \brief [27:27] Receive FIFO Underflow Flag - RFU (rh) */
Ifx_UReg_32Bit RFL:1; /**< \brief [28:28] Receive FIFO Level Flag - RFL (rh) */
Ifx_UReg_32Bit reserved_29:1; /**< \brief [29:29] \internal Reserved */
Ifx_UReg_32Bit TFO:1; /**< \brief [30:30] Transmit FIFO Overflow Flag - TFO (rh) */
Ifx_UReg_32Bit TFL:1; /**< \brief [31:31] Transmit FIFO Level Flag - TFL (rh) */
} Ifx_ASCLIN_FLAGS_Bits;
/** \brief Flags Clear Register */
typedef struct _Ifx_ASCLIN_FLAGSCLEAR_Bits
{
Ifx_UReg_32Bit THC:1; /**< \brief [0:0] Flag Clear Bit - THC (w) */
Ifx_UReg_32Bit TRC:1; /**< \brief [1:1] Flag Clear Bit - TRC (w) */
Ifx_UReg_32Bit RHC:1; /**< \brief [2:2] Flag Clear Bit - RHC (w) */
Ifx_UReg_32Bit RRC:1; /**< \brief [3:3] Flag Clear Bit - RRC (w) */
Ifx_UReg_32Bit reserved_4:1; /**< \brief [4:4] \internal Reserved */
Ifx_UReg_32Bit FEDC:1; /**< \brief [5:5] Flag Clear Bit - FEDC (w) */
Ifx_UReg_32Bit REDC:1; /**< \brief [6:6] Flag Clear Bit - REDC (w) */
Ifx_UReg_32Bit reserved_7:6; /**< \brief [12:7] \internal Reserved */
Ifx_UReg_32Bit TWRQC:1; /**< \brief [13:13] Flag Clear Bit - TWRQC (w) */
Ifx_UReg_32Bit THRQC:1; /**< \brief [14:14] Flag Clear Bit - THRQC (w) */
Ifx_UReg_32Bit TRRQC:1; /**< \brief [15:15] Flag Clear Bit - TRRQC (w) */
Ifx_UReg_32Bit PEC:1; /**< \brief [16:16] Flag Clear Bit - PEC (w) */
Ifx_UReg_32Bit TCC:1; /**< \brief [17:17] Flag Clear Bit - TCC (w) */
Ifx_UReg_32Bit FEC:1; /**< \brief [18:18] Flag Clear Bit - FEC (w) */
Ifx_UReg_32Bit HTC:1; /**< \brief [19:19] Flag Clear Bit - HTC (w) */
Ifx_UReg_32Bit RTC:1; /**< \brief [20:20] Flag Clear Bit - RTC (w) */
Ifx_UReg_32Bit BDC:1; /**< \brief [21:21] Flag Clear Bit - BDC (w) */
Ifx_UReg_32Bit LPC:1; /**< \brief [22:22] Flag Clear Bit - LPC (w) */
Ifx_UReg_32Bit LAC:1; /**< \brief [23:23] Flag Clear Bit - LAC (w) */
Ifx_UReg_32Bit LCC:1; /**< \brief [24:24] Flag Clear Bit - LCC (w) */
Ifx_UReg_32Bit CEC:1; /**< \brief [25:25] Flag Clear Bit - CEC (w) */
Ifx_UReg_32Bit RFOC:1; /**< \brief [26:26] Flag Clear Bit - RFOC (w) */
Ifx_UReg_32Bit RFUC:1; /**< \brief [27:27] Flag Clear Bit - RFUC (w) */
Ifx_UReg_32Bit RFLC:1; /**< \brief [28:28] Flag Clear Bit - RFLC (w) */
Ifx_UReg_32Bit reserved_29:1; /**< \brief [29:29] \internal Reserved */
Ifx_UReg_32Bit TFOC:1; /**< \brief [30:30] Flag Clear Bit - TFOC (w) */
Ifx_UReg_32Bit TFLC:1; /**< \brief [31:31] Flag Clear Bit - TFLC (w) */
} Ifx_ASCLIN_FLAGSCLEAR_Bits;
/** \brief Flags Enable Register */
typedef struct _Ifx_ASCLIN_FLAGSENABLE_Bits
{
Ifx_UReg_32Bit THE:1; /**< \brief [0:0] Flag Enable Bit - THE (rw) */
Ifx_UReg_32Bit TRE:1; /**< \brief [1:1] Flag Enable Bit - TRE (rw) */
Ifx_UReg_32Bit RHE:1; /**< \brief [2:2] Flag Enable Bit - RHE (rw) */
Ifx_UReg_32Bit RRE:1; /**< \brief [3:3] Flag Enable Bit - RRE (rw) */
Ifx_UReg_32Bit reserved_4:1; /**< \brief [4:4] \internal Reserved */
Ifx_UReg_32Bit FEDE:1; /**< \brief [5:5] Flag Enable Bit - FEDE (rw) */
Ifx_UReg_32Bit REDE:1; /**< \brief [6:6] Flag Enable Bit - REDE (rw) */
Ifx_UReg_32Bit reserved_7:9; /**< \brief [15:7] \internal Reserved */
Ifx_UReg_32Bit PEE:1; /**< \brief [16:16] Flag Enable Bit - PEE (rw) */
Ifx_UReg_32Bit TCE:1; /**< \brief [17:17] Flag Enable Bit - TCE (rw) */
Ifx_UReg_32Bit FEE:1; /**< \brief [18:18] Flag Enable Bit - FEE (rw) */
Ifx_UReg_32Bit HTE:1; /**< \brief [19:19] Flag Enable Bit - HTE (rw) */
Ifx_UReg_32Bit RTE:1; /**< \brief [20:20] Flag Enable Bit - RTE (rw) */
Ifx_UReg_32Bit BDE:1; /**< \brief [21:21] Flag Enable Bit - BDE (rw) */
Ifx_UReg_32Bit LPE:1; /**< \brief [22:22] Flag Enable Bit - LPE (rw) */
Ifx_UReg_32Bit LAE:1; /**< \brief [23:23] Flag Enable Bit - LAE (rw) */
Ifx_UReg_32Bit LCE:1; /**< \brief [24:24] Flag Enable Bit - LCE (rw) */
Ifx_UReg_32Bit CEE:1; /**< \brief [25:25] Flag Enable Bit - CEE (rw) */
Ifx_UReg_32Bit RFOE:1; /**< \brief [26:26] Flag Enable Bit - RFOE (rw) */
Ifx_UReg_32Bit RFUE:1; /**< \brief [27:27] Flag Enable Bit - RFUE (rw) */
Ifx_UReg_32Bit RFLE:1; /**< \brief [28:28] Flag Enable Bit - RFLE (rw) */
Ifx_UReg_32Bit reserved_29:1; /**< \brief [29:29] \internal Reserved */
Ifx_UReg_32Bit TFOE:1; /**< \brief [30:30] Flag Enable Bit - TFOE (rw) */
Ifx_UReg_32Bit TFLE:1; /**< \brief [31:31] Flag Enable Bit - TFLE (rw) */
} Ifx_ASCLIN_FLAGSENABLE_Bits;
/** \brief Flags Set Register */
typedef struct _Ifx_ASCLIN_FLAGSSET_Bits
{
Ifx_UReg_32Bit THS:1; /**< \brief [0:0] Flag Set Bit - THS (w) */
Ifx_UReg_32Bit TRS:1; /**< \brief [1:1] Flag Set Bit - TRS (w) */
Ifx_UReg_32Bit RHS:1; /**< \brief [2:2] Flag Set Bit - RHS (w) */
Ifx_UReg_32Bit RRS:1; /**< \brief [3:3] Flag Set Bit - RRS (w) */
Ifx_UReg_32Bit reserved_4:1; /**< \brief [4:4] \internal Reserved */
Ifx_UReg_32Bit FEDS:1; /**< \brief [5:5] Flag Set Bit - FEDS (w) */
Ifx_UReg_32Bit REDS:1; /**< \brief [6:6] Flag Set Bit - REDS (w) */
Ifx_UReg_32Bit reserved_7:6; /**< \brief [12:7] \internal Reserved */
Ifx_UReg_32Bit TWRQS:1; /**< \brief [13:13] Flag Set Bit - TWRQS (w) */
Ifx_UReg_32Bit THRQS:1; /**< \brief [14:14] Flag Set Bit - THRQS (w) */
Ifx_UReg_32Bit TRRQS:1; /**< \brief [15:15] Flag Set Bit - TRRQS (w) */
Ifx_UReg_32Bit PES:1; /**< \brief [16:16] Flag Set Bit - PES (w) */
Ifx_UReg_32Bit TCS:1; /**< \brief [17:17] Flag Set Bit - TCS (w) */
Ifx_UReg_32Bit FES:1; /**< \brief [18:18] Flag Set Bit - FES (w) */
Ifx_UReg_32Bit HTS:1; /**< \brief [19:19] Flag Set Bit - HTS (w) */
Ifx_UReg_32Bit RTS:1; /**< \brief [20:20] Flag Set Bit - RTS (w) */
Ifx_UReg_32Bit BDS:1; /**< \brief [21:21] Flag Set Bit - BDS (w) */
Ifx_UReg_32Bit LPS:1; /**< \brief [22:22] Flag Set Bit - LPS (w) */
Ifx_UReg_32Bit LAS:1; /**< \brief [23:23] Flag Set Bit - LAS (w) */
Ifx_UReg_32Bit LCS:1; /**< \brief [24:24] Flag Set Bit - LCS (w) */
Ifx_UReg_32Bit CES:1; /**< \brief [25:25] Flag Set Bit - CES (w) */
Ifx_UReg_32Bit RFOS:1; /**< \brief [26:26] Flag Set Bit - RFOS (w) */
Ifx_UReg_32Bit RFUS:1; /**< \brief [27:27] Flag Set Bit - RFUS (w) */
Ifx_UReg_32Bit RFLS:1; /**< \brief [28:28] Flag Set Bit - RFLS (w) */
Ifx_UReg_32Bit reserved_29:1; /**< \brief [29:29] \internal Reserved */
Ifx_UReg_32Bit TFOS:1; /**< \brief [30:30] Flag Set Bit - TFOS (w) */
Ifx_UReg_32Bit TFLS:1; /**< \brief [31:31] Flag Set Bit - TFLS (w) */
} Ifx_ASCLIN_FLAGSSET_Bits;
/** \brief Frame Control Register */
typedef struct _Ifx_ASCLIN_FRAMECON_Bits
{
Ifx_UReg_32Bit reserved_0:6; /**< \brief [5:0] \internal Reserved */
Ifx_UReg_32Bit IDLE:3; /**< \brief [8:6] Duration of the IDLE delay - IDLE (rw) */
Ifx_UReg_32Bit STOP:3; /**< \brief [11:9] Number of Stop Bits - STOP (rw) */
Ifx_UReg_32Bit LEAD:3; /**< \brief [14:12] Duration of the Leading Delay - LEAD (rw) */
Ifx_UReg_32Bit reserved_15:1; /**< \brief [15:15] \internal Reserved */
Ifx_UReg_32Bit MODE:2; /**< \brief [17:16] Mode Selection - MODE (rw) */
Ifx_UReg_32Bit reserved_18:10; /**< \brief [27:18] \internal Reserved */
Ifx_UReg_32Bit MSB:1; /**< \brief [28:28] Shift Direction - MSB (rw) */
Ifx_UReg_32Bit CEN:1; /**< \brief [29:29] Collision Detection Enable - CEN (rw) */
Ifx_UReg_32Bit PEN:1; /**< \brief [30:30] Parity Enable - PEN (rw) */
Ifx_UReg_32Bit ODD:1; /**< \brief [31:31] Parity Type - ODD (rw) */
} Ifx_ASCLIN_FRAMECON_Bits;
/** \brief Module Identification Register */
typedef struct _Ifx_ASCLIN_ID_Bits
{
Ifx_UReg_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number - MODREV (r) */
Ifx_UReg_32Bit MODTYPE:8; /**< \brief [15:8] Module Type - MODTYPE (r) */
Ifx_UReg_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value - MODNUMBER (r) */
} Ifx_ASCLIN_ID_Bits;
/** \brief Input and Output Control Register */
typedef struct _Ifx_ASCLIN_IOCR_Bits
{
Ifx_UReg_32Bit ALTI:3; /**< \brief [2:0] Alternate Input Select - ALTI (rw) */
Ifx_UReg_32Bit reserved_3:1; /**< \brief [3:3] \internal Reserved */
Ifx_UReg_32Bit DEPTH:6; /**< \brief [9:4] Digital Glitch Filter Depth - DEPTH (rw) */
Ifx_UReg_32Bit reserved_10:6; /**< \brief [15:10] \internal Reserved */
Ifx_UReg_32Bit CTS:2; /**< \brief [17:16] CTS Select - CTS (rw) */
Ifx_UReg_32Bit reserved_18:7; /**< \brief [24:18] \internal Reserved */
Ifx_UReg_32Bit RCPOL:1; /**< \brief [25:25] RTS CTS Polarity - RCPOL (rw) */
Ifx_UReg_32Bit CPOL:1; /**< \brief [26:26] Clock Polarity in Synchronous Mode - CPOL (rw) */
Ifx_UReg_32Bit SPOL:1; /**< \brief [27:27] Slave Polarity in Synchronous Mode - SPOL (rw) */
Ifx_UReg_32Bit LB:1; /**< \brief [28:28] Loop Back Mode - LB (rw) */
Ifx_UReg_32Bit CTSEN:1; /**< \brief [29:29] Input Signal CTS Enable - CTSEN (rw) */
Ifx_UReg_32Bit RXM:1; /**< \brief [30:30] Receive Monitor - RXM (rh) */
Ifx_UReg_32Bit TXM:1; /**< \brief [31:31] Transmit Monitor - TXM (rh) */
} Ifx_ASCLIN_IOCR_Bits;
/** \brief Kernel Reset Register 0 */
typedef struct _Ifx_ASCLIN_KRST0_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status - RSTSTAT (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_ASCLIN_KRST0_Bits;
/** \brief Kernel Reset Register 1 */
typedef struct _Ifx_ASCLIN_KRST1_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_ASCLIN_KRST1_Bits;
/** \brief Kernel Reset Status Clear Register */
typedef struct _Ifx_ASCLIN_KRSTCLR_Bits
{
Ifx_UReg_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear - CLR (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_ASCLIN_KRSTCLR_Bits;
/** \brief LIN Break Timer Register */
typedef struct _Ifx_ASCLIN_LIN_BTIMER_Bits
{
Ifx_UReg_32Bit BREAK:6; /**< \brief [5:0] Break Pulse Generation and Detection - BREAK (rw) */
Ifx_UReg_32Bit reserved_6:26; /**< \brief [31:6] \internal Reserved */
} Ifx_ASCLIN_LIN_BTIMER_Bits;
/** \brief LIN Control Register */
typedef struct _Ifx_ASCLIN_LIN_CON_Bits
{
Ifx_UReg_32Bit reserved_0:23; /**< \brief [22:0] \internal Reserved */
Ifx_UReg_32Bit CSI:1; /**< \brief [23:23] Checksum Injection - CSI (rw) */
Ifx_UReg_32Bit reserved_24:1; /**< \brief [24:24] \internal Reserved */
Ifx_UReg_32Bit CSEN:1; /**< \brief [25:25] Hardware Checksum Enable - CSEN (rw) */
Ifx_UReg_32Bit MS:1; /**< \brief [26:26] Master Slave Mode - MS (rw) */
Ifx_UReg_32Bit ABD:1; /**< \brief [27:27] Autobaud Detection - ABD (rw) */
Ifx_UReg_32Bit reserved_28:4; /**< \brief [31:28] \internal Reserved */
} Ifx_ASCLIN_LIN_CON_Bits;
/** \brief LIN Header Timer Register */
typedef struct _Ifx_ASCLIN_LIN_HTIMER_Bits
{
Ifx_UReg_32Bit HEADER:8; /**< \brief [7:0] Header Timeout Threshold Value - HEADER (rw) */
Ifx_UReg_32Bit reserved_8:24; /**< \brief [31:8] \internal Reserved */
} Ifx_ASCLIN_LIN_HTIMER_Bits;
/** \brief OCDS Control and Status */
typedef struct _Ifx_ASCLIN_OCS_Bits
{
Ifx_UReg_32Bit reserved_0:24; /**< \brief [23:0] \internal Reserved */
Ifx_UReg_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control - SUS (rw) */
Ifx_UReg_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection - SUS_P (w) */
Ifx_UReg_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State - SUSSTA (rh) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_ASCLIN_OCS_Bits;
/** \brief Receive Data Register */
typedef struct _Ifx_ASCLIN_RXDATA_Bits
{
Ifx_UReg_32Bit DATA:32; /**< \brief [31:0] Data - DATA (rh) */
} Ifx_ASCLIN_RXDATA_Bits;
/** \brief Receive Data Debug Register */
typedef struct _Ifx_ASCLIN_RXDATAD_Bits
{
Ifx_UReg_32Bit DATA:32; /**< \brief [31:0] Data - DATA (rh) */
} Ifx_ASCLIN_RXDATAD_Bits;
/** \brief RX FIFO Configuration Register */
typedef struct _Ifx_ASCLIN_RXFIFOCON_Bits
{
Ifx_UReg_32Bit FLUSH:1; /**< \brief [0:0] Flush the receive FIFO - FLUSH (w) */
Ifx_UReg_32Bit ENI:1; /**< \brief [1:1] Receive FIFO Inlet Enable - ENI (rwh) */
Ifx_UReg_32Bit reserved_2:2; /**< \brief [3:2] \internal Reserved */
Ifx_UReg_32Bit FM:2; /**< \brief [5:4] RXFIFO Mode - FM (rw) */
Ifx_UReg_32Bit OUTW:2; /**< \brief [7:6] Receive FIFO Outlet Width - OUTW (rw) */
Ifx_UReg_32Bit INTLEVEL:4; /**< \brief [11:8] FIFO Interrupt Level - INTLEVEL (rw) */
Ifx_UReg_32Bit reserved_12:4; /**< \brief [15:12] \internal Reserved */
Ifx_UReg_32Bit FILL:5; /**< \brief [20:16] FIFO Filling Level - FILL (rh) */
Ifx_UReg_32Bit reserved_21:10; /**< \brief [30:21] \internal Reserved */
Ifx_UReg_32Bit BUF:1; /**< \brief [31:31] Receive Buffer Mode - BUF (rw) */
} Ifx_ASCLIN_RXFIFOCON_Bits;
/** \brief Transmit Data Register */
typedef struct _Ifx_ASCLIN_TXDATA_Bits
{
Ifx_UReg_32Bit DATA:32; /**< \brief [31:0] Data - DATA (w) */
} Ifx_ASCLIN_TXDATA_Bits;
/** \brief TX FIFO Configuration Register */
typedef struct _Ifx_ASCLIN_TXFIFOCON_Bits
{
Ifx_UReg_32Bit FLUSH:1; /**< \brief [0:0] Flush the transmit FIFO - FLUSH (w) */
Ifx_UReg_32Bit ENO:1; /**< \brief [1:1] Transmit FIFO Outlet Enable - ENO (rw) */
Ifx_UReg_32Bit reserved_2:2; /**< \brief [3:2] \internal Reserved */
Ifx_UReg_32Bit FM:2; /**< \brief [5:4] TXFIFO Mode - FM (rw) */
Ifx_UReg_32Bit INW:2; /**< \brief [7:6] Transmit FIFO Inlet Width - INW (rw) */
Ifx_UReg_32Bit INTLEVEL:4; /**< \brief [11:8] FIFO Interrupt Level - INTLEVEL (rw) */
Ifx_UReg_32Bit reserved_12:4; /**< \brief [15:12] \internal Reserved */
Ifx_UReg_32Bit FILL:5; /**< \brief [20:16] FIFO Filling Level - FILL (rh) */
Ifx_UReg_32Bit reserved_21:11; /**< \brief [31:21] \internal Reserved */
} Ifx_ASCLIN_TXFIFOCON_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_asclin_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_ACCEN0;
/** \brief Access Enable Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_ACCEN1_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_ACCEN1;
/** \brief Bit Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_BITCON_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_BITCON;
/** \brief Baud Rate Detection Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_BRD_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_BRD;
/** \brief Baud Rate Generation Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_BRG_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_BRG;
/** \brief Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_CLC;
/** \brief Clock Selection Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_CSR_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_CSR;
/** \brief Data Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_DATCON_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_DATCON;
/** \brief Flags Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_FLAGS_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_FLAGS;
/** \brief Flags Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_FLAGSCLEAR_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_FLAGSCLEAR;
/** \brief Flags Enable Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_FLAGSENABLE_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_FLAGSENABLE;
/** \brief Flags Set Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_FLAGSSET_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_FLAGSSET;
/** \brief Frame Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_FRAMECON_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_FRAMECON;
/** \brief Module Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_ID_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_ID;
/** \brief Input and Output Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_IOCR_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_IOCR;
/** \brief Kernel Reset Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_KRST0_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_KRST0;
/** \brief Kernel Reset Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_KRST1_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_KRST1;
/** \brief Kernel Reset Status Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_KRSTCLR_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_KRSTCLR;
/** \brief LIN Break Timer Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_LIN_BTIMER_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_LIN_BTIMER;
/** \brief LIN Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_LIN_CON_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_LIN_CON;
/** \brief LIN Header Timer Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_LIN_HTIMER_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_LIN_HTIMER;
/** \brief OCDS Control and Status */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_OCS_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_OCS;
/** \brief Receive Data Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_RXDATA_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_RXDATA;
/** \brief Receive Data Debug Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_RXDATAD_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_RXDATAD;
/** \brief RX FIFO Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_RXFIFOCON_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_RXFIFOCON;
/** \brief Transmit Data Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_TXDATA_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_TXDATA;
/** \brief TX FIFO Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_ASCLIN_TXFIFOCON_Bits B; /**< \brief Bitfield access */
} Ifx_ASCLIN_TXFIFOCON;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Asclin_LIN_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief LIN object */
typedef volatile struct _Ifx_ASCLIN_LIN
{
Ifx_ASCLIN_LIN_CON CON; /**< \brief 0, LIN Control Register*/
Ifx_ASCLIN_LIN_BTIMER BTIMER; /**< \brief 4, LIN Break Timer Register*/
Ifx_ASCLIN_LIN_HTIMER HTIMER; /**< \brief 8, LIN Header Timer Register*/
} Ifx_ASCLIN_LIN;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Asclin_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief ASCLIN object */
typedef volatile struct _Ifx_ASCLIN
{
Ifx_ASCLIN_CLC CLC; /**< \brief 0, Clock Control Register*/
Ifx_ASCLIN_IOCR IOCR; /**< \brief 4, Input and Output Control Register*/
Ifx_ASCLIN_ID ID; /**< \brief 8, Module Identification Register*/
Ifx_ASCLIN_TXFIFOCON TXFIFOCON; /**< \brief C, TX FIFO Configuration Register*/
Ifx_ASCLIN_RXFIFOCON RXFIFOCON; /**< \brief 10, RX FIFO Configuration Register*/
Ifx_ASCLIN_BITCON BITCON; /**< \brief 14, Bit Configuration Register*/
Ifx_ASCLIN_FRAMECON FRAMECON; /**< \brief 18, Frame Control Register*/
Ifx_ASCLIN_DATCON DATCON; /**< \brief 1C, Data Configuration Register*/
Ifx_ASCLIN_BRG BRG; /**< \brief 20, Baud Rate Generation Register*/
Ifx_ASCLIN_BRD BRD; /**< \brief 24, Baud Rate Detection Register*/
Ifx_ASCLIN_LIN LIN; /**< \brief 28, LIN Header Timer Register*/
Ifx_ASCLIN_FLAGS FLAGS; /**< \brief 34, Flags Register*/
Ifx_ASCLIN_FLAGSSET FLAGSSET; /**< \brief 38, Flags Set Register*/
Ifx_ASCLIN_FLAGSCLEAR FLAGSCLEAR; /**< \brief 3C, Flags Clear Register*/
Ifx_ASCLIN_FLAGSENABLE FLAGSENABLE; /**< \brief 40, Flags Enable Register*/
Ifx_ASCLIN_TXDATA TXDATA; /**< \brief 44, Transmit Data Register*/
Ifx_ASCLIN_RXDATA RXDATA; /**< \brief 48, Receive Data Register*/
Ifx_ASCLIN_CSR CSR; /**< \brief 4C, Clock Selection Register*/
Ifx_ASCLIN_RXDATAD RXDATAD; /**< \brief 50, Receive Data Debug Register*/
Ifx_UReg_8Bit reserved_54[148]; /**< \brief 54, \internal Reserved */
Ifx_ASCLIN_OCS OCS; /**< \brief E8, OCDS Control and Status*/
Ifx_ASCLIN_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register*/
Ifx_ASCLIN_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1*/
Ifx_ASCLIN_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0*/
Ifx_ASCLIN_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1*/
Ifx_ASCLIN_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0*/
} Ifx_ASCLIN;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXASCLIN_REGDEF_H */

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/**
* \file IfxCbs_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Cbs_Registers_Cfg Cbs address
* \ingroup IfxSfr_Cbs_Registers
*
* \defgroup IfxSfr_Cbs_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Cbs_Registers_Cfg
*
* \defgroup IfxSfr_Cbs_Registers_Cfg_Cbs 2-CBS
* \ingroup IfxSfr_Cbs_Registers_Cfg
*
*
*/
#ifndef IFXCBS_REG_H
#define IFXCBS_REG_H 1
/******************************************************************************/
#include "IfxCbs_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Cbs_Registers_Cfg_BaseAddress
* \{ */
/** \brief CBS object */
#define MODULE_CBS /*lint --e(923, 9078)*/ ((*(Ifx_CBS*)0xF0000400u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Cbs_Registers_Cfg_Cbs
* \{ */
/** \brief 8, Module Identification Register */
#define CBS_JDPID /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_JDPID*)0xF0000408u)
/** \brief C, OCDS Interface Mode Register */
#define CBS_OIFM /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_OIFM*)0xF000040Cu)
/** \brief 10, TG Input Pins Routing */
#define CBS_TIPR /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TIPR*)0xF0000410u)
/** \brief 14, TG Output Pins Routing */
#define CBS_TOPR /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TOPR*)0xF0000414u)
/** \brief 18, TG Output Pins Pulse Stretcher */
#define CBS_TOPPS /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TOPPS*)0xF0000418u)
/** \brief 1C, TG Capture for TG Input Pins */
#define CBS_TCIP /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TCIP*)0xF000041Cu)
/** \brief 20, TG Routing for CPU0 */
#define CBS_TRC0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRC*)0xF0000420u)
/** \brief 24, TG Routing for CPU1 */
#define CBS_TRC1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRC*)0xF0000424u)
/** \brief 28, TG Routing for CPU2 */
#define CBS_TRC2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRC*)0xF0000428u)
/** \brief 2C, TG Routing for CPU3 */
#define CBS_TRC3 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRC*)0xF000042Cu)
/** \brief 30, TG Routing for CPU4 */
#define CBS_TRC4 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRC*)0xF0000430u)
/** \brief 34, TG Routing for CPU5 */
#define CBS_TRC5 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRC*)0xF0000434u)
/** \brief 38, TG Routing for HSMControl */
#define CBS_TRHSM /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRHSM*)0xF0000438u)
/** \brief 3C, TG Routing for MCDS Control */
#define CBS_TRMC /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRMC*)0xF000043Cu)
/** \brief 40, TG Line Counter Control */
#define CBS_TLCC0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLCC*)0xF0000440u)
/** \brief 44, TG Line Counter Control */
#define CBS_TLCC1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLCC*)0xF0000444u)
/** \brief 50, TG Line Counter Value */
#define CBS_TLCV0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLCV*)0xF0000450u)
/** \brief 54, TG Line Counter Value */
#define CBS_TLCV1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLCV*)0xF0000454u)
/** \brief 60, TG Routing for Special Signals */
#define CBS_TRSS /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRSS*)0xF0000460u)
/** \brief 64, JTAGDevice Identification Register */
#define CBS_JTAGID /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_JTAGID*)0xF0000464u)
/** \brief 68, Communication Mode Data Register */
#define CBS_COMDATA /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_COMDATA*)0xF0000468u)
/** \brief 6C, IOClientStatus and Control Register */
#define CBS_IOSR /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_IOSR*)0xF000046Cu)
/** \brief 70, TG Line State */
#define CBS_TLS /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLS*)0xF0000470u)
/** \brief 74, TG Capture for TG Lines */
#define CBS_TCTL /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TCTL*)0xF0000474u)
/** \brief 78, OCDS Enable Control Register */
#define CBS_OEC /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_OEC*)0xF0000478u)
/** \brief 7C, OSCU Control Register */
#define CBS_OCNTRL /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_OCNTRL*)0xF000047Cu)
/** \brief 80, OSCUStatus Register */
#define CBS_OSTATE /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_OSTATE*)0xF0000480u)
/** \brief 84, Internal Mode Status and Control Register */
#define CBS_INTMOD /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_INTMOD*)0xF0000484u)
/** \brief 88, Internally Controlled Trace Source Register */
#define CBS_ICTSA /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_ICTSA*)0xF0000488u)
/** \brief 8C, Internally Controlled Trace Destination Register */
#define CBS_ICTTA /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_ICTTA*)0xF000048Cu)
/** \brief 90, TG Line Control */
#define CBS_TLC /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLC*)0xF0000490u)
/** \brief 94, TG Line 1 Suspend Targets */
#define CBS_TL1ST /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TL1ST*)0xF0000494u)
/** \brief 98, TG Line Capture and Hold Enable */
#define CBS_TLCHE /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLCHE*)0xF0000498u)
/** \brief 9C, TG Line Capture and Hold Clear */
#define CBS_TLCHS /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLCHS*)0xF000049Cu)
/** \brief A0, Set Trigger to Host Register */
#define CBS_TRIGS /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRIGS*)0xF00004A0u)
/** \brief A4, Clear Trigger to Host Register */
#define CBS_TRIGC /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRIGC*)0xF00004A4u)
/** \brief A8, TG Line Timer */
#define CBS_TLT /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLT*)0xF00004A8u)
/** \brief AC, TG Lines for Trigger to Host */
#define CBS_TLTTH /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TLTTH*)0xF00004ACu)
/** \brief B0, TG Capture for Cores - BRKOUT */
#define CBS_TCCB /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TCCB*)0xF00004B0u)
/** \brief B4, TG Capture for Cores - HALT */
#define CBS_TCCH /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TCCH*)0xF00004B4u)
/** \brief B8, TG Capture for OTGB0/1 */
#define CBS_TCTGB /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TCTGB*)0xF00004B8u)
/** \brief BC, TG Capture for MCDS */
#define CBS_TCM /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TCM*)0xF00004BCu)
/** \brief C0, TG Routing Events of CPU0 */
#define CBS_TREC0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C0u)
/** \brief C4, TG Routing Events of CPU1 */
#define CBS_TREC1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C4u)
/** \brief C8, TG Routing Events of CPU2 */
#define CBS_TREC2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C8u)
/** \brief CC, TG Routing Events of CPU3 */
#define CBS_TREC3 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TREC*)0xF00004CCu)
/** \brief D0, TG Routing Events of CPU4 */
#define CBS_TREC4 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TREC*)0xF00004D0u)
/** \brief D4, TG Routing Events of CPU5 */
#define CBS_TREC5 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TREC*)0xF00004D4u)
/** \brief DC, TG Routing for MCDS Triggers */
#define CBS_TRMT /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRMT*)0xF00004DCu)
/** \brief E0, TG Routing for OTGBi Bits [7:0] */
#define CBS_TRTGB0_L /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRTGB_L*)0xF00004E0u)
/** Alias (User Manual Name) for CBS_TRTGB0_L.
* To use register names with standard convension, please use CBS_TRTGB0_L.
*/
#define CBS_TRTGB0L (CBS_TRTGB0_L)
/** \brief E4, TG Routing for OTGBi Bits [15:8] */
#define CBS_TRTGB0_H /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRTGB_H*)0xF00004E4u)
/** Alias (User Manual Name) for CBS_TRTGB0_H.
* To use register names with standard convension, please use CBS_TRTGB0_H.
*/
#define CBS_TRTGB0H (CBS_TRTGB0_H)
/** \brief E8, TG Routing for OTGBi Bits [7:0] */
#define CBS_TRTGB1_L /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRTGB_L*)0xF00004E8u)
/** Alias (User Manual Name) for CBS_TRTGB1_L.
* To use register names with standard convension, please use CBS_TRTGB1_L.
*/
#define CBS_TRTGB1L (CBS_TRTGB1_L)
/** \brief EC, TG Routing for OTGBi Bits [15:8] */
#define CBS_TRTGB1_H /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRTGB_H*)0xF00004ECu)
/** Alias (User Manual Name) for CBS_TRTGB1_H.
* To use register names with standard convension, please use CBS_TRTGB1_H.
*/
#define CBS_TRTGB1H (CBS_TRTGB1_H)
/** \brief F0, IFS Address Register */
#define CBS_IFSA /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_IFSA*)0xF00004F0u)
/** \brief F4, IFS Control Register */
#define CBS_IFSC /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_IFSC*)0xF00004F4u)
/** \brief 100, Trigger to Host Register 0 */
#define CBS_TRIG0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000500u)
/** \brief 104, Trigger to Host Register 1 */
#define CBS_TRIG1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000504u)
/** \brief 108, Trigger to Host Register 2 */
#define CBS_TRIG2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000508u)
/** \brief 10C, Trigger to Host Register 3 */
#define CBS_TRIG3 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRIG*)0xF000050Cu)
/** \brief 110, Trigger to Host Register 4 */
#define CBS_TRIG4 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000510u)
/** \brief 114, Trigger to Host Register 5 */
#define CBS_TRIG5 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000514u)
/** \brief 1F8, Access Enable Register 1 */
#define CBS_ACCEN1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_ACCEN1*)0xF00005F8u)
/** \brief 1FC, Access Enable Register 0 */
#define CBS_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CBS_ACCEN0*)0xF00005FCu)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXCBS_REG_H */

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/**
* \file IfxCcu6_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Ccu6_Registers_Cfg Ccu6 address
* \ingroup IfxSfr_Ccu6_Registers
*
* \defgroup IfxSfr_Ccu6_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Ccu6_Registers_Cfg
*
* \defgroup IfxSfr_Ccu6_Registers_Cfg_Ccu60 2-CCU60
* \ingroup IfxSfr_Ccu6_Registers_Cfg
*
* \defgroup IfxSfr_Ccu6_Registers_Cfg_Ccu61 2-CCU61
* \ingroup IfxSfr_Ccu6_Registers_Cfg
*
*
*/
#ifndef IFXCCU6_REG_H
#define IFXCCU6_REG_H 1
/******************************************************************************/
#include "IfxCcu6_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Ccu6_Registers_Cfg_BaseAddress
* \{ */
/** \brief CCU6 object */
#define MODULE_CCU60 /*lint --e(923, 9078)*/ ((*(Ifx_CCU6*)0xF0002A00u))
#define MODULE_CCU61 /*lint --e(923, 9078)*/ ((*(Ifx_CCU6*)0xF0002B00u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Ccu6_Registers_Cfg_Ccu60
* \{ */
/** \brief 0, Clock Control Register */
#define CCU60_CLC /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CLC*)0xF0002A00u)
/** \brief 4, Module Configuration Register */
#define CCU60_MCFG /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MCFG*)0xF0002A04u)
/** \brief 8, Module Identification Register */
#define CCU60_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_ID*)0xF0002A08u)
/** \brief C, CCU60 Module Output Select Register */
#define CCU60_MOSEL /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MOSEL*)0xF0002A0Cu)
/** \brief 10, Port Input Select Register 0 */
#define CCU60_PISEL0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_PISEL0*)0xF0002A10u)
/** \brief 14, Port Input Select Register 2 */
#define CCU60_PISEL2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_PISEL2*)0xF0002A14u)
/** \brief 1C, Kernel State Control Sensitivity Register */
#define CCU60_KSCSR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_KSCSR*)0xF0002A1Cu)
/** \brief 20, Timer T12 Counter Register */
#define CCU60_T12 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T12*)0xF0002A20u)
/** \brief 24, Timer 12 Period Register */
#define CCU60_T12PR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T12PR*)0xF0002A24u)
/** \brief 28, Dead-Time Control Register for Timer12 */
#define CCU60_T12DTC /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T12DTC*)0xF0002A28u)
/** \brief 30, Capture/Compare Register for Channel CC60 */
#define CCU60_CC6R0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6R*)0xF0002A30u)
/** Alias (User Manual Name) for CCU60_CC6R0.
* To use register names with standard convension, please use CCU60_CC6R0.
*/
#define CCU60_CC60R (CCU60_CC6R0)
/** \brief 34, Capture/Compare Register for Channel CC61 */
#define CCU60_CC6R1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6R*)0xF0002A34u)
/** Alias (User Manual Name) for CCU60_CC6R1.
* To use register names with standard convension, please use CCU60_CC6R1.
*/
#define CCU60_CC61R (CCU60_CC6R1)
/** \brief 38, Capture/Compare Register for Channel CC62 */
#define CCU60_CC6R2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6R*)0xF0002A38u)
/** Alias (User Manual Name) for CCU60_CC6R2.
* To use register names with standard convension, please use CCU60_CC6R2.
*/
#define CCU60_CC62R (CCU60_CC6R2)
/** \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
#define CCU60_CC6SR0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6SR*)0xF0002A40u)
/** Alias (User Manual Name) for CCU60_CC6SR0.
* To use register names with standard convension, please use CCU60_CC6SR0.
*/
#define CCU60_CC60SR (CCU60_CC6SR0)
/** \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
#define CCU60_CC6SR1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6SR*)0xF0002A44u)
/** Alias (User Manual Name) for CCU60_CC6SR1.
* To use register names with standard convension, please use CCU60_CC6SR1.
*/
#define CCU60_CC61SR (CCU60_CC6SR1)
/** \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
#define CCU60_CC6SR2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6SR*)0xF0002A48u)
/** Alias (User Manual Name) for CCU60_CC6SR2.
* To use register names with standard convension, please use CCU60_CC6SR2.
*/
#define CCU60_CC62SR (CCU60_CC6SR2)
/** \brief 50, Timer T13 Counter Register */
#define CCU60_T13 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T13*)0xF0002A50u)
/** \brief 54, Timer 13 Period Register */
#define CCU60_T13PR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T13PR*)0xF0002A54u)
/** \brief 58, Compare Register for T13 */
#define CCU60_CC63R /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC63R*)0xF0002A58u)
/** \brief 5C, Compare Shadow Register for T13 */
#define CCU60_CC63SR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC63SR*)0xF0002A5Cu)
/** \brief 60, Compare State Register */
#define CCU60_CMPSTAT /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CMPSTAT*)0xF0002A60u)
/** \brief 64, Compare State Modification Register */
#define CCU60_CMPMODIF /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CMPMODIF*)0xF0002A64u)
/** \brief 68, T12 Mode Select Register */
#define CCU60_T12MSEL /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T12MSEL*)0xF0002A68u)
/** \brief 70, Timer Control Register 0 */
#define CCU60_TCTR0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_TCTR0*)0xF0002A70u)
/** \brief 74, Timer Control Register 2 */
#define CCU60_TCTR2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_TCTR2*)0xF0002A74u)
/** \brief 78, Timer Control Register 4 */
#define CCU60_TCTR4 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_TCTR4*)0xF0002A78u)
/** \brief 80, Modulation Control Register */
#define CCU60_MODCTR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MODCTR*)0xF0002A80u)
/** \brief 84, Trap Control Register */
#define CCU60_TRPCTR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_TRPCTR*)0xF0002A84u)
/** \brief 88, Passive State Level Register */
#define CCU60_PSLR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_PSLR*)0xF0002A88u)
/** \brief 8C, Multi-Channel Mode Output Shadow Register */
#define CCU60_MCMOUTS /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MCMOUTS*)0xF0002A8Cu)
/** \brief 90, Multi-Channel Mode Output Register */
#define CCU60_MCMOUT /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MCMOUT*)0xF0002A90u)
/** \brief 94, Multi-Channel Mode Control Register */
#define CCU60_MCMCTR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MCMCTR*)0xF0002A94u)
/** \brief 98, Input Monitoring Register */
#define CCU60_IMON /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_IMON*)0xF0002A98u)
/** \brief 9C, Lost Indicator Register */
#define CCU60_LI /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_LI*)0xF0002A9Cu)
/** \brief A0, Interrupt Status Register */
#define CCU60_IS /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_IS*)0xF0002AA0u)
/** \brief A4, Interrupt Status Set Register */
#define CCU60_ISS /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_ISS*)0xF0002AA4u)
/** \brief A8, Interrupt Status Reset Register */
#define CCU60_ISR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_ISR*)0xF0002AA8u)
/** \brief AC, Interrupt Node Pointer Register */
#define CCU60_INP /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_INP*)0xF0002AACu)
/** \brief B0, Interrupt Enable Register */
#define CCU60_IEN /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_IEN*)0xF0002AB0u)
/** \brief E8, OCDS Control and Status Register */
#define CCU60_OCS /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_OCS*)0xF0002AE8u)
/** \brief EC, Kernel Reset Status Clear Register */
#define CCU60_KRSTCLR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_KRSTCLR*)0xF0002AECu)
/** \brief F0, Kernel Reset Register 1 */
#define CCU60_KRST1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_KRST1*)0xF0002AF0u)
/** \brief F4, Kernel Reset Register 0 */
#define CCU60_KRST0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_KRST0*)0xF0002AF4u)
/** \brief FC, Access Enable Register 0 */
#define CCU60_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_ACCEN0*)0xF0002AFCu)
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Ccu6_Registers_Cfg_Ccu61
* \{ */
/** \brief 0, Clock Control Register */
#define CCU61_CLC /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CLC*)0xF0002B00u)
/** \brief 4, Module Configuration Register */
#define CCU61_MCFG /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MCFG*)0xF0002B04u)
/** \brief 8, Module Identification Register */
#define CCU61_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_ID*)0xF0002B08u)
/** \brief 10, Port Input Select Register 0 */
#define CCU61_PISEL0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_PISEL0*)0xF0002B10u)
/** \brief 14, Port Input Select Register 2 */
#define CCU61_PISEL2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_PISEL2*)0xF0002B14u)
/** \brief 1C, Kernel State Control Sensitivity Register */
#define CCU61_KSCSR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_KSCSR*)0xF0002B1Cu)
/** \brief 20, Timer T12 Counter Register */
#define CCU61_T12 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T12*)0xF0002B20u)
/** \brief 24, Timer 12 Period Register */
#define CCU61_T12PR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T12PR*)0xF0002B24u)
/** \brief 28, Dead-Time Control Register for Timer12 */
#define CCU61_T12DTC /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T12DTC*)0xF0002B28u)
/** \brief 30, Capture/Compare Register for Channel CC60 */
#define CCU61_CC6R0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6R*)0xF0002B30u)
/** Alias (User Manual Name) for CCU61_CC6R0.
* To use register names with standard convension, please use CCU61_CC6R0.
*/
#define CCU61_CC60R (CCU61_CC6R0)
/** \brief 34, Capture/Compare Register for Channel CC61 */
#define CCU61_CC6R1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6R*)0xF0002B34u)
/** Alias (User Manual Name) for CCU61_CC6R1.
* To use register names with standard convension, please use CCU61_CC6R1.
*/
#define CCU61_CC61R (CCU61_CC6R1)
/** \brief 38, Capture/Compare Register for Channel CC62 */
#define CCU61_CC6R2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6R*)0xF0002B38u)
/** Alias (User Manual Name) for CCU61_CC6R2.
* To use register names with standard convension, please use CCU61_CC6R2.
*/
#define CCU61_CC62R (CCU61_CC6R2)
/** \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
#define CCU61_CC6SR0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6SR*)0xF0002B40u)
/** Alias (User Manual Name) for CCU61_CC6SR0.
* To use register names with standard convension, please use CCU61_CC6SR0.
*/
#define CCU61_CC60SR (CCU61_CC6SR0)
/** \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
#define CCU61_CC6SR1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6SR*)0xF0002B44u)
/** Alias (User Manual Name) for CCU61_CC6SR1.
* To use register names with standard convension, please use CCU61_CC6SR1.
*/
#define CCU61_CC61SR (CCU61_CC6SR1)
/** \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
#define CCU61_CC6SR2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC6SR*)0xF0002B48u)
/** Alias (User Manual Name) for CCU61_CC6SR2.
* To use register names with standard convension, please use CCU61_CC6SR2.
*/
#define CCU61_CC62SR (CCU61_CC6SR2)
/** \brief 50, Timer T13 Counter Register */
#define CCU61_T13 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T13*)0xF0002B50u)
/** \brief 54, Timer 13 Period Register */
#define CCU61_T13PR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T13PR*)0xF0002B54u)
/** \brief 58, Compare Register for T13 */
#define CCU61_CC63R /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC63R*)0xF0002B58u)
/** \brief 5C, Compare Shadow Register for T13 */
#define CCU61_CC63SR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CC63SR*)0xF0002B5Cu)
/** \brief 60, Compare State Register */
#define CCU61_CMPSTAT /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CMPSTAT*)0xF0002B60u)
/** \brief 64, Compare State Modification Register */
#define CCU61_CMPMODIF /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_CMPMODIF*)0xF0002B64u)
/** \brief 68, T12 Mode Select Register */
#define CCU61_T12MSEL /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_T12MSEL*)0xF0002B68u)
/** \brief 70, Timer Control Register 0 */
#define CCU61_TCTR0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_TCTR0*)0xF0002B70u)
/** \brief 74, Timer Control Register 2 */
#define CCU61_TCTR2 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_TCTR2*)0xF0002B74u)
/** \brief 78, Timer Control Register 4 */
#define CCU61_TCTR4 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_TCTR4*)0xF0002B78u)
/** \brief 80, Modulation Control Register */
#define CCU61_MODCTR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MODCTR*)0xF0002B80u)
/** \brief 84, Trap Control Register */
#define CCU61_TRPCTR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_TRPCTR*)0xF0002B84u)
/** \brief 88, Passive State Level Register */
#define CCU61_PSLR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_PSLR*)0xF0002B88u)
/** \brief 8C, Multi-Channel Mode Output Shadow Register */
#define CCU61_MCMOUTS /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MCMOUTS*)0xF0002B8Cu)
/** \brief 90, Multi-Channel Mode Output Register */
#define CCU61_MCMOUT /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MCMOUT*)0xF0002B90u)
/** \brief 94, Multi-Channel Mode Control Register */
#define CCU61_MCMCTR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_MCMCTR*)0xF0002B94u)
/** \brief 98, Input Monitoring Register */
#define CCU61_IMON /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_IMON*)0xF0002B98u)
/** \brief 9C, Lost Indicator Register */
#define CCU61_LI /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_LI*)0xF0002B9Cu)
/** \brief A0, Interrupt Status Register */
#define CCU61_IS /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_IS*)0xF0002BA0u)
/** \brief A4, Interrupt Status Set Register */
#define CCU61_ISS /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_ISS*)0xF0002BA4u)
/** \brief A8, Interrupt Status Reset Register */
#define CCU61_ISR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_ISR*)0xF0002BA8u)
/** \brief AC, Interrupt Node Pointer Register */
#define CCU61_INP /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_INP*)0xF0002BACu)
/** \brief B0, Interrupt Enable Register */
#define CCU61_IEN /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_IEN*)0xF0002BB0u)
/** \brief E8, OCDS Control and Status Register */
#define CCU61_OCS /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_OCS*)0xF0002BE8u)
/** \brief EC, Kernel Reset Status Clear Register */
#define CCU61_KRSTCLR /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_KRSTCLR*)0xF0002BECu)
/** \brief F0, Kernel Reset Register 1 */
#define CCU61_KRST1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_KRST1*)0xF0002BF0u)
/** \brief F4, Kernel Reset Register 0 */
#define CCU61_KRST0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_KRST0*)0xF0002BF4u)
/** \brief FC, Access Enable Register 0 */
#define CCU61_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CCU6_ACCEN0*)0xF0002BFCu)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXCCU6_REG_H */

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/**
* \file IfxCcu6_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Ccu6_Registers Ccu6 Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Ccu6_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Ccu6_Registers
*
* \defgroup IfxSfr_Ccu6_Registers_union Register unions
* \ingroup IfxSfr_Ccu6_Registers
*
* \defgroup IfxSfr_Ccu6_Registers_struct Memory map
* \ingroup IfxSfr_Ccu6_Registers
*/
#ifndef IFXCCU6_REGDEF_H
#define IFXCCU6_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Ccu6_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_CCU6_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_CCU6_ACCEN0_Bits;
/** \brief Compare Register for T13 */
typedef struct _Ifx_CCU6_CC63R_Bits
{
Ifx_UReg_32Bit CCV:16; /**< \brief [15:0] Channel CC63 Compare Value - CCV (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_CC63R_Bits;
/** \brief Compare Shadow Register for T13 */
typedef struct _Ifx_CCU6_CC63SR_Bits
{
Ifx_UReg_32Bit CCS:16; /**< \brief [15:0] Shadow Register for Channel CC63 Compare Value - CCS (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_CC63SR_Bits;
/** \brief Capture/Compare Register for Channel CC6${x} */
typedef struct _Ifx_CCU6_CC6R_Bits
{
Ifx_UReg_32Bit CCV:16; /**< \brief [15:0] Capture/Compare Value - CCV (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_CC6R_Bits;
/** \brief Capture/Compare Shadow Reg. for Channel CC6${x} */
typedef struct _Ifx_CCU6_CC6SR_Bits
{
Ifx_UReg_32Bit CCS:16; /**< \brief [15:0] Shadow Register for Channel x Capture/Compare Value - CCS (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_CC6SR_Bits;
/** \brief Clock Control Register */
typedef struct _Ifx_CCU6_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (rh) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control - EDIS (rw) */
Ifx_UReg_32Bit reserved_4:12; /**< \brief [15:4] \internal Reserved */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_CLC_Bits;
/** \brief Compare State Modification Register */
typedef struct _Ifx_CCU6_CMPMODIF_Bits
{
Ifx_UReg_32Bit MCC60S:1; /**< \brief [0:0] Capture/Compare Status Modification Bits MCC60S (x = 0, 1, 2) - MCC60S (w) */
Ifx_UReg_32Bit MCC61S:1; /**< \brief [1:1] Capture/Compare Status Modification Bits MCC61S (x = 0, 1, 2) - MCC61S (w) */
Ifx_UReg_32Bit MCC62S:1; /**< \brief [2:2] Capture/Compare Status Modification Bits MCC62S (x = 0, 1, 2) - MCC62S (w) */
Ifx_UReg_32Bit reserved_3:3; /**< \brief [5:3] \internal Reserved */
Ifx_UReg_32Bit MCC63S:1; /**< \brief [6:6] Capture/Compare Status Modification Bit MCC63S - MCC63S (w) */
Ifx_UReg_32Bit reserved_7:1; /**< \brief [7:7] \internal Reserved */
Ifx_UReg_32Bit MCC60R:1; /**< \brief [8:8] Capture/Compare Status Modification Bits MCC60R (x = 0, 1, 2) - MCC60R (w) */
Ifx_UReg_32Bit MCC61R:1; /**< \brief [9:9] Capture/Compare Status Modification Bits MCC61R (x = 0, 1, 2) - MCC61R (w) */
Ifx_UReg_32Bit MCC62R:1; /**< \brief [10:10] Capture/Compare Status Modification Bits MCC62R (x = 0, 1, 2) - MCC62R (w) */
Ifx_UReg_32Bit reserved_11:3; /**< \brief [13:11] \internal Reserved */
Ifx_UReg_32Bit MCC63R:1; /**< \brief [14:14] Capture/Compare Status Modification Bits MCC63R - MCC63R (w) */
Ifx_UReg_32Bit reserved_15:17; /**< \brief [31:15] \internal Reserved */
} Ifx_CCU6_CMPMODIF_Bits;
/** \brief Compare State Register */
typedef struct _Ifx_CCU6_CMPSTAT_Bits
{
Ifx_UReg_32Bit CC60ST:1; /**< \brief [0:0] Capture/Compare State Bits for CC60 (x = 0, 1, 2) - CC60ST (rh) */
Ifx_UReg_32Bit CC61ST:1; /**< \brief [1:1] Capture/Compare State Bits for CC61 (x = 0, 1, 2) - CC61ST (rh) */
Ifx_UReg_32Bit CC62ST:1; /**< \brief [2:2] Capture/Compare State Bits for CC62 (x = 0, 1, 2) - CC62ST (rh) */
Ifx_UReg_32Bit CCPOS60:1; /**< \brief [3:3] Sampled Hall Pattern Bits - CCPOS60 (rh) */
Ifx_UReg_32Bit CCPOS61:1; /**< \brief [4:4] Sampled Hall Pattern Bits - CCPOS61 (rh) */
Ifx_UReg_32Bit CCPOS62:1; /**< \brief [5:5] Sampled Hall Pattern Bits - CCPOS62 (rh) */
Ifx_UReg_32Bit CC63ST:1; /**< \brief [6:6] Capture/Compare State Bit for CC63 - CC63ST (rh) */
Ifx_UReg_32Bit reserved_7:1; /**< \brief [7:7] \internal Reserved */
Ifx_UReg_32Bit CC60PS:1; /**< \brief [8:8] Passive State Select for Compare Outputs CC60 (x = 0, 1, 2) - CC60PS (rwh) */
Ifx_UReg_32Bit COUT60PS:1; /**< \brief [9:9] Passive State Select for Compare Outputs COUT60 (x = 0, 1, 2) - COUT60PS (rwh) */
Ifx_UReg_32Bit CC61PS:1; /**< \brief [10:10] Passive State Select for Compare Outputs CC61 (x = 0, 1, 2) - CC61PS (rwh) */
Ifx_UReg_32Bit COUT61PS:1; /**< \brief [11:11] Passive State Select for Compare Outputs COUT61 (x = 0, 1, 2) - COUT61PS (rwh) */
Ifx_UReg_32Bit CC62PS:1; /**< \brief [12:12] Passive State Select for Compare Outputs CC62 (x = 0, 1, 2) - CC62PS (rwh) */
Ifx_UReg_32Bit COUT62PS:1; /**< \brief [13:13] Passive State Select for Compare Outputs COUT62 (x = 0, 1, 2) - COUT62PS (rwh) */
Ifx_UReg_32Bit COUT63PS:1; /**< \brief [14:14] Passive State Select for Compare Output COUT63 - COUT63PS (rwh) */
Ifx_UReg_32Bit T13IM:1; /**< \brief [15:15] T13 Inverted Modulation - T13IM (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_CMPSTAT_Bits;
/** \brief Module Identification Register */
typedef struct _Ifx_CCU6_ID_Bits
{
Ifx_UReg_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number - MODREV (r) */
Ifx_UReg_32Bit MODNUM:8; /**< \brief [15:8] Module Number Value - MODNUM (r) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_ID_Bits;
/** \brief Interrupt Enable Register */
typedef struct _Ifx_CCU6_IEN_Bits
{
Ifx_UReg_32Bit ENCC60R:1; /**< \brief [0:0] Capture, Compare-Match Rising Edge Interrupt Enable for Channel CC6x ENCC6xF (x=0,1,2) (rw) */
Ifx_UReg_32Bit ENCC60F:1; /**< \brief [1:1] Capture, Compare-Match Falling Edge Interrupt Enable for Channel CC6x ENCC6xF (x=0,1,2) (rw) */
Ifx_UReg_32Bit ENCC61R:1; /**< \brief [2:2] Capture, Compare-Match Rising Edge Interrupt Enable for Channel CC6x ENCC6xF (x=0,1,2) (rw) */
Ifx_UReg_32Bit ENCC61F:1; /**< \brief [3:3] Capture, Compare-Match Falling Edge Interrupt Enable for Channel CC6x ENCC6xF (x=0,1,2) (rw) */
Ifx_UReg_32Bit ENCC62R:1; /**< \brief [4:4] Capture, Compare-Match Rising Edge Interrupt Enable for Channel CC6x ENCC6xF (x=0,1,2) (rw) */
Ifx_UReg_32Bit ENCC62F:1; /**< \brief [5:5] Capture, Compare-Match Falling Edge Interrupt Enable for Channel CC6x ENCC6xF (x=0,1,2) (rw) */
Ifx_UReg_32Bit ENT12OM:1; /**< \brief [6:6] Enable Interrupt for T12 One-Match - ENT12OM (rw) */
Ifx_UReg_32Bit ENT12PM:1; /**< \brief [7:7] Enable Interrupt for T12 Period-Match - ENT12PM (rw) */
Ifx_UReg_32Bit ENT13CM:1; /**< \brief [8:8] Enable Interrupt for T13 Compare-Match - ENT13CM (rw) */
Ifx_UReg_32Bit ENT13PM:1; /**< \brief [9:9] Enable Interrupt for T13 Period-Match - ENT13PM (rw) */
Ifx_UReg_32Bit ENTRPF:1; /**< \brief [10:10] Enable Interrupt for Trap Flag - ENTRPF (rw) */
Ifx_UReg_32Bit reserved_11:1; /**< \brief [11:11] \internal Reserved */
Ifx_UReg_32Bit ENCHE:1; /**< \brief [12:12] Enable Interrupt for Correct Hall Event - ENCHE (rw) */
Ifx_UReg_32Bit ENWHE:1; /**< \brief [13:13] Enable Interrupt for Wrong Hall Event - ENWHE (rw) */
Ifx_UReg_32Bit ENIDLE:1; /**< \brief [14:14] Enable Idle - ENIDLE (rw) */
Ifx_UReg_32Bit ENSTR:1; /**< \brief [15:15] Enable Multi-Channel Mode Shadow Transfer Interrupt - ENSTR (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_IEN_Bits;
/** \brief Input Monitoring Register */
typedef struct _Ifx_CCU6_IMON_Bits
{
Ifx_UReg_32Bit LBE:1; /**< \brief [0:0] Lost Bit Event - LBE (rwh) */
Ifx_UReg_32Bit CCPOS0I:1; /**< \brief [1:1] Event indication for input signal CCPOS0 - CCPOS0I (rwh) */
Ifx_UReg_32Bit CCPOS1I:1; /**< \brief [2:2] Event indication for input signal CCPOS1 - CCPOS1I (rwh) */
Ifx_UReg_32Bit CCPOS2I:1; /**< \brief [3:3] Event indication for input signal CCPOS2 - CCPOS2I (rwh) */
Ifx_UReg_32Bit CC60INI:1; /**< \brief [4:4] Event indication for input signal CC60IN - CC60INI (rwh) */
Ifx_UReg_32Bit CC61INI:1; /**< \brief [5:5] Event indication for input signal CC61IN - CC61INI (rwh) */
Ifx_UReg_32Bit CC62INI:1; /**< \brief [6:6] Event indication for input signal CC62IN - CC62INI (rwh) */
Ifx_UReg_32Bit CTRAPI:1; /**< \brief [7:7] Event indication for input signal CTRAP - CTRAPI (rwh) */
Ifx_UReg_32Bit T12HRI:1; /**< \brief [8:8] Event indication for input signal T12HR - T12HRI (rwh) */
Ifx_UReg_32Bit T13HRI:1; /**< \brief [9:9] Event indication for input signal T13HR - T13HRI (rwh) */
Ifx_UReg_32Bit reserved_10:22; /**< \brief [31:10] \internal Reserved */
} Ifx_CCU6_IMON_Bits;
/** \brief Interrupt Node Pointer Register */
typedef struct _Ifx_CCU6_INP_Bits
{
Ifx_UReg_32Bit INPCC60:2; /**< \brief [1:0] Interrupt Node Pointer for Channel CC6x Interrupts INPCC6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit INPCC61:2; /**< \brief [3:2] Interrupt Node Pointer for Channel CC6x Interrupts INPCC6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit INPCC62:2; /**< \brief [5:4] Interrupt Node Pointer for Channel CC6x Interrupts INPCC6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit INPCHE:2; /**< \brief [7:6] Interrupt Node Pointer for the CHE Interrupt - INPCHE (rw) */
Ifx_UReg_32Bit INPERR:2; /**< \brief [9:8] Interrupt Node Pointer for Error Interrupts - INPERR (rw) */
Ifx_UReg_32Bit INPT12:2; /**< \brief [11:10] Interrupt Node Pointer for Timer12 Interrupts - INPT12 (rw) */
Ifx_UReg_32Bit INPT13:2; /**< \brief [13:12] Interrupt Node Pointer for Timer13 Interrupt - INPT13 (rw) */
Ifx_UReg_32Bit reserved_14:18; /**< \brief [31:14] \internal Reserved */
} Ifx_CCU6_INP_Bits;
/** \brief Interrupt Status Register */
typedef struct _Ifx_CCU6_IS_Bits
{
Ifx_UReg_32Bit ICC60R:1; /**< \brief [0:0] Capture, Compare-Match Rising Edge Flag ICC6xR (x=0,1,2) (rh) */
Ifx_UReg_32Bit ICC60F:1; /**< \brief [1:1] Capture, Compare-Match Falling Edge Flag ICC6xF (x=0,1,2) (rh) */
Ifx_UReg_32Bit ICC61R:1; /**< \brief [2:2] Capture, Compare-Match Rising Edge Flag ICC6xR (x=0,1,2) (rh) */
Ifx_UReg_32Bit ICC61F:1; /**< \brief [3:3] Capture, Compare-Match Falling Edge Flag ICC6xF (x=0,1,2) (rh) */
Ifx_UReg_32Bit ICC62R:1; /**< \brief [4:4] Capture, Compare-Match Rising Edge Flag ICC6xR (x=0,1,2) (rh) */
Ifx_UReg_32Bit ICC62F:1; /**< \brief [5:5] Capture, Compare-Match Falling Edge Flag ICC6xF (x=0,1,2) (rh) */
Ifx_UReg_32Bit T12OM:1; /**< \brief [6:6] Timer T12 One-Match Flag - T12OM (rh) */
Ifx_UReg_32Bit T12PM:1; /**< \brief [7:7] Timer T12 Period-Match Flag - T12PM (rh) */
Ifx_UReg_32Bit T13CM:1; /**< \brief [8:8] Timer T13 Compare-Match Flag - T13CM (rh) */
Ifx_UReg_32Bit T13PM:1; /**< \brief [9:9] Timer T13 Period-Match Flag - T13PM (rh) */
Ifx_UReg_32Bit TRPF:1; /**< \brief [10:10] Trap Flag - TRPF (rh) */
Ifx_UReg_32Bit TRPS:1; /**< \brief [11:11] Trap State - TRPS (rh) */
Ifx_UReg_32Bit CHE:1; /**< \brief [12:12] Correct Hall Event - CHE (rh) */
Ifx_UReg_32Bit WHE:1; /**< \brief [13:13] Wrong Hall Event - WHE (rh) */
Ifx_UReg_32Bit IDLE:1; /**< \brief [14:14] IDLE State - IDLE (rh) */
Ifx_UReg_32Bit STR:1; /**< \brief [15:15] Multi-Channel Mode Shadow Transfer Request - STR (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_IS_Bits;
/** \brief Interrupt Status Reset Register */
typedef struct _Ifx_CCU6_ISR_Bits
{
Ifx_UReg_32Bit RCC60R:1; /**< \brief [0:0] Reset Capture, Compare-Match Rising Edge Flag - RCC6xR (x=0,1,2) (w) */
Ifx_UReg_32Bit RCC60F:1; /**< \brief [1:1] Reset Capture, Compare-Match Falling Edge Flag - RCC6xF (x=0,1,2) (w) */
Ifx_UReg_32Bit RCC61R:1; /**< \brief [2:2] Reset Capture, Compare-Match Rising Edge Flag - RCC6xR (x=0,1,2) (w) */
Ifx_UReg_32Bit RCC61F:1; /**< \brief [3:3] Reset Capture, Compare-Match Falling Edge Flag - RCC6xF (x=0,1,2) (w) */
Ifx_UReg_32Bit RCC62R:1; /**< \brief [4:4] Reset Capture, Compare-Match Rising Edge Flag - RCC6xR (x=0,1,2) (w) */
Ifx_UReg_32Bit RCC62F:1; /**< \brief [5:5] Reset Capture, Compare-Match Falling Edge Flag - RCC6xF (x=0,1,2) (w) */
Ifx_UReg_32Bit RT12OM:1; /**< \brief [6:6] Reset Timer T12 One-Match Flag - RT12OM (w) */
Ifx_UReg_32Bit RT12PM:1; /**< \brief [7:7] Reset Timer T12 Period-Match Flag - RT12PM (w) */
Ifx_UReg_32Bit RT13CM:1; /**< \brief [8:8] Reset Timer T13 Compare-Match Flag - RT13CM (w) */
Ifx_UReg_32Bit RT13PM:1; /**< \brief [9:9] Reset Timer T13 Period-Match Flag - RT13PM (w) */
Ifx_UReg_32Bit RTRPF:1; /**< \brief [10:10] Reset Trap Flag - RTRPF (w) */
Ifx_UReg_32Bit reserved_11:1; /**< \brief [11:11] \internal Reserved */
Ifx_UReg_32Bit RCHE:1; /**< \brief [12:12] Reset Correct Hall Event Flag - RCHE (w) */
Ifx_UReg_32Bit RWHE:1; /**< \brief [13:13] Reset Wrong Hall Event Flag - RWHE (w) */
Ifx_UReg_32Bit RIDLE:1; /**< \brief [14:14] Reset IDLE Flag - RIDLE (w) */
Ifx_UReg_32Bit RSTR:1; /**< \brief [15:15] Reset STR Flag - RSTR (w) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_ISR_Bits;
/** \brief Interrupt Status Set Register */
typedef struct _Ifx_CCU6_ISS_Bits
{
Ifx_UReg_32Bit SCC60R:1; /**< \brief [0:0] Set Capture, Compare-Match Rising Edge Flag - SCC6xR (x=0,1,2) (w) */
Ifx_UReg_32Bit SCC60F:1; /**< \brief [1:1] Set Capture, Compare-Match Falling Edge Flag - SCC6xF (x=0,1,2) (w) */
Ifx_UReg_32Bit SCC61R:1; /**< \brief [2:2] Set Capture, Compare-Match Rising Edge Flag - SCC6xR (x=0,1,2) (w) */
Ifx_UReg_32Bit SCC61F:1; /**< \brief [3:3] Set Capture, Compare-Match Falling Edge Flag - SCC6xF (x=0,1,2) (w) */
Ifx_UReg_32Bit SCC62R:1; /**< \brief [4:4] Set Capture, Compare-Match Rising Edge Flag - SCC6xR (x=0,1,2) (w) */
Ifx_UReg_32Bit SCC62F:1; /**< \brief [5:5] Set Capture, Compare-Match Falling Edge Flag - SCC6xF (x=0,1,2) (w) */
Ifx_UReg_32Bit ST12OM:1; /**< \brief [6:6] Set Timer T12 One-Match Flag - ST12OM (w) */
Ifx_UReg_32Bit ST12PM:1; /**< \brief [7:7] Set Timer T12 Period-Match Flag - ST12PM (w) */
Ifx_UReg_32Bit ST13CM:1; /**< \brief [8:8] Set Timer T13 Compare-Match Flag - ST13CM (w) */
Ifx_UReg_32Bit ST13PM:1; /**< \brief [9:9] Set Timer T13 Period-Match Flag - ST13PM (w) */
Ifx_UReg_32Bit STRPF:1; /**< \brief [10:10] Set Trap Flag - STRPF (w) */
Ifx_UReg_32Bit SWHC:1; /**< \brief [11:11] Software Hall Compare - SWHC (w) */
Ifx_UReg_32Bit SCHE:1; /**< \brief [12:12] Set Correct Hall Event Flag - SCHE (w) */
Ifx_UReg_32Bit SWHE:1; /**< \brief [13:13] Set Wrong Hall Event Flag - SWHE (w) */
Ifx_UReg_32Bit SIDLE:1; /**< \brief [14:14] Set IDLE Flag - SIDLE (w) */
Ifx_UReg_32Bit SSTR:1; /**< \brief [15:15] Set STR Flag - SSTR (w) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_ISS_Bits;
/** \brief Kernel Reset Register 0 */
typedef struct _Ifx_CCU6_KRST0_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status - RSTSTAT (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_CCU6_KRST0_Bits;
/** \brief Kernel Reset Register 1 */
typedef struct _Ifx_CCU6_KRST1_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_CCU6_KRST1_Bits;
/** \brief Kernel Reset Status Clear Register */
typedef struct _Ifx_CCU6_KRSTCLR_Bits
{
Ifx_UReg_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear - CLR (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_CCU6_KRSTCLR_Bits;
/** \brief Kernel State Control Sensitivity Register */
typedef struct _Ifx_CCU6_KSCSR_Bits
{
Ifx_UReg_32Bit SB0:1; /**< \brief [0:0] Sensitivity Block x SBx (x=0,1,2,3) (rw) */
Ifx_UReg_32Bit SB1:1; /**< \brief [1:1] Sensitivity Block x SBx (x=0,1,2,3) (rw) */
Ifx_UReg_32Bit SB2:1; /**< \brief [2:2] Sensitivity Block x SBx (x=0,1,2,3) (rw) */
Ifx_UReg_32Bit SB3:1; /**< \brief [3:3] Sensitivity Block x SBx (x=0,1,2,3) (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_CCU6_KSCSR_Bits;
/** \brief Lost Indicator Register */
typedef struct _Ifx_CCU6_LI_Bits
{
Ifx_UReg_32Bit reserved_0:1; /**< \brief [0:0] \internal Reserved */
Ifx_UReg_32Bit CCPOS0EN:1; /**< \brief [1:1] Lost Indicator Enable for input signal CCPOS0 - CCPOS0EN (rw) */
Ifx_UReg_32Bit CCPOS1EN:1; /**< \brief [2:2] Lost Indicator Enable for input signal CCPOS1 - CCPOS1EN (rw) */
Ifx_UReg_32Bit CCPOS2EN:1; /**< \brief [3:3] Lost Indicator Enable for input signal CCPOS2 - CCPOS2EN (rw) */
Ifx_UReg_32Bit CC60INEN:1; /**< \brief [4:4] Lost Indicator Enable for input signal CC60IN - CC60INEN (rw) */
Ifx_UReg_32Bit CC61INEN:1; /**< \brief [5:5] Lost Indicator Enable for input signal CC61IN - CC61INEN (rw) */
Ifx_UReg_32Bit CC62INEN:1; /**< \brief [6:6] Lost Indicator Enable for input signal CC62IN - CC62INEN (rw) */
Ifx_UReg_32Bit CTRAPEN:1; /**< \brief [7:7] Lost Indicator Enable for input signal CTRAP - CTRAPEN (rw) */
Ifx_UReg_32Bit T12HREN:1; /**< \brief [8:8] Lost Indicator Enable for input signal T12HR - T12HREN (rw) */
Ifx_UReg_32Bit T13HREN:1; /**< \brief [9:9] Lost Indicator Enable for input signal T13HR - T13HREN (rw) */
Ifx_UReg_32Bit reserved_10:3; /**< \brief [12:10] \internal Reserved */
Ifx_UReg_32Bit LBEEN:1; /**< \brief [13:13] Interrupt Enable for Lost Bit Event - LBEEN (rw) */
Ifx_UReg_32Bit INPLBE:2; /**< \brief [15:14] Interrupt Node Pointer for lost bit event - INPLBE (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_LI_Bits;
/** \brief Module Configuration Register */
typedef struct _Ifx_CCU6_MCFG_Bits
{
Ifx_UReg_32Bit T12:1; /**< \brief [0:0] T12 Available - T12 (r) */
Ifx_UReg_32Bit T13:1; /**< \brief [1:1] T13 Available - T13 (r) */
Ifx_UReg_32Bit MCM:1; /**< \brief [2:2] Multi-Channel Mode Available - MCM (r) */
Ifx_UReg_32Bit reserved_3:12; /**< \brief [14:3] \internal Reserved */
Ifx_UReg_32Bit reserved_15:1; /**< \brief [15:15] \internal Reserved */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_MCFG_Bits;
/** \brief Multi-Channel Mode Control Register */
typedef struct _Ifx_CCU6_MCMCTR_Bits
{
Ifx_UReg_32Bit SWSEL:3; /**< \brief [2:0] Switching Selection - SWSEL (rw) */
Ifx_UReg_32Bit reserved_3:1; /**< \brief [3:3] \internal Reserved */
Ifx_UReg_32Bit SWSYN:2; /**< \brief [5:4] Switching Synchronization - SWSYN (rw) */
Ifx_UReg_32Bit reserved_6:2; /**< \brief [7:6] \internal Reserved */
Ifx_UReg_32Bit STE12U:1; /**< \brief [8:8] Shadow Transfer Enable for T12 Upcounting - STE12U (rw) */
Ifx_UReg_32Bit STE12D:1; /**< \brief [9:9] Shadow Transfer Enable for T12 Downcounting - STE12D (rw) */
Ifx_UReg_32Bit STE13U:1; /**< \brief [10:10] Shadow Transfer Enable for T13 Upcounting - STE13U (rw) */
Ifx_UReg_32Bit reserved_11:21; /**< \brief [31:11] \internal Reserved */
} Ifx_CCU6_MCMCTR_Bits;
/** \brief Multi-Channel Mode Output Register */
typedef struct _Ifx_CCU6_MCMOUT_Bits
{
Ifx_UReg_32Bit MCMP:6; /**< \brief [5:0] Multi-Channel PWM Pattern - MCMP (rh) */
Ifx_UReg_32Bit R:1; /**< \brief [6:6] Reminder Flag - R (rh) */
Ifx_UReg_32Bit reserved_7:1; /**< \brief [7:7] \internal Reserved */
Ifx_UReg_32Bit EXPH:3; /**< \brief [10:8] Expected Hall Pattern - EXPH (rh) */
Ifx_UReg_32Bit CURH:3; /**< \brief [13:11] Current Hall Pattern - CURH (rh) */
Ifx_UReg_32Bit reserved_14:18; /**< \brief [31:14] \internal Reserved */
} Ifx_CCU6_MCMOUT_Bits;
/** \brief Multi-Channel Mode Output Shadow Register */
typedef struct _Ifx_CCU6_MCMOUTS_Bits
{
Ifx_UReg_32Bit MCMPS:6; /**< \brief [5:0] Multi-Channel PWM Pattern Shadow - MCMPS (rw) */
Ifx_UReg_32Bit reserved_6:1; /**< \brief [6:6] \internal Reserved */
Ifx_UReg_32Bit STRMCM:1; /**< \brief [7:7] Shadow Transfer Request for MCMPS - STRMCM (w) */
Ifx_UReg_32Bit EXPHS:3; /**< \brief [10:8] Expected Hall Pattern Shadow - EXPHS (rw) */
Ifx_UReg_32Bit CURHS:3; /**< \brief [13:11] Current Hall Pattern Shadow - CURHS (rw) */
Ifx_UReg_32Bit reserved_14:1; /**< \brief [14:14] \internal Reserved */
Ifx_UReg_32Bit STRHP:1; /**< \brief [15:15] Shadow Transfer Request for the Hall Pattern - STRHP (w) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_MCMOUTS_Bits;
/** \brief Modulation Control Register */
typedef struct _Ifx_CCU6_MODCTR_Bits
{
Ifx_UReg_32Bit T12MODEN:6; /**< \brief [5:0] T12 Modulation Enable - T12MODEN (rw) */
Ifx_UReg_32Bit reserved_6:1; /**< \brief [6:6] \internal Reserved */
Ifx_UReg_32Bit MCMEN:1; /**< \brief [7:7] Multi-Channel Mode Enable - MCMEN (rw) */
Ifx_UReg_32Bit T13MODEN:6; /**< \brief [13:8] T13 Modulation Enable - T13MODEN (rw) */
Ifx_UReg_32Bit reserved_14:1; /**< \brief [14:14] \internal Reserved */
Ifx_UReg_32Bit ECT13O:1; /**< \brief [15:15] Enable Compare Timer T13 Output - ECT13O (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_MODCTR_Bits;
/** \brief CCU60 Module Output Select Register */
typedef struct _Ifx_CCU6_MOSEL_Bits
{
Ifx_UReg_32Bit TRIG0SEL:3; /**< \brief [2:0] Output Trigger Select for CCU6061 TRIG0 (rw) */
Ifx_UReg_32Bit TRIG1SEL:3; /**< \brief [5:3] Output Trigger Select for CCU6061 TRIG1 (rw) */
Ifx_UReg_32Bit TRIG2SEL:3; /**< \brief [8:6] Output Trigger Select for CCU6061 TRIG2 (rw) */
Ifx_UReg_32Bit reserved_9:23; /**< \brief [31:9] \internal Reserved */
} Ifx_CCU6_MOSEL_Bits;
/** \brief OCDS Control and Status Register */
typedef struct _Ifx_CCU6_OCS_Bits
{
Ifx_UReg_32Bit TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 - TGS (rw) */
Ifx_UReg_32Bit TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select - TGB (rw) */
Ifx_UReg_32Bit TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection - TG_P (w) */
Ifx_UReg_32Bit reserved_4:20; /**< \brief [23:4] \internal Reserved */
Ifx_UReg_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control - SUS (rw) */
Ifx_UReg_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection - SUS_P (w) */
Ifx_UReg_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State - SUSSTA (rh) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_CCU6_OCS_Bits;
/** \brief Port Input Select Register 0 */
typedef struct _Ifx_CCU6_PISEL0_Bits
{
Ifx_UReg_32Bit ISCC60:2; /**< \brief [1:0] Input Select for CC60 ISCC6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit ISCC61:2; /**< \brief [3:2] Input Select for CC60 ISCC6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit ISCC62:2; /**< \brief [5:4] Input Select for CC60 ISCC6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit ISTRP:2; /**< \brief [7:6] Input Select for CTRAP - ISTRP (rw) */
Ifx_UReg_32Bit ISPOS0:2; /**< \brief [9:8] Input Select for CCPOS0 ISPOSx (x=0,1,2) (rw) */
Ifx_UReg_32Bit ISPOS1:2; /**< \brief [11:10] Input Select for CCPOS0 ISPOSx (x=0,1,2) (rw) */
Ifx_UReg_32Bit ISPOS2:2; /**< \brief [13:12] Input Select for CCPOS0 ISPOSx (x=0,1,2) (rw) */
Ifx_UReg_32Bit IST12HR:2; /**< \brief [15:14] Input Select for T12HR - IST12HR (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_PISEL0_Bits;
/** \brief Port Input Select Register 2 */
typedef struct _Ifx_CCU6_PISEL2_Bits
{
Ifx_UReg_32Bit IST13HR:2; /**< \brief [1:0] Input Select for T13HR - IST13HR (rw) */
Ifx_UReg_32Bit ISCNT12:2; /**< \brief [3:2] Input Select for T12 Counting Input - ISCNT12 (rw) */
Ifx_UReg_32Bit ISCNT13:2; /**< \brief [5:4] Input Select for T13 Counting Input - ISCNT13 (rw) */
Ifx_UReg_32Bit T12EXT:1; /**< \brief [6:6] Extension for T12HR Inputs - T12EXT (rw) */
Ifx_UReg_32Bit T13EXT:1; /**< \brief [7:7] Extension for T13HR Inputs - T13EXT (rw) */
Ifx_UReg_32Bit reserved_8:24; /**< \brief [31:8] \internal Reserved */
} Ifx_CCU6_PISEL2_Bits;
/** \brief Passive State Level Register */
typedef struct _Ifx_CCU6_PSLR_Bits
{
Ifx_UReg_32Bit PSL:6; /**< \brief [5:0] Compare Outputs Passive State Level - PSL (rwh) */
Ifx_UReg_32Bit reserved_6:1; /**< \brief [6:6] \internal Reserved */
Ifx_UReg_32Bit PSL63:1; /**< \brief [7:7] Passive State Level of Output COUT63 - PSL63 (rwh) */
Ifx_UReg_32Bit reserved_8:24; /**< \brief [31:8] \internal Reserved */
} Ifx_CCU6_PSLR_Bits;
/** \brief Timer T12 Counter Register */
typedef struct _Ifx_CCU6_T12_Bits
{
Ifx_UReg_32Bit T12CV:16; /**< \brief [15:0] Timer 12 Counter Value - T12CV (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_T12_Bits;
/** \brief Dead-Time Control Register for Timer12 */
typedef struct _Ifx_CCU6_T12DTC_Bits
{
Ifx_UReg_32Bit DTM:8; /**< \brief [7:0] Dead-Time - DTM (rw) */
Ifx_UReg_32Bit DTE0:1; /**< \brief [8:8] Dead Time Enable Bits DTEx (x=0,1,2) (rw) */
Ifx_UReg_32Bit DTE1:1; /**< \brief [9:9] Dead Time Enable Bits DTEx (x=0,1,2) (rw) */
Ifx_UReg_32Bit DTE2:1; /**< \brief [10:10] Dead Time Enable Bits DTEx (x=0,1,2) (rw) */
Ifx_UReg_32Bit reserved_11:1; /**< \brief [11:11] \internal Reserved */
Ifx_UReg_32Bit DTR0:1; /**< \brief [12:12] Dead Time Run Indication Bits DTRx (x=1,2,3) (rh) */
Ifx_UReg_32Bit DTR1:1; /**< \brief [13:13] Dead Time Run Indication Bits DTRx (x=1,2,3) (rh) */
Ifx_UReg_32Bit DTR2:1; /**< \brief [14:14] Dead Time Run Indication Bits DTRx (x=1,2,3) (rh) */
Ifx_UReg_32Bit reserved_15:17; /**< \brief [31:15] \internal Reserved */
} Ifx_CCU6_T12DTC_Bits;
/** \brief T12 Mode Select Register */
typedef struct _Ifx_CCU6_T12MSEL_Bits
{
Ifx_UReg_32Bit MSEL60:4; /**< \brief [3:0] Capture/Compare Mode Selection MSEL6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit MSEL61:4; /**< \brief [7:4] Capture/Compare Mode Selection MSEL6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit MSEL62:4; /**< \brief [11:8] Capture/Compare Mode Selection MSEL6x (x=0,1,2) (rw) */
Ifx_UReg_32Bit HSYNC:3; /**< \brief [14:12] Hall Synchronization - HSYNC (rw) */
Ifx_UReg_32Bit DBYP:1; /**< \brief [15:15] Delay Bypass - DBYP (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_T12MSEL_Bits;
/** \brief Timer 12 Period Register */
typedef struct _Ifx_CCU6_T12PR_Bits
{
Ifx_UReg_32Bit T12PV:16; /**< \brief [15:0] T12 Period Value - T12PV (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_T12PR_Bits;
/** \brief Timer T13 Counter Register */
typedef struct _Ifx_CCU6_T13_Bits
{
Ifx_UReg_32Bit T13CV:16; /**< \brief [15:0] Timer 13 Counter Value - T13CV (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_T13_Bits;
/** \brief Timer 13 Period Register */
typedef struct _Ifx_CCU6_T13PR_Bits
{
Ifx_UReg_32Bit T13PV:16; /**< \brief [15:0] T13 Period Value - T13PV (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_T13PR_Bits;
/** \brief Timer Control Register 0 */
typedef struct _Ifx_CCU6_TCTR0_Bits
{
Ifx_UReg_32Bit T12CLK:3; /**< \brief [2:0] Timer T12 Input Clock Select - T12CLK (rw) */
Ifx_UReg_32Bit T12PRE:1; /**< \brief [3:3] Timer T12 Prescaler Bit - T12PRE (rw) */
Ifx_UReg_32Bit T12R:1; /**< \brief [4:4] Timer T12 Run Bit - T12R (rh) */
Ifx_UReg_32Bit STE12:1; /**< \brief [5:5] Timer T12 Shadow Transfer Enable - STE12 (rh) */
Ifx_UReg_32Bit CDIR:1; /**< \brief [6:6] Count Direction of Timer T12 - CDIR (rh) */
Ifx_UReg_32Bit CTM:1; /**< \brief [7:7] T12 Operating Mode - CTM (rw) */
Ifx_UReg_32Bit T13CLK:3; /**< \brief [10:8] Timer T13 Input Clock Select - T13CLK (rw) */
Ifx_UReg_32Bit T13PRE:1; /**< \brief [11:11] Timer T13 Prescaler Bit - T13PRE (rw) */
Ifx_UReg_32Bit T13R:1; /**< \brief [12:12] Timer T13 Run Bit - T13R (rh) */
Ifx_UReg_32Bit STE13:1; /**< \brief [13:13] Timer T13 Shadow Transfer Enable - STE13 (rh) */
Ifx_UReg_32Bit reserved_14:18; /**< \brief [31:14] \internal Reserved */
} Ifx_CCU6_TCTR0_Bits;
/** \brief Timer Control Register 2 */
typedef struct _Ifx_CCU6_TCTR2_Bits
{
Ifx_UReg_32Bit T12SSC:1; /**< \brief [0:0] Timer T12 Single Shot Control - T12SSC (rw) */
Ifx_UReg_32Bit T13SSC:1; /**< \brief [1:1] Timer T13 Single Shot Control - T13SSC (rw) */
Ifx_UReg_32Bit T13TEC:3; /**< \brief [4:2] T13 Trigger Event Control - T13TEC (rw) */
Ifx_UReg_32Bit T13TED:2; /**< \brief [6:5] Timer T13 Trigger Event Direction - T13TED (rw) */
Ifx_UReg_32Bit reserved_7:1; /**< \brief [7:7] \internal Reserved */
Ifx_UReg_32Bit T12RSEL:2; /**< \brief [9:8] Timer T12 External Run Selection - T12RSEL (rw) */
Ifx_UReg_32Bit T13RSEL:2; /**< \brief [11:10] Timer T13 External Run Selection - T13RSEL (rw) */
Ifx_UReg_32Bit reserved_12:20; /**< \brief [31:12] \internal Reserved */
} Ifx_CCU6_TCTR2_Bits;
/** \brief Timer Control Register 4 */
typedef struct _Ifx_CCU6_TCTR4_Bits
{
Ifx_UReg_32Bit T12RR:1; /**< \brief [0:0] Timer T12 Run Reset - T12RR (w) */
Ifx_UReg_32Bit T12RS:1; /**< \brief [1:1] Timer T12 Run Set - T12RS (w) */
Ifx_UReg_32Bit T12RES:1; /**< \brief [2:2] Timer T12 Reset - T12RES (w) */
Ifx_UReg_32Bit DTRES:1; /**< \brief [3:3] Dead-Time Counter Reset - DTRES (w) */
Ifx_UReg_32Bit reserved_4:1; /**< \brief [4:4] \internal Reserved */
Ifx_UReg_32Bit T12CNT:1; /**< \brief [5:5] Timer T12 Count Event - T12CNT (w) */
Ifx_UReg_32Bit T12STR:1; /**< \brief [6:6] Timer T12 Shadow Transfer Request - T12STR (w) */
Ifx_UReg_32Bit T12STD:1; /**< \brief [7:7] Timer T12 Shadow Transfer Disable - T12STD (w) */
Ifx_UReg_32Bit T13RR:1; /**< \brief [8:8] Timer T13 Run Reset - T13RR (w) */
Ifx_UReg_32Bit T13RS:1; /**< \brief [9:9] Timer T13 Run Set - T13RS (w) */
Ifx_UReg_32Bit T13RES:1; /**< \brief [10:10] Timer T13 Reset - T13RES (w) */
Ifx_UReg_32Bit reserved_11:2; /**< \brief [12:11] \internal Reserved */
Ifx_UReg_32Bit T13CNT:1; /**< \brief [13:13] Timer T13 Count Event - T13CNT (w) */
Ifx_UReg_32Bit T13STR:1; /**< \brief [14:14] Timer T13 Shadow Transfer Request - T13STR (w) */
Ifx_UReg_32Bit T13STD:1; /**< \brief [15:15] Timer T13 Shadow Transfer Disable - T13STD (w) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_TCTR4_Bits;
/** \brief Trap Control Register */
typedef struct _Ifx_CCU6_TRPCTR_Bits
{
Ifx_UReg_32Bit TRPM0:1; /**< \brief [0:0] Trap Mode Control Bit 0 - TRPM0 (rw) */
Ifx_UReg_32Bit TRPM1:1; /**< \brief [1:1] Trap Mode Control Bit 1 - TRPM1 (rw) */
Ifx_UReg_32Bit TRPM2:1; /**< \brief [2:2] Trap Mode Control Bit 2 - TRPM2 (rw) */
Ifx_UReg_32Bit reserved_3:5; /**< \brief [7:3] \internal Reserved */
Ifx_UReg_32Bit TRPEN:6; /**< \brief [13:8] Trap Enable Control - TRPEN (rw) */
Ifx_UReg_32Bit TRPEN13:1; /**< \brief [14:14] Trap Enable Control for Timer T13 - TRPEN13 (rw) */
Ifx_UReg_32Bit TRPPEN:1; /**< \brief [15:15] Trap Pin Enable - TRPPEN (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CCU6_TRPCTR_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_ccu6_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_ACCEN0;
/** \brief Compare Register for T13 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_CC63R_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_CC63R;
/** \brief Compare Shadow Register for T13 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_CC63SR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_CC63SR;
/** \brief Capture/Compare Register for Channel CC6${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_CC6R_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_CC6R;
/** \brief Capture/Compare Shadow Reg. for Channel CC6${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_CC6SR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_CC6SR;
/** \brief Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_CLC;
/** \brief Compare State Modification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_CMPMODIF_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_CMPMODIF;
/** \brief Compare State Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_CMPSTAT_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_CMPSTAT;
/** \brief Module Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_ID_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_ID;
/** \brief Interrupt Enable Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_IEN_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_IEN;
/** \brief Input Monitoring Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_IMON_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_IMON;
/** \brief Interrupt Node Pointer Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_INP_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_INP;
/** \brief Interrupt Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_IS_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_IS;
/** \brief Interrupt Status Reset Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_ISR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_ISR;
/** \brief Interrupt Status Set Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_ISS_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_ISS;
/** \brief Kernel Reset Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_KRST0_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_KRST0;
/** \brief Kernel Reset Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_KRST1_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_KRST1;
/** \brief Kernel Reset Status Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_KRSTCLR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_KRSTCLR;
/** \brief Kernel State Control Sensitivity Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_KSCSR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_KSCSR;
/** \brief Lost Indicator Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_LI_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_LI;
/** \brief Module Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_MCFG_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_MCFG;
/** \brief Multi-Channel Mode Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_MCMCTR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_MCMCTR;
/** \brief Multi-Channel Mode Output Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_MCMOUT_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_MCMOUT;
/** \brief Multi-Channel Mode Output Shadow Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_MCMOUTS_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_MCMOUTS;
/** \brief Modulation Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_MODCTR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_MODCTR;
/** \brief CCU60 Module Output Select Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_MOSEL_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_MOSEL;
/** \brief OCDS Control and Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_OCS_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_OCS;
/** \brief Port Input Select Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_PISEL0_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_PISEL0;
/** \brief Port Input Select Register 2 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_PISEL2_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_PISEL2;
/** \brief Passive State Level Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_PSLR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_PSLR;
/** \brief Timer T12 Counter Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_T12_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_T12;
/** \brief Dead-Time Control Register for Timer12 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_T12DTC_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_T12DTC;
/** \brief T12 Mode Select Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_T12MSEL_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_T12MSEL;
/** \brief Timer 12 Period Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_T12PR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_T12PR;
/** \brief Timer T13 Counter Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_T13_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_T13;
/** \brief Timer 13 Period Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_T13PR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_T13PR;
/** \brief Timer Control Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_TCTR0_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_TCTR0;
/** \brief Timer Control Register 2 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_TCTR2_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_TCTR2;
/** \brief Timer Control Register 4 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_TCTR4_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_TCTR4;
/** \brief Trap Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CCU6_TRPCTR_Bits B; /**< \brief Bitfield access */
} Ifx_CCU6_TRPCTR;
/** \} */
/******************************************************************************/
/** \addtogroup IfxSfr_Ccu6_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief CCU6 object */
typedef volatile struct _Ifx_CCU6
{
Ifx_CCU6_CLC CLC; /**< \brief 0, Clock Control Register*/
Ifx_CCU6_MCFG MCFG; /**< \brief 4, Module Configuration Register*/
Ifx_CCU6_ID ID; /**< \brief 8, Module Identification Register*/
Ifx_CCU6_MOSEL MOSEL; /**< \brief C, CCU60 Module Output Select Register*/
Ifx_CCU6_PISEL0 PISEL0; /**< \brief 10, Port Input Select Register 0*/
Ifx_CCU6_PISEL2 PISEL2; /**< \brief 14, Port Input Select Register 2*/
Ifx_UReg_8Bit reserved_18[4]; /**< \brief 18, \internal Reserved */
Ifx_CCU6_KSCSR KSCSR; /**< \brief 1C, Kernel State Control Sensitivity Register*/
Ifx_CCU6_T12 T12; /**< \brief 20, Timer T12 Counter Register*/
Ifx_CCU6_T12PR T12PR; /**< \brief 24, Timer 12 Period Register*/
Ifx_CCU6_T12DTC T12DTC; /**< \brief 28, Dead-Time Control Register for Timer12*/
Ifx_UReg_8Bit reserved_2C[4]; /**< \brief 2C, \internal Reserved */
Ifx_CCU6_CC6R CC6R[3]; /**< \brief 30, Capture/Compare Register for Channel CC6${x}*/
Ifx_UReg_8Bit reserved_3C[4]; /**< \brief 3C, \internal Reserved */
Ifx_CCU6_CC6SR CC6SR[3]; /**< \brief 40, Capture/Compare Shadow Reg. for Channel CC6${x}*/
Ifx_UReg_8Bit reserved_4C[4]; /**< \brief 4C, \internal Reserved */
Ifx_CCU6_T13 T13; /**< \brief 50, Timer T13 Counter Register*/
Ifx_CCU6_T13PR T13PR; /**< \brief 54, Timer 13 Period Register*/
Ifx_CCU6_CC63R CC63R; /**< \brief 58, Compare Register for T13*/
Ifx_CCU6_CC63SR CC63SR; /**< \brief 5C, Compare Shadow Register for T13*/
Ifx_CCU6_CMPSTAT CMPSTAT; /**< \brief 60, Compare State Register*/
Ifx_CCU6_CMPMODIF CMPMODIF; /**< \brief 64, Compare State Modification Register*/
Ifx_CCU6_T12MSEL T12MSEL; /**< \brief 68, T12 Mode Select Register*/
Ifx_UReg_8Bit reserved_6C[4]; /**< \brief 6C, \internal Reserved */
Ifx_CCU6_TCTR0 TCTR0; /**< \brief 70, Timer Control Register 0*/
Ifx_CCU6_TCTR2 TCTR2; /**< \brief 74, Timer Control Register 2*/
Ifx_CCU6_TCTR4 TCTR4; /**< \brief 78, Timer Control Register 4*/
Ifx_UReg_8Bit reserved_7C[4]; /**< \brief 7C, \internal Reserved */
Ifx_CCU6_MODCTR MODCTR; /**< \brief 80, Modulation Control Register*/
Ifx_CCU6_TRPCTR TRPCTR; /**< \brief 84, Trap Control Register*/
Ifx_CCU6_PSLR PSLR; /**< \brief 88, Passive State Level Register*/
Ifx_CCU6_MCMOUTS MCMOUTS; /**< \brief 8C, Multi-Channel Mode Output Shadow Register*/
Ifx_CCU6_MCMOUT MCMOUT; /**< \brief 90, Multi-Channel Mode Output Register*/
Ifx_CCU6_MCMCTR MCMCTR; /**< \brief 94, Multi-Channel Mode Control Register*/
Ifx_CCU6_IMON IMON; /**< \brief 98, Input Monitoring Register*/
Ifx_CCU6_LI LI; /**< \brief 9C, Lost Indicator Register*/
Ifx_CCU6_IS IS; /**< \brief A0, Interrupt Status Register*/
Ifx_CCU6_ISS ISS; /**< \brief A4, Interrupt Status Set Register*/
Ifx_CCU6_ISR ISR; /**< \brief A8, Interrupt Status Reset Register*/
Ifx_CCU6_INP INP; /**< \brief AC, Interrupt Node Pointer Register*/
Ifx_CCU6_IEN IEN; /**< \brief B0, Interrupt Enable Register*/
Ifx_UReg_8Bit reserved_B4[52]; /**< \brief B4, \internal Reserved */
Ifx_CCU6_OCS OCS; /**< \brief E8, OCDS Control and Status Register*/
Ifx_CCU6_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register*/
Ifx_CCU6_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1*/
Ifx_CCU6_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0*/
Ifx_UReg_8Bit reserved_F8[4]; /**< \brief F8, \internal Reserved */
Ifx_CCU6_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0*/
} Ifx_CCU6;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXCCU6_REGDEF_H */

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/**
* \file IfxConverter_bf.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Converter_Registers_BitfieldsMask Bitfields mask and offset
* \ingroup IfxSfr_Converter_Registers
*
*/
#ifndef IFXCONVERTER_BF_H
#define IFXCONVERTER_BF_H 1
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Converter_Registers_BitfieldsMask
* \{ */
/** \brief Length for Ifx_CONVERTER_CLC_Bits.DISR */
#define IFX_CONVERTER_CLC_DISR_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_CLC_Bits.DISR */
#define IFX_CONVERTER_CLC_DISR_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_CLC_Bits.DISR */
#define IFX_CONVERTER_CLC_DISR_OFF (0u)
/** \brief Length for Ifx_CONVERTER_CLC_Bits.DISS */
#define IFX_CONVERTER_CLC_DISS_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_CLC_Bits.DISS */
#define IFX_CONVERTER_CLC_DISS_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_CLC_Bits.DISS */
#define IFX_CONVERTER_CLC_DISS_OFF (1u)
/** \brief Length for Ifx_CONVERTER_CLC_Bits.EDIS */
#define IFX_CONVERTER_CLC_EDIS_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_CLC_Bits.EDIS */
#define IFX_CONVERTER_CLC_EDIS_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_CLC_Bits.EDIS */
#define IFX_CONVERTER_CLC_EDIS_OFF (3u)
/** \brief Length for Ifx_CONVERTER_ID_Bits.MOD_REV */
#define IFX_CONVERTER_ID_MOD_REV_LEN (8u)
/** \brief Mask for Ifx_CONVERTER_ID_Bits.MOD_REV */
#define IFX_CONVERTER_ID_MOD_REV_MSK (0xffu)
/** \brief Offset for Ifx_CONVERTER_ID_Bits.MOD_REV */
#define IFX_CONVERTER_ID_MOD_REV_OFF (0u)
/** \brief Length for Ifx_CONVERTER_ID_Bits.MOD_TYPE */
#define IFX_CONVERTER_ID_MOD_TYPE_LEN (8u)
/** \brief Mask for Ifx_CONVERTER_ID_Bits.MOD_TYPE */
#define IFX_CONVERTER_ID_MOD_TYPE_MSK (0xffu)
/** \brief Offset for Ifx_CONVERTER_ID_Bits.MOD_TYPE */
#define IFX_CONVERTER_ID_MOD_TYPE_OFF (8u)
/** \brief Length for Ifx_CONVERTER_ID_Bits.MOD_NUMBER */
#define IFX_CONVERTER_ID_MOD_NUMBER_LEN (16u)
/** \brief Mask for Ifx_CONVERTER_ID_Bits.MOD_NUMBER */
#define IFX_CONVERTER_ID_MOD_NUMBER_MSK (0xffffu)
/** \brief Offset for Ifx_CONVERTER_ID_Bits.MOD_NUMBER */
#define IFX_CONVERTER_ID_MOD_NUMBER_OFF (16u)
/** \brief Length for Ifx_CONVERTER_OCS_Bits.SUS */
#define IFX_CONVERTER_OCS_SUS_LEN (4u)
/** \brief Mask for Ifx_CONVERTER_OCS_Bits.SUS */
#define IFX_CONVERTER_OCS_SUS_MSK (0xfu)
/** \brief Offset for Ifx_CONVERTER_OCS_Bits.SUS */
#define IFX_CONVERTER_OCS_SUS_OFF (24u)
/** \brief Length for Ifx_CONVERTER_OCS_Bits.SUS_P */
#define IFX_CONVERTER_OCS_SUS_P_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_OCS_Bits.SUS_P */
#define IFX_CONVERTER_OCS_SUS_P_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_OCS_Bits.SUS_P */
#define IFX_CONVERTER_OCS_SUS_P_OFF (28u)
/** \brief Length for Ifx_CONVERTER_OCS_Bits.SUSSTA */
#define IFX_CONVERTER_OCS_SUSSTA_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_OCS_Bits.SUSSTA */
#define IFX_CONVERTER_OCS_SUSSTA_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_OCS_Bits.SUSSTA */
#define IFX_CONVERTER_OCS_SUSSTA_OFF (29u)
/** \brief Length for Ifx_CONVERTER_KRSTCLR_Bits.CLR */
#define IFX_CONVERTER_KRSTCLR_CLR_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_KRSTCLR_Bits.CLR */
#define IFX_CONVERTER_KRSTCLR_CLR_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_KRSTCLR_Bits.CLR */
#define IFX_CONVERTER_KRSTCLR_CLR_OFF (0u)
/** \brief Length for Ifx_CONVERTER_KRST1_Bits.RST */
#define IFX_CONVERTER_KRST1_RST_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_KRST1_Bits.RST */
#define IFX_CONVERTER_KRST1_RST_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_KRST1_Bits.RST */
#define IFX_CONVERTER_KRST1_RST_OFF (0u)
/** \brief Length for Ifx_CONVERTER_KRST0_Bits.RST */
#define IFX_CONVERTER_KRST0_RST_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_KRST0_Bits.RST */
#define IFX_CONVERTER_KRST0_RST_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_KRST0_Bits.RST */
#define IFX_CONVERTER_KRST0_RST_OFF (0u)
/** \brief Length for Ifx_CONVERTER_KRST0_Bits.RSTSTAT */
#define IFX_CONVERTER_KRST0_RSTSTAT_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_KRST0_Bits.RSTSTAT */
#define IFX_CONVERTER_KRST0_RSTSTAT_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_KRST0_Bits.RSTSTAT */
#define IFX_CONVERTER_KRST0_RSTSTAT_OFF (1u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN0 */
#define IFX_CONVERTER_ACCEN0_EN0_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN0 */
#define IFX_CONVERTER_ACCEN0_EN0_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN0 */
#define IFX_CONVERTER_ACCEN0_EN0_OFF (0u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN1 */
#define IFX_CONVERTER_ACCEN0_EN1_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN1 */
#define IFX_CONVERTER_ACCEN0_EN1_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN1 */
#define IFX_CONVERTER_ACCEN0_EN1_OFF (1u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN2 */
#define IFX_CONVERTER_ACCEN0_EN2_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN2 */
#define IFX_CONVERTER_ACCEN0_EN2_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN2 */
#define IFX_CONVERTER_ACCEN0_EN2_OFF (2u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN3 */
#define IFX_CONVERTER_ACCEN0_EN3_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN3 */
#define IFX_CONVERTER_ACCEN0_EN3_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN3 */
#define IFX_CONVERTER_ACCEN0_EN3_OFF (3u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN4 */
#define IFX_CONVERTER_ACCEN0_EN4_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN4 */
#define IFX_CONVERTER_ACCEN0_EN4_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN4 */
#define IFX_CONVERTER_ACCEN0_EN4_OFF (4u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN5 */
#define IFX_CONVERTER_ACCEN0_EN5_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN5 */
#define IFX_CONVERTER_ACCEN0_EN5_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN5 */
#define IFX_CONVERTER_ACCEN0_EN5_OFF (5u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN6 */
#define IFX_CONVERTER_ACCEN0_EN6_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN6 */
#define IFX_CONVERTER_ACCEN0_EN6_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN6 */
#define IFX_CONVERTER_ACCEN0_EN6_OFF (6u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN7 */
#define IFX_CONVERTER_ACCEN0_EN7_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN7 */
#define IFX_CONVERTER_ACCEN0_EN7_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN7 */
#define IFX_CONVERTER_ACCEN0_EN7_OFF (7u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN8 */
#define IFX_CONVERTER_ACCEN0_EN8_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN8 */
#define IFX_CONVERTER_ACCEN0_EN8_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN8 */
#define IFX_CONVERTER_ACCEN0_EN8_OFF (8u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN9 */
#define IFX_CONVERTER_ACCEN0_EN9_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN9 */
#define IFX_CONVERTER_ACCEN0_EN9_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN9 */
#define IFX_CONVERTER_ACCEN0_EN9_OFF (9u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN10 */
#define IFX_CONVERTER_ACCEN0_EN10_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN10 */
#define IFX_CONVERTER_ACCEN0_EN10_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN10 */
#define IFX_CONVERTER_ACCEN0_EN10_OFF (10u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN11 */
#define IFX_CONVERTER_ACCEN0_EN11_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN11 */
#define IFX_CONVERTER_ACCEN0_EN11_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN11 */
#define IFX_CONVERTER_ACCEN0_EN11_OFF (11u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN12 */
#define IFX_CONVERTER_ACCEN0_EN12_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN12 */
#define IFX_CONVERTER_ACCEN0_EN12_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN12 */
#define IFX_CONVERTER_ACCEN0_EN12_OFF (12u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN13 */
#define IFX_CONVERTER_ACCEN0_EN13_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN13 */
#define IFX_CONVERTER_ACCEN0_EN13_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN13 */
#define IFX_CONVERTER_ACCEN0_EN13_OFF (13u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN14 */
#define IFX_CONVERTER_ACCEN0_EN14_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN14 */
#define IFX_CONVERTER_ACCEN0_EN14_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN14 */
#define IFX_CONVERTER_ACCEN0_EN14_OFF (14u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN15 */
#define IFX_CONVERTER_ACCEN0_EN15_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN15 */
#define IFX_CONVERTER_ACCEN0_EN15_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN15 */
#define IFX_CONVERTER_ACCEN0_EN15_OFF (15u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN16 */
#define IFX_CONVERTER_ACCEN0_EN16_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN16 */
#define IFX_CONVERTER_ACCEN0_EN16_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN16 */
#define IFX_CONVERTER_ACCEN0_EN16_OFF (16u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN17 */
#define IFX_CONVERTER_ACCEN0_EN17_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN17 */
#define IFX_CONVERTER_ACCEN0_EN17_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN17 */
#define IFX_CONVERTER_ACCEN0_EN17_OFF (17u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN18 */
#define IFX_CONVERTER_ACCEN0_EN18_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN18 */
#define IFX_CONVERTER_ACCEN0_EN18_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN18 */
#define IFX_CONVERTER_ACCEN0_EN18_OFF (18u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN19 */
#define IFX_CONVERTER_ACCEN0_EN19_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN19 */
#define IFX_CONVERTER_ACCEN0_EN19_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN19 */
#define IFX_CONVERTER_ACCEN0_EN19_OFF (19u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN20 */
#define IFX_CONVERTER_ACCEN0_EN20_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN20 */
#define IFX_CONVERTER_ACCEN0_EN20_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN20 */
#define IFX_CONVERTER_ACCEN0_EN20_OFF (20u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN21 */
#define IFX_CONVERTER_ACCEN0_EN21_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN21 */
#define IFX_CONVERTER_ACCEN0_EN21_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN21 */
#define IFX_CONVERTER_ACCEN0_EN21_OFF (21u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN22 */
#define IFX_CONVERTER_ACCEN0_EN22_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN22 */
#define IFX_CONVERTER_ACCEN0_EN22_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN22 */
#define IFX_CONVERTER_ACCEN0_EN22_OFF (22u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN23 */
#define IFX_CONVERTER_ACCEN0_EN23_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN23 */
#define IFX_CONVERTER_ACCEN0_EN23_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN23 */
#define IFX_CONVERTER_ACCEN0_EN23_OFF (23u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN24 */
#define IFX_CONVERTER_ACCEN0_EN24_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN24 */
#define IFX_CONVERTER_ACCEN0_EN24_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN24 */
#define IFX_CONVERTER_ACCEN0_EN24_OFF (24u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN25 */
#define IFX_CONVERTER_ACCEN0_EN25_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN25 */
#define IFX_CONVERTER_ACCEN0_EN25_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN25 */
#define IFX_CONVERTER_ACCEN0_EN25_OFF (25u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN26 */
#define IFX_CONVERTER_ACCEN0_EN26_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN26 */
#define IFX_CONVERTER_ACCEN0_EN26_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN26 */
#define IFX_CONVERTER_ACCEN0_EN26_OFF (26u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN27 */
#define IFX_CONVERTER_ACCEN0_EN27_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN27 */
#define IFX_CONVERTER_ACCEN0_EN27_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN27 */
#define IFX_CONVERTER_ACCEN0_EN27_OFF (27u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN28 */
#define IFX_CONVERTER_ACCEN0_EN28_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN28 */
#define IFX_CONVERTER_ACCEN0_EN28_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN28 */
#define IFX_CONVERTER_ACCEN0_EN28_OFF (28u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN29 */
#define IFX_CONVERTER_ACCEN0_EN29_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN29 */
#define IFX_CONVERTER_ACCEN0_EN29_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN29 */
#define IFX_CONVERTER_ACCEN0_EN29_OFF (29u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN30 */
#define IFX_CONVERTER_ACCEN0_EN30_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN30 */
#define IFX_CONVERTER_ACCEN0_EN30_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN30 */
#define IFX_CONVERTER_ACCEN0_EN30_OFF (30u)
/** \brief Length for Ifx_CONVERTER_ACCEN0_Bits.EN31 */
#define IFX_CONVERTER_ACCEN0_EN31_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_ACCEN0_Bits.EN31 */
#define IFX_CONVERTER_ACCEN0_EN31_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_ACCEN0_Bits.EN31 */
#define IFX_CONVERTER_ACCEN0_EN31_OFF (31u)
/** \brief Length for Ifx_CONVERTER_CCCTRL_Bits.TC */
#define IFX_CONVERTER_CCCTRL_TC_LEN (4u)
/** \brief Mask for Ifx_CONVERTER_CCCTRL_Bits.TC */
#define IFX_CONVERTER_CCCTRL_TC_MSK (0xfu)
/** \brief Offset for Ifx_CONVERTER_CCCTRL_Bits.TC */
#define IFX_CONVERTER_CCCTRL_TC_OFF (28u)
/** \brief Length for Ifx_CONVERTER_PHSCFG_Bits.PHSDIV */
#define IFX_CONVERTER_PHSCFG_PHSDIV_LEN (4u)
/** \brief Mask for Ifx_CONVERTER_PHSCFG_Bits.PHSDIV */
#define IFX_CONVERTER_PHSCFG_PHSDIV_MSK (0xfu)
/** \brief Offset for Ifx_CONVERTER_PHSCFG_Bits.PHSDIV */
#define IFX_CONVERTER_PHSCFG_PHSDIV_OFF (0u)
/** \brief Length for Ifx_CONVERTER_PHSCFG_Bits.PDWC */
#define IFX_CONVERTER_PHSCFG_PDWC_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_PHSCFG_Bits.PDWC */
#define IFX_CONVERTER_PHSCFG_PDWC_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_PHSCFG_Bits.PDWC */
#define IFX_CONVERTER_PHSCFG_PDWC_OFF (15u)
/** \brief Length for Ifx_CONVERTER_PHSSFTY_Bits.ALF */
#define IFX_CONVERTER_PHSSFTY_ALF_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_PHSSFTY_Bits.ALF */
#define IFX_CONVERTER_PHSSFTY_ALF_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_PHSSFTY_Bits.ALF */
#define IFX_CONVERTER_PHSSFTY_ALF_OFF (0u)
/** \brief Length for Ifx_CONVERTER_PHSSFTY_Bits.FIPD0 */
#define IFX_CONVERTER_PHSSFTY_FIPD0_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_PHSSFTY_Bits.FIPD0 */
#define IFX_CONVERTER_PHSSFTY_FIPD0_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_PHSSFTY_Bits.FIPD0 */
#define IFX_CONVERTER_PHSSFTY_FIPD0_OFF (4u)
/** \brief Length for Ifx_CONVERTER_PHSSFTY_Bits.FICN0 */
#define IFX_CONVERTER_PHSSFTY_FICN0_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_PHSSFTY_Bits.FICN0 */
#define IFX_CONVERTER_PHSSFTY_FICN0_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_PHSSFTY_Bits.FICN0 */
#define IFX_CONVERTER_PHSSFTY_FICN0_OFF (5u)
/** \brief Length for Ifx_CONVERTER_PHSSFTY_Bits.ALFCLR */
#define IFX_CONVERTER_PHSSFTY_ALFCLR_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_PHSSFTY_Bits.ALFCLR */
#define IFX_CONVERTER_PHSSFTY_ALFCLR_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_PHSSFTY_Bits.ALFCLR */
#define IFX_CONVERTER_PHSSFTY_ALFCLR_OFF (16u)
/** \brief Length for Ifx_CONVERTER_PHSSFTY_Bits.FIPD1 */
#define IFX_CONVERTER_PHSSFTY_FIPD1_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_PHSSFTY_Bits.FIPD1 */
#define IFX_CONVERTER_PHSSFTY_FIPD1_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_PHSSFTY_Bits.FIPD1 */
#define IFX_CONVERTER_PHSSFTY_FIPD1_OFF (20u)
/** \brief Length for Ifx_CONVERTER_PHSSFTY_Bits.FICN1 */
#define IFX_CONVERTER_PHSSFTY_FICN1_LEN (1u)
/** \brief Mask for Ifx_CONVERTER_PHSSFTY_Bits.FICN1 */
#define IFX_CONVERTER_PHSSFTY_FICN1_MSK (0x1u)
/** \brief Offset for Ifx_CONVERTER_PHSSFTY_Bits.FICN1 */
#define IFX_CONVERTER_PHSSFTY_FICN1_OFF (21u)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXCONVERTER_BF_H */

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/**
* \file IfxConverter_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Converter_Registers_Cfg Converter address
* \ingroup IfxSfr_Converter_Registers
*
* \defgroup IfxSfr_Converter_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Converter_Registers_Cfg
*
* \defgroup IfxSfr_Converter_Registers_Cfg_Convctrl 2-CONVCTRL
* \ingroup IfxSfr_Converter_Registers_Cfg
*
*
*/
#ifndef IFXCONVERTER_REG_H
#define IFXCONVERTER_REG_H 1
/******************************************************************************/
#include "IfxConverter_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Converter_Registers_Cfg_BaseAddress
* \{ */
/** \brief CONVERTER object */
#define MODULE_CONVCTRL /*lint --e(923, 9078)*/ ((*(Ifx_CONVERTER*)0xF0025000u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Converter_Registers_Cfg_Convctrl
* \{ */
/** \brief 0, Clock Control Register */
#define CONVCTRL_CLC /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_CLC*)0xF0025000u)
/** \brief 8, Module Identification Register */
#define CONVCTRL_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_ID*)0xF0025008u)
/** \brief 28, OCDS Control and Status Register */
#define CONVCTRL_OCS /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_OCS*)0xF0025028u)
/** \brief 2C, Kernel Reset Status Clear Register */
#define CONVCTRL_KRSTCLR /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_KRSTCLR*)0xF002502Cu)
/** \brief 30, Kernel Reset Register 1 */
#define CONVCTRL_KRST1 /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_KRST1*)0xF0025030u)
/** \brief 34, Kernel Reset Register 0 */
#define CONVCTRL_KRST0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_KRST0*)0xF0025034u)
/** \brief 3C, Access Enable Register 0 */
#define CONVCTRL_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_ACCEN0*)0xF002503Cu)
/** \brief 7C, Converter Control Block Control Register */
#define CONVCTRL_CCCTRL /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_CCCTRL*)0xF002507Cu)
/** \brief 80, Phase Synchronizer Configuration Register */
#define CONVCTRL_PHSCFG /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_PHSCFG*)0xF0025080u)
/** \brief 84, Phase Synchronizer Safety Control Register */
#define CONVCTRL_PHSSFTY /*lint --e(923, 9078)*/ (*(volatile Ifx_CONVERTER_PHSSFTY*)0xF0025084u)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXCONVERTER_REG_H */

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/**
* \file IfxConverter_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Converter_Registers Converter Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Converter_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Converter_Registers
*
* \defgroup IfxSfr_Converter_Registers_union Register unions
* \ingroup IfxSfr_Converter_Registers
*
* \defgroup IfxSfr_Converter_Registers_struct Memory map
* \ingroup IfxSfr_Converter_Registers
*/
#ifndef IFXCONVERTER_REGDEF_H
#define IFXCONVERTER_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Converter_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_CONVERTER_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_CONVERTER_ACCEN0_Bits;
/** \brief Converter Control Block Control Register */
typedef struct _Ifx_CONVERTER_CCCTRL_Bits
{
Ifx_UReg_32Bit reserved_0:28; /**< \brief [27:0] \internal Reserved */
Ifx_UReg_32Bit TC:4; /**< \brief [31:28] Test Control - TC (rw) */
} Ifx_CONVERTER_CCCTRL_Bits;
/** \brief Clock Control Register */
typedef struct _Ifx_CONVERTER_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (rh) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control - EDIS (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_CONVERTER_CLC_Bits;
/** \brief Module Identification Register */
typedef struct _Ifx_CONVERTER_ID_Bits
{
Ifx_UReg_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision - MOD_REV (r) */
Ifx_UReg_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Type - MOD_TYPE (r) */
Ifx_UReg_32Bit MOD_NUMBER:16; /**< \brief [31:16] Module Number - MOD_NUMBER (r) */
} Ifx_CONVERTER_ID_Bits;
/** \brief Kernel Reset Register 0 */
typedef struct _Ifx_CONVERTER_KRST0_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status - RSTSTAT (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_CONVERTER_KRST0_Bits;
/** \brief Kernel Reset Register 1 */
typedef struct _Ifx_CONVERTER_KRST1_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_CONVERTER_KRST1_Bits;
/** \brief Kernel Reset Status Clear Register */
typedef struct _Ifx_CONVERTER_KRSTCLR_Bits
{
Ifx_UReg_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear - CLR (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_CONVERTER_KRSTCLR_Bits;
/** \brief OCDS Control and Status Register */
typedef struct _Ifx_CONVERTER_OCS_Bits
{
Ifx_UReg_32Bit reserved_0:24; /**< \brief [23:0] \internal Reserved */
Ifx_UReg_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control - SUS (rw) */
Ifx_UReg_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection - SUS_P (w) */
Ifx_UReg_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State - SUSSTA (rh) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_CONVERTER_OCS_Bits;
/** \brief Phase Synchronizer Configuration Register */
typedef struct _Ifx_CONVERTER_PHSCFG_Bits
{
Ifx_UReg_32Bit PHSDIV:4; /**< \brief [3:0] Phase Synchronizer Divider - PHSDIV (rwh) */
Ifx_UReg_32Bit reserved_4:11; /**< \brief [14:4] \internal Reserved */
Ifx_UReg_32Bit PDWC:1; /**< \brief [15:15] Write Control for Phase Sync. Divider - PDWC (w) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_CONVERTER_PHSCFG_Bits;
/** \brief Phase Synchronizer Safety Control Register */
typedef struct _Ifx_CONVERTER_PHSSFTY_Bits
{
Ifx_UReg_32Bit ALF:1; /**< \brief [0:0] Alarm Flag for Safety Features (rh) */
Ifx_UReg_32Bit reserved_1:3; /**< \brief [3:1] \internal Reserved */
Ifx_UReg_32Bit FIPD0:1; /**< \brief [4:4] Fault Injection Phase sync Divider (w) */
Ifx_UReg_32Bit FICN0:1; /**< \brief [5:5] Fault Injection Counter (w) */
Ifx_UReg_32Bit reserved_6:10; /**< \brief [15:6] \internal Reserved */
Ifx_UReg_32Bit ALFCLR:1; /**< \brief [16:16] Alarm Flag ALF Clear (w) */
Ifx_UReg_32Bit reserved_17:3; /**< \brief [19:17] \internal Reserved */
Ifx_UReg_32Bit FIPD1:1; /**< \brief [20:20] Fault Injection Phase sync Divider (w) */
Ifx_UReg_32Bit FICN1:1; /**< \brief [21:21] Fault Injection Phase sync Divider (w) */
Ifx_UReg_32Bit reserved_22:10; /**< \brief [31:22] \internal Reserved */
} Ifx_CONVERTER_PHSSFTY_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_converter_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_ACCEN0;
/** \brief Converter Control Block Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_CCCTRL_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_CCCTRL;
/** \brief Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_CLC;
/** \brief Module Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_ID_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_ID;
/** \brief Kernel Reset Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_KRST0_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_KRST0;
/** \brief Kernel Reset Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_KRST1_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_KRST1;
/** \brief Kernel Reset Status Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_KRSTCLR_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_KRSTCLR;
/** \brief OCDS Control and Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_OCS_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_OCS;
/** \brief Phase Synchronizer Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_PHSCFG_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_PHSCFG;
/** \brief Phase Synchronizer Safety Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_CONVERTER_PHSSFTY_Bits B; /**< \brief Bitfield access */
} Ifx_CONVERTER_PHSSFTY;
/** \} */
/******************************************************************************/
/** \addtogroup IfxSfr_Converter_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief CONVERTER object */
typedef volatile struct _Ifx_CONVERTER
{
Ifx_CONVERTER_CLC CLC; /**< \brief 0, Clock Control Register*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_CONVERTER_ID ID; /**< \brief 8, Module Identification Register*/
Ifx_UReg_8Bit reserved_C[28]; /**< \brief C, \internal Reserved */
Ifx_CONVERTER_OCS OCS; /**< \brief 28, OCDS Control and Status Register*/
Ifx_CONVERTER_KRSTCLR KRSTCLR; /**< \brief 2C, Kernel Reset Status Clear Register*/
Ifx_CONVERTER_KRST1 KRST1; /**< \brief 30, Kernel Reset Register 1*/
Ifx_CONVERTER_KRST0 KRST0; /**< \brief 34, Kernel Reset Register 0*/
Ifx_UReg_8Bit reserved_38[4]; /**< \brief 38, \internal Reserved */
Ifx_CONVERTER_ACCEN0 ACCEN0; /**< \brief 3C, Access Enable Register 0*/
Ifx_UReg_8Bit reserved_40[60]; /**< \brief 40, \internal Reserved */
Ifx_CONVERTER_CCCTRL CCCTRL; /**< \brief 7C, Converter Control Block Control Register*/
Ifx_CONVERTER_PHSCFG PHSCFG; /**< \brief 80, Phase Synchronizer Configuration Register*/
Ifx_CONVERTER_PHSSFTY PHSSFTY; /**< \brief 84, Phase Synchronizer Safety Control Register*/
Ifx_UReg_8Bit reserved_88[120]; /**< \brief 88, \internal Reserved */
} Ifx_CONVERTER;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXCONVERTER_REGDEF_H */

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/**
* \file IfxDam_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.4.0.R0
* Specification: TC3xx User Manual V1.4.0.R0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Dam_Registers_Cfg Dam address
* \ingroup IfxSfr_Dam_Registers
*
* \defgroup IfxSfr_Dam_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Dam_Registers_Cfg
*
* \defgroup IfxSfr_Dam_Registers_Cfg_Dam0 2-DAM0
* \ingroup IfxSfr_Dam_Registers_Cfg
*
*
*/
#ifndef IFXDAM_REG_H
#define IFXDAM_REG_H 1
/******************************************************************************/
#include "IfxDam_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dam_Registers_Cfg_BaseAddress
* \{ */
/** \brief DAM object */
#define MODULE_DAM0 /*lint --e(923, 9078)*/ ((*(Ifx_DAM*)0xF8500000u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dam_Registers_Cfg_Dam0
* \{ */
/** \brief 0, DAM Clock Control Register */
#define DAM0_CLC /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_CLC*)0xF8500000u)
/** \brief 8, DAM Module ID Register */
#define DAM0_MODID /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_MODID*)0xF8500008u)
/** \brief 10, DAM Access Enable Register 0 */
#define DAM0_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_ACCEN0*)0xF8500010u)
/** \brief 14, DAM Access Enable Register 1 */
#define DAM0_ACCEN1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_ACCEN1*)0xF8500014u)
/** \brief 20, DAM Memory Control Register */
#define DAM0_MEMCON /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_MEMCON*)0xF8500020u)
/** \brief 50, DAM Region Lower Address Register */
#define DAM0_RGN0_LA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_LA*)0xF8500050u)
/** Alias (User Manual Name) for DAM0_RGN0_LA.
* To use register names with standard convension, please use DAM0_RGN0_LA.
*/
#define DAM0_RGNLA0 (DAM0_RGN0_LA)
/** \brief 54, DAM Region Upper Address Register */
#define DAM0_RGN0_UA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_UA*)0xF8500054u)
/** Alias (User Manual Name) for DAM0_RGN0_UA.
* To use register names with standard convension, please use DAM0_RGN0_UA.
*/
#define DAM0_RGNUA0 (DAM0_RGN0_UA)
/** \brief 58, DAM Region Write Enable Register A */
#define DAM0_RGN0_ACCENA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENA*)0xF8500058u)
/** Alias (User Manual Name) for DAM0_RGN0_ACCENA.
* To use register names with standard convension, please use DAM0_RGN0_ACCENA.
*/
#define DAM0_RGNACCENWA0 (DAM0_RGN0_ACCENA)
/** \brief 5C, DAM Region Write Enable Register B */
#define DAM0_RGN0_ACCENB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENB*)0xF850005Cu)
/** Alias (User Manual Name) for DAM0_RGN0_ACCENB.
* To use register names with standard convension, please use DAM0_RGN0_ACCENB.
*/
#define DAM0_RGNACCENWB0 (DAM0_RGN0_ACCENB)
/** \brief 60, DAM Region Lower Address Register */
#define DAM0_RGN1_LA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_LA*)0xF8500060u)
/** Alias (User Manual Name) for DAM0_RGN1_LA.
* To use register names with standard convension, please use DAM0_RGN1_LA.
*/
#define DAM0_RGNLA1 (DAM0_RGN1_LA)
/** \brief 64, DAM Region Upper Address Register */
#define DAM0_RGN1_UA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_UA*)0xF8500064u)
/** Alias (User Manual Name) for DAM0_RGN1_UA.
* To use register names with standard convension, please use DAM0_RGN1_UA.
*/
#define DAM0_RGNUA1 (DAM0_RGN1_UA)
/** \brief 68, DAM Region Write Enable Register A */
#define DAM0_RGN1_ACCENA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENA*)0xF8500068u)
/** Alias (User Manual Name) for DAM0_RGN1_ACCENA.
* To use register names with standard convension, please use DAM0_RGN1_ACCENA.
*/
#define DAM0_RGNACCENWA1 (DAM0_RGN1_ACCENA)
/** \brief 6C, DAM Region Write Enable Register B */
#define DAM0_RGN1_ACCENB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENB*)0xF850006Cu)
/** Alias (User Manual Name) for DAM0_RGN1_ACCENB.
* To use register names with standard convension, please use DAM0_RGN1_ACCENB.
*/
#define DAM0_RGNACCENWB1 (DAM0_RGN1_ACCENB)
/** \brief 70, DAM Region Lower Address Register */
#define DAM0_RGN2_LA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_LA*)0xF8500070u)
/** Alias (User Manual Name) for DAM0_RGN2_LA.
* To use register names with standard convension, please use DAM0_RGN2_LA.
*/
#define DAM0_RGNLA2 (DAM0_RGN2_LA)
/** \brief 74, DAM Region Upper Address Register */
#define DAM0_RGN2_UA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_UA*)0xF8500074u)
/** Alias (User Manual Name) for DAM0_RGN2_UA.
* To use register names with standard convension, please use DAM0_RGN2_UA.
*/
#define DAM0_RGNUA2 (DAM0_RGN2_UA)
/** \brief 78, DAM Region Write Enable Register A */
#define DAM0_RGN2_ACCENA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENA*)0xF8500078u)
/** Alias (User Manual Name) for DAM0_RGN2_ACCENA.
* To use register names with standard convension, please use DAM0_RGN2_ACCENA.
*/
#define DAM0_RGNACCENWA2 (DAM0_RGN2_ACCENA)
/** \brief 7C, DAM Region Write Enable Register B */
#define DAM0_RGN2_ACCENB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENB*)0xF850007Cu)
/** Alias (User Manual Name) for DAM0_RGN2_ACCENB.
* To use register names with standard convension, please use DAM0_RGN2_ACCENB.
*/
#define DAM0_RGNACCENWB2 (DAM0_RGN2_ACCENB)
/** \brief 80, DAM Region Lower Address Register */
#define DAM0_RGN3_LA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_LA*)0xF8500080u)
/** Alias (User Manual Name) for DAM0_RGN3_LA.
* To use register names with standard convension, please use DAM0_RGN3_LA.
*/
#define DAM0_RGNLA3 (DAM0_RGN3_LA)
/** \brief 84, DAM Region Upper Address Register */
#define DAM0_RGN3_UA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_UA*)0xF8500084u)
/** Alias (User Manual Name) for DAM0_RGN3_UA.
* To use register names with standard convension, please use DAM0_RGN3_UA.
*/
#define DAM0_RGNUA3 (DAM0_RGN3_UA)
/** \brief 88, DAM Region Write Enable Register A */
#define DAM0_RGN3_ACCENA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENA*)0xF8500088u)
/** Alias (User Manual Name) for DAM0_RGN3_ACCENA.
* To use register names with standard convension, please use DAM0_RGN3_ACCENA.
*/
#define DAM0_RGNACCENWA3 (DAM0_RGN3_ACCENA)
/** \brief 8C, DAM Region Write Enable Register B */
#define DAM0_RGN3_ACCENB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENB*)0xF850008Cu)
/** Alias (User Manual Name) for DAM0_RGN3_ACCENB.
* To use register names with standard convension, please use DAM0_RGN3_ACCENB.
*/
#define DAM0_RGNACCENWB3 (DAM0_RGN3_ACCENB)
/** \brief 90, DAM Region Lower Address Register */
#define DAM0_RGN4_LA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_LA*)0xF8500090u)
/** Alias (User Manual Name) for DAM0_RGN4_LA.
* To use register names with standard convension, please use DAM0_RGN4_LA.
*/
#define DAM0_RGNLA4 (DAM0_RGN4_LA)
/** \brief 94, DAM Region Upper Address Register */
#define DAM0_RGN4_UA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_UA*)0xF8500094u)
/** Alias (User Manual Name) for DAM0_RGN4_UA.
* To use register names with standard convension, please use DAM0_RGN4_UA.
*/
#define DAM0_RGNUA4 (DAM0_RGN4_UA)
/** \brief 98, DAM Region Write Enable Register A */
#define DAM0_RGN4_ACCENA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENA*)0xF8500098u)
/** Alias (User Manual Name) for DAM0_RGN4_ACCENA.
* To use register names with standard convension, please use DAM0_RGN4_ACCENA.
*/
#define DAM0_RGNACCENWA4 (DAM0_RGN4_ACCENA)
/** \brief 9C, DAM Region Write Enable Register B */
#define DAM0_RGN4_ACCENB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENB*)0xF850009Cu)
/** Alias (User Manual Name) for DAM0_RGN4_ACCENB.
* To use register names with standard convension, please use DAM0_RGN4_ACCENB.
*/
#define DAM0_RGNACCENWB4 (DAM0_RGN4_ACCENB)
/** \brief A0, DAM Region Lower Address Register */
#define DAM0_RGN5_LA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_LA*)0xF85000A0u)
/** Alias (User Manual Name) for DAM0_RGN5_LA.
* To use register names with standard convension, please use DAM0_RGN5_LA.
*/
#define DAM0_RGNLA5 (DAM0_RGN5_LA)
/** \brief A4, DAM Region Upper Address Register */
#define DAM0_RGN5_UA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_UA*)0xF85000A4u)
/** Alias (User Manual Name) for DAM0_RGN5_UA.
* To use register names with standard convension, please use DAM0_RGN5_UA.
*/
#define DAM0_RGNUA5 (DAM0_RGN5_UA)
/** \brief A8, DAM Region Write Enable Register A */
#define DAM0_RGN5_ACCENA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENA*)0xF85000A8u)
/** Alias (User Manual Name) for DAM0_RGN5_ACCENA.
* To use register names with standard convension, please use DAM0_RGN5_ACCENA.
*/
#define DAM0_RGNACCENWA5 (DAM0_RGN5_ACCENA)
/** \brief AC, DAM Region Write Enable Register B */
#define DAM0_RGN5_ACCENB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENB*)0xF85000ACu)
/** Alias (User Manual Name) for DAM0_RGN5_ACCENB.
* To use register names with standard convension, please use DAM0_RGN5_ACCENB.
*/
#define DAM0_RGNACCENWB5 (DAM0_RGN5_ACCENB)
/** \brief B0, DAM Region Lower Address Register */
#define DAM0_RGN6_LA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_LA*)0xF85000B0u)
/** Alias (User Manual Name) for DAM0_RGN6_LA.
* To use register names with standard convension, please use DAM0_RGN6_LA.
*/
#define DAM0_RGNLA6 (DAM0_RGN6_LA)
/** \brief B4, DAM Region Upper Address Register */
#define DAM0_RGN6_UA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_UA*)0xF85000B4u)
/** Alias (User Manual Name) for DAM0_RGN6_UA.
* To use register names with standard convension, please use DAM0_RGN6_UA.
*/
#define DAM0_RGNUA6 (DAM0_RGN6_UA)
/** \brief B8, DAM Region Write Enable Register A */
#define DAM0_RGN6_ACCENA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENA*)0xF85000B8u)
/** Alias (User Manual Name) for DAM0_RGN6_ACCENA.
* To use register names with standard convension, please use DAM0_RGN6_ACCENA.
*/
#define DAM0_RGNACCENWA6 (DAM0_RGN6_ACCENA)
/** \brief BC, DAM Region Write Enable Register B */
#define DAM0_RGN6_ACCENB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENB*)0xF85000BCu)
/** Alias (User Manual Name) for DAM0_RGN6_ACCENB.
* To use register names with standard convension, please use DAM0_RGN6_ACCENB.
*/
#define DAM0_RGNACCENWB6 (DAM0_RGN6_ACCENB)
/** \brief C0, DAM Region Lower Address Register */
#define DAM0_RGN7_LA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_LA*)0xF85000C0u)
/** Alias (User Manual Name) for DAM0_RGN7_LA.
* To use register names with standard convension, please use DAM0_RGN7_LA.
*/
#define DAM0_RGNLA7 (DAM0_RGN7_LA)
/** \brief C4, DAM Region Upper Address Register */
#define DAM0_RGN7_UA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_UA*)0xF85000C4u)
/** Alias (User Manual Name) for DAM0_RGN7_UA.
* To use register names with standard convension, please use DAM0_RGN7_UA.
*/
#define DAM0_RGNUA7 (DAM0_RGN7_UA)
/** \brief C8, DAM Region Write Enable Register A */
#define DAM0_RGN7_ACCENA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENA*)0xF85000C8u)
/** Alias (User Manual Name) for DAM0_RGN7_ACCENA.
* To use register names with standard convension, please use DAM0_RGN7_ACCENA.
*/
#define DAM0_RGNACCENWA7 (DAM0_RGN7_ACCENA)
/** \brief CC, DAM Region Write Enable Register B */
#define DAM0_RGN7_ACCENB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGN_ACCENB*)0xF85000CCu)
/** Alias (User Manual Name) for DAM0_RGN7_ACCENB.
* To use register names with standard convension, please use DAM0_RGN7_ACCENB.
*/
#define DAM0_RGNACCENWB7 (DAM0_RGN7_ACCENB)
/** \brief D8, DAM Region Read Enable Register A */
#define DAM0_RGNACCEN0_RA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RA*)0xF85000D8u)
/** Alias (User Manual Name) for DAM0_RGNACCEN0_RA.
* To use register names with standard convension, please use DAM0_RGNACCEN0_RA.
*/
#define DAM0_RGNACCENRA0 (DAM0_RGNACCEN0_RA)
/** \brief DC, DAM Region Read Enable Register B */
#define DAM0_RGNACCEN0_RB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RB*)0xF85000DCu)
/** Alias (User Manual Name) for DAM0_RGNACCEN0_RB.
* To use register names with standard convension, please use DAM0_RGNACCEN0_RB.
*/
#define DAM0_RGNACCENRB0 (DAM0_RGNACCEN0_RB)
/** \brief E8, DAM Region Read Enable Register A */
#define DAM0_RGNACCEN1_RA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RA*)0xF85000E8u)
/** Alias (User Manual Name) for DAM0_RGNACCEN1_RA.
* To use register names with standard convension, please use DAM0_RGNACCEN1_RA.
*/
#define DAM0_RGNACCENRA1 (DAM0_RGNACCEN1_RA)
/** \brief EC, DAM Region Read Enable Register B */
#define DAM0_RGNACCEN1_RB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RB*)0xF85000ECu)
/** Alias (User Manual Name) for DAM0_RGNACCEN1_RB.
* To use register names with standard convension, please use DAM0_RGNACCEN1_RB.
*/
#define DAM0_RGNACCENRB1 (DAM0_RGNACCEN1_RB)
/** \brief F8, DAM Region Read Enable Register A */
#define DAM0_RGNACCEN2_RA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RA*)0xF85000F8u)
/** Alias (User Manual Name) for DAM0_RGNACCEN2_RA.
* To use register names with standard convension, please use DAM0_RGNACCEN2_RA.
*/
#define DAM0_RGNACCENRA2 (DAM0_RGNACCEN2_RA)
/** \brief FC, DAM Region Read Enable Register B */
#define DAM0_RGNACCEN2_RB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RB*)0xF85000FCu)
/** Alias (User Manual Name) for DAM0_RGNACCEN2_RB.
* To use register names with standard convension, please use DAM0_RGNACCEN2_RB.
*/
#define DAM0_RGNACCENRB2 (DAM0_RGNACCEN2_RB)
/** \brief 108, DAM Region Read Enable Register A */
#define DAM0_RGNACCEN3_RA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RA*)0xF8500108u)
/** Alias (User Manual Name) for DAM0_RGNACCEN3_RA.
* To use register names with standard convension, please use DAM0_RGNACCEN3_RA.
*/
#define DAM0_RGNACCENRA3 (DAM0_RGNACCEN3_RA)
/** \brief 10C, DAM Region Read Enable Register B */
#define DAM0_RGNACCEN3_RB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RB*)0xF850010Cu)
/** Alias (User Manual Name) for DAM0_RGNACCEN3_RB.
* To use register names with standard convension, please use DAM0_RGNACCEN3_RB.
*/
#define DAM0_RGNACCENRB3 (DAM0_RGNACCEN3_RB)
/** \brief 118, DAM Region Read Enable Register A */
#define DAM0_RGNACCEN4_RA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RA*)0xF8500118u)
/** Alias (User Manual Name) for DAM0_RGNACCEN4_RA.
* To use register names with standard convension, please use DAM0_RGNACCEN4_RA.
*/
#define DAM0_RGNACCENRA4 (DAM0_RGNACCEN4_RA)
/** \brief 11C, DAM Region Read Enable Register B */
#define DAM0_RGNACCEN4_RB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RB*)0xF850011Cu)
/** Alias (User Manual Name) for DAM0_RGNACCEN4_RB.
* To use register names with standard convension, please use DAM0_RGNACCEN4_RB.
*/
#define DAM0_RGNACCENRB4 (DAM0_RGNACCEN4_RB)
/** \brief 128, DAM Region Read Enable Register A */
#define DAM0_RGNACCEN5_RA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RA*)0xF8500128u)
/** Alias (User Manual Name) for DAM0_RGNACCEN5_RA.
* To use register names with standard convension, please use DAM0_RGNACCEN5_RA.
*/
#define DAM0_RGNACCENRA5 (DAM0_RGNACCEN5_RA)
/** \brief 12C, DAM Region Read Enable Register B */
#define DAM0_RGNACCEN5_RB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RB*)0xF850012Cu)
/** Alias (User Manual Name) for DAM0_RGNACCEN5_RB.
* To use register names with standard convension, please use DAM0_RGNACCEN5_RB.
*/
#define DAM0_RGNACCENRB5 (DAM0_RGNACCEN5_RB)
/** \brief 138, DAM Region Read Enable Register A */
#define DAM0_RGNACCEN6_RA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RA*)0xF8500138u)
/** Alias (User Manual Name) for DAM0_RGNACCEN6_RA.
* To use register names with standard convension, please use DAM0_RGNACCEN6_RA.
*/
#define DAM0_RGNACCENRA6 (DAM0_RGNACCEN6_RA)
/** \brief 13C, DAM Region Read Enable Register B */
#define DAM0_RGNACCEN6_RB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RB*)0xF850013Cu)
/** Alias (User Manual Name) for DAM0_RGNACCEN6_RB.
* To use register names with standard convension, please use DAM0_RGNACCEN6_RB.
*/
#define DAM0_RGNACCENRB6 (DAM0_RGNACCEN6_RB)
/** \brief 148, DAM Region Read Enable Register A */
#define DAM0_RGNACCEN7_RA /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RA*)0xF8500148u)
/** Alias (User Manual Name) for DAM0_RGNACCEN7_RA.
* To use register names with standard convension, please use DAM0_RGNACCEN7_RA.
*/
#define DAM0_RGNACCENRA7 (DAM0_RGNACCEN7_RA)
/** \brief 14C, DAM Region Read Enable Register B */
#define DAM0_RGNACCEN7_RB /*lint --e(923, 9078)*/ (*(volatile Ifx_DAM_RGNACCEN_RB*)0xF850014Cu)
/** Alias (User Manual Name) for DAM0_RGNACCEN7_RB.
* To use register names with standard convension, please use DAM0_RGNACCEN7_RB.
*/
#define DAM0_RGNACCENRB7 (DAM0_RGNACCEN7_RB)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXDAM_REG_H */

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/**
* \file IfxDam_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.4.0.R0
* Specification: TC3xx User Manual V1.4.0.R0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Dam_Registers Dam Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Dam_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Dam_Registers
*
* \defgroup IfxSfr_Dam_Registers_union Register unions
* \ingroup IfxSfr_Dam_Registers
*
* \defgroup IfxSfr_Dam_Registers_struct Memory map
* \ingroup IfxSfr_Dam_Registers
*/
#ifndef IFXDAM_REGDEF_H
#define IFXDAM_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dam_Registers_Bitfields
* \{ */
/** \brief DAM Access Enable Register 0 */
typedef struct _Ifx_DAM_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_DAM_ACCEN0_Bits;
/** \brief DAM Access Enable Register 1 */
typedef struct _Ifx_DAM_ACCEN1_Bits
{
Ifx_UReg_32Bit EN32:1; /**< \brief [0:0] Access Enable for Master TAG ID 32 - EN32 (rw) */
Ifx_UReg_32Bit EN33:1; /**< \brief [1:1] Access Enable for Master TAG ID 33 - EN33 (rw) */
Ifx_UReg_32Bit EN34:1; /**< \brief [2:2] Access Enable for Master TAG ID 34 - EN34 (rw) */
Ifx_UReg_32Bit EN35:1; /**< \brief [3:3] Access Enable for Master TAG ID 35 - EN35 (rw) */
Ifx_UReg_32Bit EN36:1; /**< \brief [4:4] Access Enable for Master TAG ID 36 - EN36 (rw) */
Ifx_UReg_32Bit EN37:1; /**< \brief [5:5] Access Enable for Master TAG ID 37 - EN37 (rw) */
Ifx_UReg_32Bit EN38:1; /**< \brief [6:6] Access Enable for Master TAG ID 38 - EN38 (rw) */
Ifx_UReg_32Bit EN39:1; /**< \brief [7:7] Access Enable for Master TAG ID 39 - EN39 (rw) */
Ifx_UReg_32Bit EN40:1; /**< \brief [8:8] Access Enable for Master TAG ID 40 - EN40 (rw) */
Ifx_UReg_32Bit EN41:1; /**< \brief [9:9] Access Enable for Master TAG ID 41 - EN41 (rw) */
Ifx_UReg_32Bit EN42:1; /**< \brief [10:10] Access Enable for Master TAG ID 42 - EN42 (rw) */
Ifx_UReg_32Bit EN43:1; /**< \brief [11:11] Access Enable for Master TAG ID 43 - EN43 (rw) */
Ifx_UReg_32Bit EN44:1; /**< \brief [12:12] Access Enable for Master TAG ID 44 - EN44 (rw) */
Ifx_UReg_32Bit EN45:1; /**< \brief [13:13] Access Enable for Master TAG ID 45 - EN45 (rw) */
Ifx_UReg_32Bit EN46:1; /**< \brief [14:14] Access Enable for Master TAG ID 46 - EN46 (rw) */
Ifx_UReg_32Bit EN47:1; /**< \brief [15:15] Access Enable for Master TAG ID 47 - EN47 (rw) */
Ifx_UReg_32Bit EN48:1; /**< \brief [16:16] Access Enable for Master TAG ID 48 - EN48 (rw) */
Ifx_UReg_32Bit EN49:1; /**< \brief [17:17] Access Enable for Master TAG ID 49 - EN49 (rw) */
Ifx_UReg_32Bit EN50:1; /**< \brief [18:18] Access Enable for Master TAG ID 50 - EN50 (rw) */
Ifx_UReg_32Bit EN51:1; /**< \brief [19:19] Access Enable for Master TAG ID 51 - EN51 (rw) */
Ifx_UReg_32Bit EN52:1; /**< \brief [20:20] Access Enable for Master TAG ID 52 - EN52 (rw) */
Ifx_UReg_32Bit EN53:1; /**< \brief [21:21] Access Enable for Master TAG ID 53 - EN53 (rw) */
Ifx_UReg_32Bit EN54:1; /**< \brief [22:22] Access Enable for Master TAG ID 54 - EN54 (rw) */
Ifx_UReg_32Bit EN55:1; /**< \brief [23:23] Access Enable for Master TAG ID 55 - EN55 (rw) */
Ifx_UReg_32Bit EN56:1; /**< \brief [24:24] Access Enable for Master TAG ID 56 - EN56 (rw) */
Ifx_UReg_32Bit EN57:1; /**< \brief [25:25] Access Enable for Master TAG ID 57 - EN57 (rw) */
Ifx_UReg_32Bit EN58:1; /**< \brief [26:26] Access Enable for Master TAG ID 58 - EN58 (rw) */
Ifx_UReg_32Bit EN59:1; /**< \brief [27:27] Access Enable for Master TAG ID 59 - EN59 (rw) */
Ifx_UReg_32Bit EN60:1; /**< \brief [28:28] Access Enable for Master TAG ID 60 - EN60 (rw) */
Ifx_UReg_32Bit EN61:1; /**< \brief [29:29] Access Enable for Master TAG ID 61 - EN61 (rw) */
Ifx_UReg_32Bit EN62:1; /**< \brief [30:30] Access Enable for Master TAG ID 62 - EN62 (rw) */
Ifx_UReg_32Bit EN63:1; /**< \brief [31:31] Access Enable for Master TAG ID 63 - EN63 (rw) */
} Ifx_DAM_ACCEN1_Bits;
/** \brief DAM Clock Control Register */
typedef struct _Ifx_DAM_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] DAM Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] DAM Disable Status Bit - DISS (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_DAM_CLC_Bits;
/** \brief DAM Memory Control Register */
typedef struct _Ifx_DAM_MEMCON_Bits
{
Ifx_UReg_32Bit ROM:1; /**< \brief [0:0] Read Only Memory - ROM (rw) */
Ifx_UReg_32Bit reserved_1:1; /**< \brief [1:1] \internal Reserved */
Ifx_UReg_32Bit INTERR:1; /**< \brief [2:2] Internal ECC Error - INTERR (rwh) */
Ifx_UReg_32Bit reserved_3:1; /**< \brief [3:3] \internal Reserved */
Ifx_UReg_32Bit RMWERR:1; /**< \brief [4:4] Internal Read Modify Write Error - RMWERR (rwh) */
Ifx_UReg_32Bit reserved_5:1; /**< \brief [5:5] \internal Reserved */
Ifx_UReg_32Bit DATAERR:1; /**< \brief [6:6] SRI Data Phase ECC Error - DATAERR (rwh) */
Ifx_UReg_32Bit ADDERR:1; /**< \brief [7:7] SRI Address Phase ECC Error - ADDERR (rwh) */
Ifx_UReg_32Bit PMIC:1; /**< \brief [8:8] Protection Bit for Memory Integrity Control Bit - PMIC (w) */
Ifx_UReg_32Bit ERRDIS:1; /**< \brief [9:9] ECC Error Disable - ERRDIS (rw) */
Ifx_UReg_32Bit reserved_10:6; /**< \brief [15:10] \internal Reserved */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_DAM_MEMCON_Bits;
/** \brief DAM Module ID Register */
typedef struct _Ifx_DAM_MODID_Bits
{
Ifx_UReg_32Bit ID_VALUE:32; /**< \brief [31:0] Module Identification Value - ID_VALUE (r) */
} Ifx_DAM_MODID_Bits;
/** \brief DAM Region Read Enable Register A */
typedef struct _Ifx_DAM_RGNACCEN_RA_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_DAM_RGNACCEN_RA_Bits;
/** \brief DAM Region Read Enable Register B */
typedef struct _Ifx_DAM_RGNACCEN_RB_Bits
{
Ifx_UReg_32Bit EN32:1; /**< \brief [0:0] Access Enable for Master TAG ID 32 - EN32 (rw) */
Ifx_UReg_32Bit EN33:1; /**< \brief [1:1] Access Enable for Master TAG ID 33 - EN33 (rw) */
Ifx_UReg_32Bit EN34:1; /**< \brief [2:2] Access Enable for Master TAG ID 34 - EN34 (rw) */
Ifx_UReg_32Bit EN35:1; /**< \brief [3:3] Access Enable for Master TAG ID 35 - EN35 (rw) */
Ifx_UReg_32Bit EN36:1; /**< \brief [4:4] Access Enable for Master TAG ID 36 - EN36 (rw) */
Ifx_UReg_32Bit EN37:1; /**< \brief [5:5] Access Enable for Master TAG ID 37 - EN37 (rw) */
Ifx_UReg_32Bit EN38:1; /**< \brief [6:6] Access Enable for Master TAG ID 38 - EN38 (rw) */
Ifx_UReg_32Bit EN39:1; /**< \brief [7:7] Access Enable for Master TAG ID 39 - EN39 (rw) */
Ifx_UReg_32Bit EN40:1; /**< \brief [8:8] Access Enable for Master TAG ID 40 - EN40 (rw) */
Ifx_UReg_32Bit EN41:1; /**< \brief [9:9] Access Enable for Master TAG ID 41 - EN41 (rw) */
Ifx_UReg_32Bit EN42:1; /**< \brief [10:10] Access Enable for Master TAG ID 42 - EN42 (rw) */
Ifx_UReg_32Bit EN43:1; /**< \brief [11:11] Access Enable for Master TAG ID 43 - EN43 (rw) */
Ifx_UReg_32Bit EN44:1; /**< \brief [12:12] Access Enable for Master TAG ID 44 - EN44 (rw) */
Ifx_UReg_32Bit EN45:1; /**< \brief [13:13] Access Enable for Master TAG ID 45 - EN45 (rw) */
Ifx_UReg_32Bit EN46:1; /**< \brief [14:14] Access Enable for Master TAG ID 46 - EN46 (rw) */
Ifx_UReg_32Bit EN47:1; /**< \brief [15:15] Access Enable for Master TAG ID 47 - EN47 (rw) */
Ifx_UReg_32Bit EN48:1; /**< \brief [16:16] Access Enable for Master TAG ID 48 - EN48 (rw) */
Ifx_UReg_32Bit EN49:1; /**< \brief [17:17] Access Enable for Master TAG ID 49 - EN49 (rw) */
Ifx_UReg_32Bit EN50:1; /**< \brief [18:18] Access Enable for Master TAG ID 50 - EN50 (rw) */
Ifx_UReg_32Bit EN51:1; /**< \brief [19:19] Access Enable for Master TAG ID 51 - EN51 (rw) */
Ifx_UReg_32Bit EN52:1; /**< \brief [20:20] Access Enable for Master TAG ID 52 - EN52 (rw) */
Ifx_UReg_32Bit EN53:1; /**< \brief [21:21] Access Enable for Master TAG ID 53 - EN53 (rw) */
Ifx_UReg_32Bit EN54:1; /**< \brief [22:22] Access Enable for Master TAG ID 54 - EN54 (rw) */
Ifx_UReg_32Bit EN55:1; /**< \brief [23:23] Access Enable for Master TAG ID 55 - EN55 (rw) */
Ifx_UReg_32Bit EN56:1; /**< \brief [24:24] Access Enable for Master TAG ID 56 - EN56 (rw) */
Ifx_UReg_32Bit EN57:1; /**< \brief [25:25] Access Enable for Master TAG ID 57 - EN57 (rw) */
Ifx_UReg_32Bit EN58:1; /**< \brief [26:26] Access Enable for Master TAG ID 58 - EN58 (rw) */
Ifx_UReg_32Bit EN59:1; /**< \brief [27:27] Access Enable for Master TAG ID 59 - EN59 (rw) */
Ifx_UReg_32Bit EN60:1; /**< \brief [28:28] Access Enable for Master TAG ID 60 - EN60 (rw) */
Ifx_UReg_32Bit EN61:1; /**< \brief [29:29] Access Enable for Master TAG ID 61 - EN61 (rw) */
Ifx_UReg_32Bit EN62:1; /**< \brief [30:30] Access Enable for Master TAG ID 62 - EN62 (rw) */
Ifx_UReg_32Bit EN63:1; /**< \brief [31:31] Access Enable for Master TAG ID 63 - EN63 (rw) */
} Ifx_DAM_RGNACCEN_RB_Bits;
/** \brief DAM Region Write Enable Register A */
typedef struct _Ifx_DAM_RGN_ACCENA_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_DAM_RGN_ACCENA_Bits;
/** \brief DAM Region Write Enable Register B */
typedef struct _Ifx_DAM_RGN_ACCENB_Bits
{
Ifx_UReg_32Bit EN32:1; /**< \brief [0:0] Access Enable for Master TAG ID 32 - EN32 (rw) */
Ifx_UReg_32Bit EN33:1; /**< \brief [1:1] Access Enable for Master TAG ID 33 - EN33 (rw) */
Ifx_UReg_32Bit EN34:1; /**< \brief [2:2] Access Enable for Master TAG ID 34 - EN34 (rw) */
Ifx_UReg_32Bit EN35:1; /**< \brief [3:3] Access Enable for Master TAG ID 35 - EN35 (rw) */
Ifx_UReg_32Bit EN36:1; /**< \brief [4:4] Access Enable for Master TAG ID 36 - EN36 (rw) */
Ifx_UReg_32Bit EN37:1; /**< \brief [5:5] Access Enable for Master TAG ID 37 - EN37 (rw) */
Ifx_UReg_32Bit EN38:1; /**< \brief [6:6] Access Enable for Master TAG ID 38 - EN38 (rw) */
Ifx_UReg_32Bit EN39:1; /**< \brief [7:7] Access Enable for Master TAG ID 39 - EN39 (rw) */
Ifx_UReg_32Bit EN40:1; /**< \brief [8:8] Access Enable for Master TAG ID 40 - EN40 (rw) */
Ifx_UReg_32Bit EN41:1; /**< \brief [9:9] Access Enable for Master TAG ID 41 - EN41 (rw) */
Ifx_UReg_32Bit EN42:1; /**< \brief [10:10] Access Enable for Master TAG ID 42 - EN42 (rw) */
Ifx_UReg_32Bit EN43:1; /**< \brief [11:11] Access Enable for Master TAG ID 43 - EN43 (rw) */
Ifx_UReg_32Bit EN44:1; /**< \brief [12:12] Access Enable for Master TAG ID 44 - EN44 (rw) */
Ifx_UReg_32Bit EN45:1; /**< \brief [13:13] Access Enable for Master TAG ID 45 - EN45 (rw) */
Ifx_UReg_32Bit EN46:1; /**< \brief [14:14] Access Enable for Master TAG ID 46 - EN46 (rw) */
Ifx_UReg_32Bit EN47:1; /**< \brief [15:15] Access Enable for Master TAG ID 47 - EN47 (rw) */
Ifx_UReg_32Bit EN48:1; /**< \brief [16:16] Access Enable for Master TAG ID 48 - EN48 (rw) */
Ifx_UReg_32Bit EN49:1; /**< \brief [17:17] Access Enable for Master TAG ID 49 - EN49 (rw) */
Ifx_UReg_32Bit EN50:1; /**< \brief [18:18] Access Enable for Master TAG ID 50 - EN50 (rw) */
Ifx_UReg_32Bit EN51:1; /**< \brief [19:19] Access Enable for Master TAG ID 51 - EN51 (rw) */
Ifx_UReg_32Bit EN52:1; /**< \brief [20:20] Access Enable for Master TAG ID 52 - EN52 (rw) */
Ifx_UReg_32Bit EN53:1; /**< \brief [21:21] Access Enable for Master TAG ID 53 - EN53 (rw) */
Ifx_UReg_32Bit EN54:1; /**< \brief [22:22] Access Enable for Master TAG ID 54 - EN54 (rw) */
Ifx_UReg_32Bit EN55:1; /**< \brief [23:23] Access Enable for Master TAG ID 55 - EN55 (rw) */
Ifx_UReg_32Bit EN56:1; /**< \brief [24:24] Access Enable for Master TAG ID 56 - EN56 (rw) */
Ifx_UReg_32Bit EN57:1; /**< \brief [25:25] Access Enable for Master TAG ID 57 - EN57 (rw) */
Ifx_UReg_32Bit EN58:1; /**< \brief [26:26] Access Enable for Master TAG ID 58 - EN58 (rw) */
Ifx_UReg_32Bit EN59:1; /**< \brief [27:27] Access Enable for Master TAG ID 59 - EN59 (rw) */
Ifx_UReg_32Bit EN60:1; /**< \brief [28:28] Access Enable for Master TAG ID 60 - EN60 (rw) */
Ifx_UReg_32Bit EN61:1; /**< \brief [29:29] Access Enable for Master TAG ID 61 - EN61 (rw) */
Ifx_UReg_32Bit EN62:1; /**< \brief [30:30] Access Enable for Master TAG ID 62 - EN62 (rw) */
Ifx_UReg_32Bit EN63:1; /**< \brief [31:31] Access Enable for Master TAG ID 63 - EN63 (rw) */
} Ifx_DAM_RGN_ACCENB_Bits;
/** \brief DAM Region Lower Address Register */
typedef struct _Ifx_DAM_RGN_LA_Bits
{
Ifx_UReg_32Bit reserved_0:5; /**< \brief [4:0] \internal Reserved */
Ifx_UReg_32Bit ADDR:27; /**< \brief [31:5] Region Lower Address - ADDR (rw) */
} Ifx_DAM_RGN_LA_Bits;
/** \brief DAM Region Upper Address Register */
typedef struct _Ifx_DAM_RGN_UA_Bits
{
Ifx_UReg_32Bit reserved_0:5; /**< \brief [4:0] \internal Reserved */
Ifx_UReg_32Bit ADDR:27; /**< \brief [31:5] Region Lower Address - ADDR (rw) */
} Ifx_DAM_RGN_UA_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_dam_Registers_union
* \{ */
/** \brief DAM Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_ACCEN0;
/** \brief DAM Access Enable Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_ACCEN1_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_ACCEN1;
/** \brief DAM Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_CLC;
/** \brief DAM Memory Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_MEMCON_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_MEMCON;
/** \brief DAM Module ID Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_MODID_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_MODID;
/** \brief DAM Region Read Enable Register A */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_RGNACCEN_RA_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_RGNACCEN_RA;
/** \brief DAM Region Read Enable Register B */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_RGNACCEN_RB_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_RGNACCEN_RB;
/** \brief DAM Region Write Enable Register A */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_RGN_ACCENA_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_RGN_ACCENA;
/** \brief DAM Region Write Enable Register B */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_RGN_ACCENB_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_RGN_ACCENB;
/** \brief DAM Region Lower Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_RGN_LA_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_RGN_LA;
/** \brief DAM Region Upper Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DAM_RGN_UA_Bits B; /**< \brief Bitfield access */
} Ifx_DAM_RGN_UA;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dam_RGN_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief RGN object */
typedef volatile struct _Ifx_DAM_RGN
{
Ifx_DAM_RGN_LA LA; /**< \brief 0, DAM Region Lower Address Register*/
Ifx_DAM_RGN_UA UA; /**< \brief 4, DAM Region Upper Address Register*/
Ifx_DAM_RGN_ACCENA ACCENA; /**< \brief 8, DAM Region Write Enable Register A*/
Ifx_DAM_RGN_ACCENB ACCENB; /**< \brief C, DAM Region Write Enable Register B*/
} Ifx_DAM_RGN;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dam_RGNACCEN_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief RGNACCEN object */
typedef volatile struct _Ifx_DAM_RGNACCEN
{
Ifx_DAM_RGNACCEN_RA RA; /**< \brief 0, DAM Region Read Enable Register A*/
Ifx_DAM_RGNACCEN_RB RB; /**< \brief 4, DAM Region Read Enable Register B*/
Ifx_UReg_8Bit reserved_8[8]; /**< \brief 8, \internal Reserved */
} Ifx_DAM_RGNACCEN;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dam_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief DAM object */
typedef volatile struct _Ifx_DAM
{
Ifx_DAM_CLC CLC; /**< \brief 0, DAM Clock Control Register*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_DAM_MODID MODID; /**< \brief 8, DAM Module ID Register*/
Ifx_UReg_8Bit reserved_C[4]; /**< \brief C, \internal Reserved */
Ifx_DAM_ACCEN0 ACCEN0; /**< \brief 10, DAM Access Enable Register 0*/
Ifx_DAM_ACCEN1 ACCEN1; /**< \brief 14, DAM Access Enable Register 1*/
Ifx_UReg_8Bit reserved_18[8]; /**< \brief 18, \internal Reserved */
Ifx_DAM_MEMCON MEMCON; /**< \brief 20, DAM Memory Control Register*/
Ifx_UReg_8Bit reserved_24[44]; /**< \brief 24, \internal Reserved */
Ifx_DAM_RGN RGN[8]; /**< \brief 50, DAM Region Write Enable Register B*/
Ifx_UReg_8Bit reserved_D0[8]; /**< \brief D0, \internal Reserved */
Ifx_DAM_RGNACCEN RGNACCEN[8]; /**< \brief D8, */
Ifx_UReg_8Bit reserved_158[32424]; /**< \brief 158, \internal Reserved */
} Ifx_DAM;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXDAM_REGDEF_H */

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/**
* \file IfxDma_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Dma_Registers Dma Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Dma_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Dma_Registers
*
* \defgroup IfxSfr_Dma_Registers_union Register unions
* \ingroup IfxSfr_Dma_Registers
*
* \defgroup IfxSfr_Dma_Registers_struct Memory map
* \ingroup IfxSfr_Dma_Registers
*/
#ifndef IFXDMA_REGDEF_H
#define IFXDMA_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dma_Registers_Bitfields
* \{ */
/** \brief RP ${r} Access Enable Register 0 */
typedef struct _Ifx_DMA_ACCEN_ACCENR0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID q - ENq (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID q - ENq (rw) */
} Ifx_DMA_ACCEN_ACCENR0_Bits;
/** \brief RP ${r} Access Enable Register 1 */
typedef struct _Ifx_DMA_ACCEN_ACCENR1_Bits
{
Ifx_UReg_32Bit reserved_0:32; /**< \brief [31:0] \internal Reserved */
} Ifx_DMA_ACCEN_ACCENR1_Bits;
/** \brief DMARAM Channel ${c} Address and Interrupt Control Register */
typedef struct _Ifx_DMA_CH_ADICR_Bits
{
Ifx_UReg_32Bit SMF:3; /**< \brief [2:0] Source Address Modification Factor - SMF (rwh) */
Ifx_UReg_32Bit INCS:1; /**< \brief [3:3] Increment of Source Address - INCS (rwh) */
Ifx_UReg_32Bit DMF:3; /**< \brief [6:4] Destination Address Modification Factor - DMF (rwh) */
Ifx_UReg_32Bit INCD:1; /**< \brief [7:7] Increment of Destination Address - INCD (rwh) */
Ifx_UReg_32Bit CBLS:4; /**< \brief [11:8] Circular Buffer Length Source - CBLS (rw) */
Ifx_UReg_32Bit CBLD:4; /**< \brief [15:12] Circular Buffer Length Destination - CBLD (rw) */
Ifx_UReg_32Bit SHCT:4; /**< \brief [19:16] Shadow Control - SHCT (rwh) */
Ifx_UReg_32Bit SCBE:1; /**< \brief [20:20] Source Circular Buffer Enable - SCBE (rwh) */
Ifx_UReg_32Bit DCBE:1; /**< \brief [21:21] Destination Circular Buffer Enable - DCBE (rwh) */
Ifx_UReg_32Bit STAMP:1; /**< \brief [22:22] Time Stamp - STAMP (rwh) */
Ifx_UReg_32Bit reserved_23:1; /**< \brief [23:23] \internal Reserved */
Ifx_UReg_32Bit WRPSE:1; /**< \brief [24:24] Wrap Source Enable - WRPSE (rwh) */
Ifx_UReg_32Bit WRPDE:1; /**< \brief [25:25] Wrap Destination Enable - WRPDE (rwh) */
Ifx_UReg_32Bit INTCT:2; /**< \brief [27:26] Interrupt Control - INTCT (rwh) */
Ifx_UReg_32Bit IRDV:4; /**< \brief [31:28] Interrupt Raise Detect Value - IRDV (rwh) */
} Ifx_DMA_CH_ADICR_Bits;
/** \brief DMARAM Channel ${c} Configuration Register */
typedef struct _Ifx_DMA_CH_CHCFGR_Bits
{
Ifx_UReg_32Bit TREL:14; /**< \brief [13:0] Transfer Reload Value - TREL (rwh) */
Ifx_UReg_32Bit reserved_14:2; /**< \brief [15:14] \internal Reserved */
Ifx_UReg_32Bit BLKM:3; /**< \brief [18:16] Block Mode - BLKM (rwh) */
Ifx_UReg_32Bit RROAT:1; /**< \brief [19:19] Reset Request Only After Transaction - RROAT (rwh) */
Ifx_UReg_32Bit CHMODE:1; /**< \brief [20:20] Channel Operation Mode - CHMODE (rwh) */
Ifx_UReg_32Bit CHDW:3; /**< \brief [23:21] Channel Data Width - CHDW (rwh) */
Ifx_UReg_32Bit PATSEL:3; /**< \brief [26:24] Pattern Select - PATSEL (rwh) */
Ifx_UReg_32Bit SWAP:1; /**< \brief [27:27] Swap Data CRC Byte Order - SWAP (rw) */
Ifx_UReg_32Bit PRSEL:1; /**< \brief [28:28] Peripheral Request Select - PRSEL (rwh) */
Ifx_UReg_32Bit reserved_29:3; /**< \brief [31:29] \internal Reserved */
} Ifx_DMA_CH_CHCFGR_Bits;
/** \brief DMARAM Channel ${c} Control and Status Register */
typedef struct _Ifx_DMA_CH_CHCSR_Bits
{
Ifx_UReg_32Bit TCOUNT:14; /**< \brief [13:0] Transfer Count - TCOUNT (rh) */
Ifx_UReg_32Bit reserved_14:1; /**< \brief [14:14] \internal Reserved */
Ifx_UReg_32Bit LXO:1; /**< \brief [15:15] Old Value of Pattern Detection - LXO (rh) */
Ifx_UReg_32Bit WRPS:1; /**< \brief [16:16] Wrap Source Buffer - WRPS (rh) */
Ifx_UReg_32Bit WRPD:1; /**< \brief [17:17] Wrap Destination Buffer - WRPD (rh) */
Ifx_UReg_32Bit ICH:1; /**< \brief [18:18] Interrupt from Channel - ICH (rh) */
Ifx_UReg_32Bit IPM:1; /**< \brief [19:19] Pattern Detection from Channel - IPM (rh) */
Ifx_UReg_32Bit reserved_20:2; /**< \brief [21:20] \internal Reserved */
Ifx_UReg_32Bit BUFFER:1; /**< \brief [22:22] DMA Double Buffering Active Buffer - BUFFER (rh) */
Ifx_UReg_32Bit FROZEN:1; /**< \brief [23:23] DMA Double Buffering Frozen Buffer - FROZEN (rwh) */
Ifx_UReg_32Bit SWB:1; /**< \brief [24:24] DMA Double Buffering Switch Buffer - SWB (w) */
Ifx_UReg_32Bit CWRP:1; /**< \brief [25:25] Clear Wrap Buffer Interrupt - CWRP (w) */
Ifx_UReg_32Bit CICH:1; /**< \brief [26:26] Clear Interrupt for DMA Channel - CICH (w) */
Ifx_UReg_32Bit SIT:1; /**< \brief [27:27] Set Interrupt Trigger for DMA Channel - SIT (w) */
Ifx_UReg_32Bit reserved_28:3; /**< \brief [30:28] \internal Reserved */
Ifx_UReg_32Bit SCH:1; /**< \brief [31:31] Set Transaction Request - SCH (w) */
} Ifx_DMA_CH_CHCSR_Bits;
/** \brief DMARAM Channel ${c} Destination Address Register */
typedef struct _Ifx_DMA_CH_DADR_Bits
{
Ifx_UReg_32Bit DADR:32; /**< \brief [31:0] Destination Address - DADR (rwh) */
} Ifx_DMA_CH_DADR_Bits;
/** \brief DMARAM Channel ${c} Read Data CRC Register */
typedef struct _Ifx_DMA_CH_RDCRCR_Bits
{
Ifx_UReg_32Bit RDCRC:32; /**< \brief [31:0] Read Data CRC - RDCRC (rwh) */
} Ifx_DMA_CH_RDCRCR_Bits;
/** \brief DMARAM Channel ${c} Source Address Register */
typedef struct _Ifx_DMA_CH_SADR_Bits
{
Ifx_UReg_32Bit SADR:32; /**< \brief [31:0] Source Address - SADR (rwh) */
} Ifx_DMA_CH_SADR_Bits;
/** \brief DMARAM Channel ${c} Source and Destination Address CRC Register */
typedef struct _Ifx_DMA_CH_SDCRCR_Bits
{
Ifx_UReg_32Bit SDCRC:32; /**< \brief [31:0] Source and Destination Address CRC - SDCRC (rwh) */
} Ifx_DMA_CH_SDCRCR_Bits;
/** \brief DMARAM Channel ${c} Shadow Address Register */
typedef struct _Ifx_DMA_CH_SHADR_Bits
{
Ifx_UReg_32Bit SHADR:32; /**< \brief [31:0] Shadowed Address - SHADR (rwh) */
} Ifx_DMA_CH_SHADR_Bits;
/** \brief DMA Clock Control Register */
typedef struct _Ifx_DMA_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (rh) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control - EDIS (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_DMA_CLC_Bits;
/** \brief RP ${r} Error Interrupt Set Register */
typedef struct _Ifx_DMA_ERRINTR_Bits
{
Ifx_UReg_32Bit SIT:1; /**< \brief [0:0] Set Error Interrupt Service Request - SIT (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_DMA_ERRINTR_Bits;
/** \brief DMA Channel ${c} Resource Partition Register */
typedef struct _Ifx_DMA_HRR_Bits
{
Ifx_UReg_32Bit HRP:2; /**< \brief [1:0] DMA Channel Resource Partition - HRP (rw) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_DMA_HRR_Bits;
/** \brief DMA Identification Register */
typedef struct _Ifx_DMA_ID_Bits
{
Ifx_UReg_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number - MOD_REV (r) */
Ifx_UReg_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Type - MOD_TYPE (r) */
Ifx_UReg_32Bit MOD_NUMBER:16; /**< \brief [31:16] Module Number Value - MOD_NUMBER (r) */
} Ifx_DMA_ID_Bits;
/** \brief ME ${m} Channel Address and Interrupt Control Register */
typedef struct _Ifx_DMA_ME_ADICR_Bits
{
Ifx_UReg_32Bit SMF:3; /**< \brief [2:0] Source Address Modification Factor - SMF (rh) */
Ifx_UReg_32Bit INCS:1; /**< \brief [3:3] Increment of Source Address - INCS (rh) */
Ifx_UReg_32Bit DMF:3; /**< \brief [6:4] Destination Address Modification Factor - DMF (rh) */
Ifx_UReg_32Bit INCD:1; /**< \brief [7:7] Increment of Destination Address - INCD (rh) */
Ifx_UReg_32Bit CBLS:4; /**< \brief [11:8] Circular Buffer Length Source - CBLS (rh) */
Ifx_UReg_32Bit CBLD:4; /**< \brief [15:12] Circular Buffer Length Destination - CBLD (rh) */
Ifx_UReg_32Bit SHCT:4; /**< \brief [19:16] Shadow Control - SHCT (rh) */
Ifx_UReg_32Bit SCBE:1; /**< \brief [20:20] Source Circular Buffer Enable - SCBE (rh) */
Ifx_UReg_32Bit DCBE:1; /**< \brief [21:21] Destination Circular Buffer Enable - DCBE (rh) */
Ifx_UReg_32Bit STAMP:1; /**< \brief [22:22] Time Stamp - STAMP (rh) */
Ifx_UReg_32Bit reserved_23:1; /**< \brief [23:23] \internal Reserved */
Ifx_UReg_32Bit WRPSE:1; /**< \brief [24:24] Wrap Source Enable - WRPSE (rh) */
Ifx_UReg_32Bit WRPDE:1; /**< \brief [25:25] Wrap Destination Enable - WRPDE (rh) */
Ifx_UReg_32Bit INTCT:2; /**< \brief [27:26] Interrupt Control - INTCT (rh) */
Ifx_UReg_32Bit IRDV:4; /**< \brief [31:28] Interrupt Raise Detect Value - IRDV (rh) */
} Ifx_DMA_ME_ADICR_Bits;
/** \brief ME ${m} Channel Control Register */
typedef struct _Ifx_DMA_ME_CHCR_Bits
{
Ifx_UReg_32Bit TREL:14; /**< \brief [13:0] Transfer Reload Value - TREL (rh) */
Ifx_UReg_32Bit reserved_14:2; /**< \brief [15:14] \internal Reserved */
Ifx_UReg_32Bit BLKM:3; /**< \brief [18:16] Block Mode - BLKM (rh) */
Ifx_UReg_32Bit RROAT:1; /**< \brief [19:19] Reset Request Only After Transaction - RROAT (rh) */
Ifx_UReg_32Bit CHMODE:1; /**< \brief [20:20] Channel Operation Mode - CHMODE (rh) */
Ifx_UReg_32Bit CHDW:3; /**< \brief [23:21] Channel Data Width - CHDW (rh) */
Ifx_UReg_32Bit PATSEL:3; /**< \brief [26:24] Pattern Select - PATSEL (rh) */
Ifx_UReg_32Bit SWAP:1; /**< \brief [27:27] Swap Data CRC byte order - SWAP (rh) */
Ifx_UReg_32Bit PRSEL:1; /**< \brief [28:28] Peripheral Request Select - PRSEL (rh) */
Ifx_UReg_32Bit reserved_29:3; /**< \brief [31:29] \internal Reserved */
} Ifx_DMA_ME_CHCR_Bits;
/** \brief ME ${m} Channel Status Register */
typedef struct _Ifx_DMA_ME_CHSR_Bits
{
Ifx_UReg_32Bit TCOUNT:14; /**< \brief [13:0] Transfer Count Status - TCOUNT (rh) */
Ifx_UReg_32Bit reserved_14:1; /**< \brief [14:14] \internal Reserved */
Ifx_UReg_32Bit LXO:1; /**< \brief [15:15] Old Value of Pattern Detection - LXO (rh) */
Ifx_UReg_32Bit WRPS:1; /**< \brief [16:16] Wrap Source Buffer - WRPS (rh) */
Ifx_UReg_32Bit WRPD:1; /**< \brief [17:17] Wrap Destination Buffer - WRPD (rh) */
Ifx_UReg_32Bit ICH:1; /**< \brief [18:18] Interrupt from Channel - ICH (rh) */
Ifx_UReg_32Bit IPM:1; /**< \brief [19:19] Pattern Detection from Channel - IPM (rh) */
Ifx_UReg_32Bit reserved_20:2; /**< \brief [21:20] \internal Reserved */
Ifx_UReg_32Bit BUFFER:1; /**< \brief [22:22] DMA Double Buffering Active Buffer - BUFFER (rh) */
Ifx_UReg_32Bit FROZEN:1; /**< \brief [23:23] DMA Double Buffering Frozen Buffer - FROZEN (rh) */
Ifx_UReg_32Bit reserved_24:8; /**< \brief [31:24] \internal Reserved */
} Ifx_DMA_ME_CHSR_Bits;
/** \brief ME ${m} Clear Error Register */
typedef struct _Ifx_DMA_ME_CLRE_Bits
{
Ifx_UReg_32Bit reserved_0:16; /**< \brief [15:0] \internal Reserved */
Ifx_UReg_32Bit CSER:1; /**< \brief [16:16] Clear ME Source Error - CSER (w) */
Ifx_UReg_32Bit CDER:1; /**< \brief [17:17] Clear ME Destination Error - CDER (w) */
Ifx_UReg_32Bit reserved_18:2; /**< \brief [19:18] \internal Reserved */
Ifx_UReg_32Bit CSPBER:1; /**< \brief [20:20] Clear SPB Error - CSPBER (w) */
Ifx_UReg_32Bit CSRIER:1; /**< \brief [21:21] Clear SRI Error - CSRIER (w) */
Ifx_UReg_32Bit reserved_22:2; /**< \brief [23:22] \internal Reserved */
Ifx_UReg_32Bit CRAMER:1; /**< \brief [24:24] Clear RAM Error - CRAMER (w) */
Ifx_UReg_32Bit CSLLER:1; /**< \brief [25:25] Clear SLL Error - CSLLER (w) */
Ifx_UReg_32Bit CDLLER:1; /**< \brief [26:26] Clear DLL Error - CDLLER (w) */
Ifx_UReg_32Bit reserved_27:5; /**< \brief [31:27] \internal Reserved */
} Ifx_DMA_ME_CLRE_Bits;
/** \brief ME ${m} Channel Destination Address Register */
typedef struct _Ifx_DMA_ME_DADR_Bits
{
Ifx_UReg_32Bit DADR:32; /**< \brief [31:0] Destination Address - DADR (rh) */
} Ifx_DMA_ME_DADR_Bits;
/** \brief ME ${m} Enable Error Register */
typedef struct _Ifx_DMA_ME_EER_Bits
{
Ifx_UReg_32Bit reserved_0:16; /**< \brief [15:0] \internal Reserved */
Ifx_UReg_32Bit ESER:1; /**< \brief [16:16] Enable ME Source Error - ESER (rw) */
Ifx_UReg_32Bit EDER:1; /**< \brief [17:17] Enable ME Destination Error - EDER (rw) */
Ifx_UReg_32Bit reserved_18:8; /**< \brief [25:18] \internal Reserved */
Ifx_UReg_32Bit ELER:1; /**< \brief [26:26] Enable ME DMA Linked List Error - ELER (rw) */
Ifx_UReg_32Bit reserved_27:5; /**< \brief [31:27] \internal Reserved */
} Ifx_DMA_ME_EER_Bits;
/** \brief ME ${m} Error Status Register */
typedef struct _Ifx_DMA_ME_ERRSR_Bits
{
Ifx_UReg_32Bit LEC:7; /**< \brief [6:0] ME Last Error Channel - LEC (rh) */
Ifx_UReg_32Bit reserved_7:9; /**< \brief [15:7] \internal Reserved */
Ifx_UReg_32Bit SER:1; /**< \brief [16:16] ME Source Error - SER (rh) */
Ifx_UReg_32Bit DER:1; /**< \brief [17:17] ME Destination Error - DER (rh) */
Ifx_UReg_32Bit reserved_18:2; /**< \brief [19:18] \internal Reserved */
Ifx_UReg_32Bit SPBER:1; /**< \brief [20:20] ME SPB Bus Error - SPBER (rh) */
Ifx_UReg_32Bit SRIER:1; /**< \brief [21:21] ME SRI Bus Error - SRIER (rh) */
Ifx_UReg_32Bit reserved_22:2; /**< \brief [23:22] \internal Reserved */
Ifx_UReg_32Bit RAMER:1; /**< \brief [24:24] ME RAM Error - RAMER (rh) */
Ifx_UReg_32Bit SLLER:1; /**< \brief [25:25] ME Safe Linked List Error - SLLER (rh) */
Ifx_UReg_32Bit DLLER:1; /**< \brief [26:26] ME DMA Linked List Error - DLLER (rh) */
Ifx_UReg_32Bit reserved_27:5; /**< \brief [31:27] \internal Reserved */
} Ifx_DMA_ME_ERRSR_Bits;
/** \brief ME ${m} Read Register 0 */
typedef struct _Ifx_DMA_ME_R0_Bits
{
Ifx_UReg_32Bit RD00:8; /**< \brief [7:0] DMA Read Move Data Byte - RD00 (rh) */
Ifx_UReg_32Bit RD01:8; /**< \brief [15:8] DMA Read Move Data Byte - RD01 (rh) */
Ifx_UReg_32Bit RD02:8; /**< \brief [23:16] DMA Read Move Data Byte - RD02 (rh) */
Ifx_UReg_32Bit RD03:8; /**< \brief [31:24] DMA Read Move Data Byte - RD03 (rh) */
} Ifx_DMA_ME_R0_Bits;
/** \brief ME ${m} Read Register 1 */
typedef struct _Ifx_DMA_ME_R1_Bits
{
Ifx_UReg_32Bit RD10:8; /**< \brief [7:0] DMA Read Move Data Byte - RD10 (rh) */
Ifx_UReg_32Bit RD11:8; /**< \brief [15:8] DMA Read Move Data Byte - RD11 (rh) */
Ifx_UReg_32Bit RD12:8; /**< \brief [23:16] DMA Read Move Data Byte - RD12 (rh) */
Ifx_UReg_32Bit RD13:8; /**< \brief [31:24] DMA Read Move Data Byte - RD13 (rh) */
} Ifx_DMA_ME_R1_Bits;
/** \brief ME ${m} Read Register 2 */
typedef struct _Ifx_DMA_ME_R2_Bits
{
Ifx_UReg_32Bit RD20:8; /**< \brief [7:0] DMA Read Move Data Byte - RD20 (rh) */
Ifx_UReg_32Bit RD21:8; /**< \brief [15:8] DMA Read Move Data Byte - RD21 (rh) */
Ifx_UReg_32Bit RD22:8; /**< \brief [23:16] DMA Read Move Data Byte - RD22 (rh) */
Ifx_UReg_32Bit RD23:8; /**< \brief [31:24] DMA Read Move Data Byte - RD23 (rh) */
} Ifx_DMA_ME_R2_Bits;
/** \brief ME ${m} Read Register 3 */
typedef struct _Ifx_DMA_ME_R3_Bits
{
Ifx_UReg_32Bit RD30:8; /**< \brief [7:0] DMA Read Move Data Byte - RD30 (rh) */
Ifx_UReg_32Bit RD31:8; /**< \brief [15:8] DMA Read Move Data Byte - RD31 (rh) */
Ifx_UReg_32Bit RD32:8; /**< \brief [23:16] DMA Read Move Data Byte - RD32 (rh) */
Ifx_UReg_32Bit RD33:8; /**< \brief [31:24] DMA Read Move Data Byte - RD33 (rh) */
} Ifx_DMA_ME_R3_Bits;
/** \brief ME ${m} Read Register 4 */
typedef struct _Ifx_DMA_ME_R4_Bits
{
Ifx_UReg_32Bit RD40:8; /**< \brief [7:0] DMA Read Move Data Byte - RD40 (rh) */
Ifx_UReg_32Bit RD41:8; /**< \brief [15:8] DMA Read Move Data Byte - RD41 (rh) */
Ifx_UReg_32Bit RD42:8; /**< \brief [23:16] DMA Read Move Data Byte - RD42 (rh) */
Ifx_UReg_32Bit RD43:8; /**< \brief [31:24] DMA Read Move Data Byte - RD43 (rh) */
} Ifx_DMA_ME_R4_Bits;
/** \brief ME ${m} Read Register 5 */
typedef struct _Ifx_DMA_ME_R5_Bits
{
Ifx_UReg_32Bit RD50:8; /**< \brief [7:0] DMA Read Move Data Byte - RD50 (rh) */
Ifx_UReg_32Bit RD51:8; /**< \brief [15:8] DMA Read Move Data Byte - RD51 (rh) */
Ifx_UReg_32Bit RD52:8; /**< \brief [23:16] DMA Read Move Data Byte - RD52 (rh) */
Ifx_UReg_32Bit RD53:8; /**< \brief [31:24] DMA Read Move Data Byte - RD53 (rh) */
} Ifx_DMA_ME_R5_Bits;
/** \brief ME ${m} Read Register 6 */
typedef struct _Ifx_DMA_ME_R6_Bits
{
Ifx_UReg_32Bit RD60:8; /**< \brief [7:0] DMA Read Move Data Byte - RD60 (rh) */
Ifx_UReg_32Bit RD61:8; /**< \brief [15:8] DMA Read Move Data Byte - RD61 (rh) */
Ifx_UReg_32Bit RD62:8; /**< \brief [23:16] DMA Read Move Data Byte - RD62 (rh) */
Ifx_UReg_32Bit RD63:8; /**< \brief [31:24] DMA Read Move Data Byte - RD63 (rh) */
} Ifx_DMA_ME_R6_Bits;
/** \brief ME ${m} Read Register 7 */
typedef struct _Ifx_DMA_ME_R7_Bits
{
Ifx_UReg_32Bit RD70:8; /**< \brief [7:0] DMA Read Move Data Byte - RD70 (rh) */
Ifx_UReg_32Bit RD71:8; /**< \brief [15:8] DMA Read Move Data Byte - RD71 (rh) */
Ifx_UReg_32Bit RD72:8; /**< \brief [23:16] DMA Read Move Data Byte - RD72 (rh) */
Ifx_UReg_32Bit RD73:8; /**< \brief [31:24] DMA Read Move Data Byte - RD73 (rh) */
} Ifx_DMA_ME_R7_Bits;
/** \brief ME ${m} Channel Read Data CRC Register */
typedef struct _Ifx_DMA_ME_RDCRC_Bits
{
Ifx_UReg_32Bit RDCRC:32; /**< \brief [31:0] Read Data CRC - RDCRC (rh) */
} Ifx_DMA_ME_RDCRC_Bits;
/** \brief ME ${m} Channel Source Address Register */
typedef struct _Ifx_DMA_ME_SADR_Bits
{
Ifx_UReg_32Bit SADR:32; /**< \brief [31:0] Source Address - SADR (rh) */
} Ifx_DMA_ME_SADR_Bits;
/** \brief ME ${m} Channel Source and Destination Address CRC Register */
typedef struct _Ifx_DMA_ME_SDCRC_Bits
{
Ifx_UReg_32Bit SDCRC:32; /**< \brief [31:0] Source and Destination Address CRC - SDCRC (rh) */
} Ifx_DMA_ME_SDCRC_Bits;
/** \brief ME ${m} Channel Shadow Address Register */
typedef struct _Ifx_DMA_ME_SHADR_Bits
{
Ifx_UReg_32Bit SHADR:32; /**< \brief [31:0] Shadowed Address - SHADR (rh) */
} Ifx_DMA_ME_SHADR_Bits;
/** \brief ME ${m} Status Register */
typedef struct _Ifx_DMA_ME_SR_Bits
{
Ifx_UReg_32Bit RS:1; /**< \brief [0:0] ME Read Status - RS (rh) */
Ifx_UReg_32Bit reserved_1:3; /**< \brief [3:1] \internal Reserved */
Ifx_UReg_32Bit WS:1; /**< \brief [4:4] ME Write Status - WS (rh) */
Ifx_UReg_32Bit reserved_5:11; /**< \brief [15:5] \internal Reserved */
Ifx_UReg_32Bit CH:7; /**< \brief [22:16] ME Active Channel - CH (rh) */
Ifx_UReg_32Bit reserved_23:9; /**< \brief [31:23] \internal Reserved */
} Ifx_DMA_ME_SR_Bits;
/** \brief RP ${r} Mode Register */
typedef struct _Ifx_DMA_MODE_Bits
{
Ifx_UReg_32Bit MODE:1; /**< \brief [0:0] Resource Partition Supervisor Mode - MODE (rw) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_DMA_MODE_Bits;
/** \brief DMA OCDS Trigger Set Select */
typedef struct _Ifx_DMA_OTSS_Bits
{
Ifx_UReg_32Bit TGS:4; /**< \brief [3:0] Trigger Set for OTGB0 or OTGB1 - TGS (rw) */
Ifx_UReg_32Bit reserved_4:3; /**< \brief [6:4] \internal Reserved */
Ifx_UReg_32Bit BS:1; /**< \brief [7:7] OTGB0 or OTGB1 Bus Select - BS (rw) */
Ifx_UReg_32Bit reserved_8:24; /**< \brief [31:8] \internal Reserved */
} Ifx_DMA_OTSS_Bits;
/** \brief DMA Pattern Read Register 0 */
typedef struct _Ifx_DMA_PRR0_Bits
{
Ifx_UReg_32Bit PAT00:8; /**< \brief [7:0] Pattern Data Byte - PAT00 (rw) */
Ifx_UReg_32Bit PAT01:8; /**< \brief [15:8] Pattern Data Byte - PAT01 (rw) */
Ifx_UReg_32Bit PAT02:8; /**< \brief [23:16] Pattern Data Byte - PAT02 (rw) */
Ifx_UReg_32Bit PAT03:8; /**< \brief [31:24] Pattern Data Byte - PAT03 (rw) */
} Ifx_DMA_PRR0_Bits;
/** \brief DMA Pattern Read Register 1 */
typedef struct _Ifx_DMA_PRR1_Bits
{
Ifx_UReg_32Bit PAT10:8; /**< \brief [7:0] Pattern Data Byte - PAT10 (rw) */
Ifx_UReg_32Bit PAT11:8; /**< \brief [15:8] Pattern Data Byte - PAT11 (rw) */
Ifx_UReg_32Bit PAT12:8; /**< \brief [23:16] Pattern Data Byte - PAT12 (rw) */
Ifx_UReg_32Bit PAT13:8; /**< \brief [31:24] Pattern Data Byte - PAT13 (rw) */
} Ifx_DMA_PRR1_Bits;
/** \brief DMA Channel ${c} Suspend Acknowledge Register */
typedef struct _Ifx_DMA_SUSACR_Bits
{
Ifx_UReg_32Bit SUSAC:1; /**< \brief [0:0] DMA Channel Suspend State or Frozen State Active for DMA Channel - SUSAC (rh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_DMA_SUSACR_Bits;
/** \brief DMA Channel ${c} Suspend Enable Register */
typedef struct _Ifx_DMA_SUSENR_Bits
{
Ifx_UReg_32Bit SUSEN:1; /**< \brief [0:0] Channel Suspend Enable for DMA Channel - SUSEN (rw) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_DMA_SUSENR_Bits;
/** \brief DMA Time Register */
typedef struct _Ifx_DMA_TIME_Bits
{
Ifx_UReg_32Bit COUNT:32; /**< \brief [31:0] Timestamp Count - COUNT (r) */
} Ifx_DMA_TIME_Bits;
/** \brief DMA Channel ${c} Transaction State Register */
typedef struct _Ifx_DMA_TSR_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] DMA Channel Reset - RST (rwh) */
Ifx_UReg_32Bit HTRE:1; /**< \brief [1:1] DMA Channel Hardware Request Enable - HTRE (rh) */
Ifx_UReg_32Bit TRL:1; /**< \brief [2:2] DMA Channel Transaction/Transfer Request Lost - TRL (rh) */
Ifx_UReg_32Bit CH:1; /**< \brief [3:3] DMA Channel Transaction Request State - CH (rh) */
Ifx_UReg_32Bit ETRL:1; /**< \brief [4:4] Enable DMA Channel Transaction/Transfer Request Lost Interrupt - ETRL (rw) */
Ifx_UReg_32Bit reserved_5:3; /**< \brief [7:5] \internal Reserved */
Ifx_UReg_32Bit HLTREQ:1; /**< \brief [8:8] DMA Channel Halt Request - HLTREQ (rwh) */
Ifx_UReg_32Bit HLTACK:1; /**< \brief [9:9] DMA Channel Halt Acknowledge - HLTACK (rh) */
Ifx_UReg_32Bit reserved_10:6; /**< \brief [15:10] \internal Reserved */
Ifx_UReg_32Bit ECH:1; /**< \brief [16:16] Enable DMA Channel Hardware Transaction Request - ECH (w) */
Ifx_UReg_32Bit DCH:1; /**< \brief [17:17] Disable DMA Channel Hardware Transaction Request - DCH (w) */
Ifx_UReg_32Bit CTL:1; /**< \brief [18:18] Clear DMA Channel Transaction/Transfer Request Lost - CTL (w) */
Ifx_UReg_32Bit reserved_19:5; /**< \brief [23:19] \internal Reserved */
Ifx_UReg_32Bit HLTCLR:1; /**< \brief [24:24] Clear DMA Channel Halt Request and Acknowledge - HLTCLR (w) */
Ifx_UReg_32Bit reserved_25:7; /**< \brief [31:25] \internal Reserved */
} Ifx_DMA_TSR_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_dma_Registers_union
* \{ */
/** \brief RP ${r} Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ACCEN_ACCENR0_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ACCEN_ACCENR0;
/** \brief RP ${r} Access Enable Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ACCEN_ACCENR1_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ACCEN_ACCENR1;
/** \brief DMARAM Channel ${c} Address and Interrupt Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CH_ADICR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CH_ADICR;
/** \brief DMARAM Channel ${c} Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CH_CHCFGR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CH_CHCFGR;
/** \brief DMARAM Channel ${c} Control and Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CH_CHCSR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CH_CHCSR;
/** \brief DMARAM Channel ${c} Destination Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CH_DADR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CH_DADR;
/** \brief DMARAM Channel ${c} Read Data CRC Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CH_RDCRCR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CH_RDCRCR;
/** \brief DMARAM Channel ${c} Source Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CH_SADR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CH_SADR;
/** \brief DMARAM Channel ${c} Source and Destination Address CRC Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CH_SDCRCR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CH_SDCRCR;
/** \brief DMARAM Channel ${c} Shadow Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CH_SHADR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CH_SHADR;
/** \brief DMA Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_CLC;
/** \brief RP ${r} Error Interrupt Set Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ERRINTR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ERRINTR;
/** \brief DMA Channel ${c} Resource Partition Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_HRR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_HRR;
/** \brief DMA Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ID_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ID;
/** \brief ME ${m} Channel Address and Interrupt Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_ADICR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_ADICR;
/** \brief ME ${m} Channel Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_CHCR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_CHCR;
/** \brief ME ${m} Channel Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_CHSR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_CHSR;
/** \brief ME ${m} Clear Error Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_CLRE_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_CLRE;
/** \brief ME ${m} Channel Destination Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_DADR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_DADR;
/** \brief ME ${m} Enable Error Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_EER_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_EER;
/** \brief ME ${m} Error Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_ERRSR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_ERRSR;
/** \brief ME ${m} Read Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_R0_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_R0;
/** \brief ME ${m} Read Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_R1_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_R1;
/** \brief ME ${m} Read Register 2 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_R2_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_R2;
/** \brief ME ${m} Read Register 3 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_R3_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_R3;
/** \brief ME ${m} Read Register 4 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_R4_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_R4;
/** \brief ME ${m} Read Register 5 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_R5_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_R5;
/** \brief ME ${m} Read Register 6 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_R6_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_R6;
/** \brief ME ${m} Read Register 7 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_R7_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_R7;
/** \brief ME ${m} Channel Read Data CRC Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_RDCRC_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_RDCRC;
/** \brief ME ${m} Channel Source Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_SADR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_SADR;
/** \brief ME ${m} Channel Source and Destination Address CRC Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_SDCRC_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_SDCRC;
/** \brief ME ${m} Channel Shadow Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_SHADR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_SHADR;
/** \brief ME ${m} Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_ME_SR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_ME_SR;
/** \brief RP ${r} Mode Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_MODE_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_MODE;
/** \brief DMA OCDS Trigger Set Select */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_OTSS_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_OTSS;
/** \brief DMA Pattern Read Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_PRR0_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_PRR0;
/** \brief DMA Pattern Read Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_PRR1_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_PRR1;
/** \brief DMA Channel ${c} Suspend Acknowledge Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_SUSACR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_SUSACR;
/** \brief DMA Channel ${c} Suspend Enable Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_SUSENR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_SUSENR;
/** \brief DMA Time Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_TIME_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_TIME;
/** \brief DMA Channel ${c} Transaction State Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DMA_TSR_Bits B; /**< \brief Bitfield access */
} Ifx_DMA_TSR;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dma_ACCEN_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief ACCEN object */
typedef volatile struct _Ifx_DMA_ACCEN
{
Ifx_DMA_ACCEN_ACCENR0 ACCENR0; /**< \brief 0, RP ${r} Access Enable Register 0*/
Ifx_DMA_ACCEN_ACCENR1 ACCENR1; /**< \brief 4, RP ${r} Access Enable Register 1*/
} Ifx_DMA_ACCEN;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dma_ME_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief ME object */
typedef volatile struct _Ifx_DMA_ME
{
Ifx_DMA_ME_EER EER; /**< \brief 0, ME ${m} Enable Error Register*/
Ifx_DMA_ME_ERRSR ERRSR; /**< \brief 4, ME ${m} Error Status Register*/
Ifx_DMA_ME_CLRE CLRE; /**< \brief 8, ME ${m} Clear Error Register*/
Ifx_UReg_8Bit reserved_C[4]; /**< \brief C, \internal Reserved */
Ifx_DMA_ME_SR SR; /**< \brief 10, ME ${m} Status Register*/
Ifx_UReg_8Bit reserved_14[12]; /**< \brief 14, \internal Reserved */
Ifx_DMA_ME_R0 R0; /**< \brief 20, ME ${m} Read Register 0*/
Ifx_DMA_ME_R1 R1; /**< \brief 24, ME ${m} Read Register 1*/
Ifx_DMA_ME_R2 R2; /**< \brief 28, ME ${m} Read Register 2*/
Ifx_DMA_ME_R3 R3; /**< \brief 2C, ME ${m} Read Register 3*/
Ifx_DMA_ME_R4 R4; /**< \brief 30, ME ${m} Read Register 4*/
Ifx_DMA_ME_R5 R5; /**< \brief 34, ME ${m} Read Register 5*/
Ifx_DMA_ME_R6 R6; /**< \brief 38, ME ${m} Read Register 6*/
Ifx_DMA_ME_R7 R7; /**< \brief 3C, ME ${m} Read Register 7*/
Ifx_UReg_8Bit reserved_40[32]; /**< \brief 40, \internal Reserved */
Ifx_DMA_ME_RDCRC RDCRC; /**< \brief 60, ME ${m} Channel Read Data CRC Register*/
Ifx_DMA_ME_SDCRC SDCRC; /**< \brief 64, ME ${m} Channel Source and Destination Address CRC Register*/
Ifx_DMA_ME_SADR SADR; /**< \brief 68, ME ${m} Channel Source Address Register*/
Ifx_DMA_ME_DADR DADR; /**< \brief 6C, ME ${m} Channel Destination Address Register*/
Ifx_DMA_ME_ADICR ADICR; /**< \brief 70, ME ${m} Channel Address and Interrupt Control Register*/
Ifx_DMA_ME_CHCR CHCR; /**< \brief 74, ME ${m} Channel Control Register*/
Ifx_DMA_ME_SHADR SHADR; /**< \brief 78, ME ${m} Channel Shadow Address Register*/
Ifx_DMA_ME_CHSR CHSR; /**< \brief 7C, ME ${m} Channel Status Register*/
} Ifx_DMA_ME;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dma_CH_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief CH object */
typedef volatile struct _Ifx_DMA_CH
{
Ifx_DMA_CH_RDCRCR RDCRCR; /**< \brief 0, DMARAM Channel ${c} Read Data CRC Register*/
Ifx_DMA_CH_SDCRCR SDCRCR; /**< \brief 4, DMARAM Channel ${c} Source and Destination Address CRC Register*/
Ifx_DMA_CH_SADR SADR; /**< \brief 8, DMARAM Channel ${c} Source Address Register*/
Ifx_DMA_CH_DADR DADR; /**< \brief C, DMARAM Channel ${c} Destination Address Register*/
Ifx_DMA_CH_ADICR ADICR; /**< \brief 10, DMARAM Channel ${c} Address and Interrupt Control Register*/
Ifx_DMA_CH_CHCFGR CHCFGR; /**< \brief 14, DMARAM Channel ${c} Configuration Register*/
Ifx_DMA_CH_SHADR SHADR; /**< \brief 18, DMARAM Channel ${c} Shadow Address Register*/
Ifx_DMA_CH_CHCSR CHCSR; /**< \brief 1C, DMARAM Channel ${c} Control and Status Register*/
} Ifx_DMA_CH;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dma_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief DMA object */
typedef volatile struct _Ifx_DMA
{
Ifx_DMA_CLC CLC; /**< \brief 0, DMA Clock Control Register*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_DMA_ID ID; /**< \brief 8, DMA Identification Register*/
Ifx_UReg_8Bit reserved_C[52]; /**< \brief C, \internal Reserved */
Ifx_DMA_ACCEN ACCEN[4]; /**< \brief 40, RP ${r} Access Enable Register 1*/
Ifx_UReg_8Bit reserved_60[192]; /**< \brief 60, \internal Reserved */
Ifx_DMA_ME ME0; /**< \brief 120, */
Ifx_UReg_8Bit reserved_1A0[3968]; /**< \brief 1A0, \internal Reserved */
Ifx_DMA_ME ME1; /**< \brief 1120, */
Ifx_UReg_8Bit reserved_11A0[96]; /**< \brief 11A0, \internal Reserved */
Ifx_DMA_OTSS OTSS; /**< \brief 1200, DMA OCDS Trigger Set Select*/
Ifx_UReg_8Bit reserved_1204[4]; /**< \brief 1204, \internal Reserved */
Ifx_DMA_PRR0 PRR0; /**< \brief 1208, DMA Pattern Read Register 0*/
Ifx_DMA_PRR1 PRR1; /**< \brief 120C, DMA Pattern Read Register 1*/
Ifx_DMA_TIME TIME; /**< \brief 1210, DMA Time Register*/
Ifx_UReg_8Bit reserved_1214[236]; /**< \brief 1214, \internal Reserved */
Ifx_DMA_MODE MODE[4]; /**< \brief 1300, RP ${r} Mode Register*/
Ifx_UReg_8Bit reserved_1310[16]; /**< \brief 1310, \internal Reserved */
Ifx_DMA_ERRINTR ERRINTR[4]; /**< \brief 1320, RP ${r} Error Interrupt Set Register*/
Ifx_UReg_8Bit reserved_1330[1232]; /**< \brief 1330, \internal Reserved */
Ifx_DMA_HRR HRR[128]; /**< \brief 1800, DMA Channel ${c} Resource Partition Register*/
Ifx_DMA_SUSENR SUSENR[128]; /**< \brief 1A00, DMA Channel ${c} Suspend Enable Register*/
Ifx_DMA_SUSACR SUSACR[128]; /**< \brief 1C00, DMA Channel ${c} Suspend Acknowledge Register*/
Ifx_DMA_TSR TSR[128]; /**< \brief 1E00, DMA Channel ${c} Transaction State Register*/
Ifx_DMA_CH CH[128]; /**< \brief 2000, DMARAM Channel ${c} Control and Status Register*/
Ifx_UReg_8Bit reserved_3000[4096]; /**< \brief 3000, \internal Reserved */
} Ifx_DMA;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXDMA_REGDEF_H */

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/**
* \file IfxDmu_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Dmu_Registers_Cfg Dmu address
* \ingroup IfxSfr_Dmu_Registers
*
* \defgroup IfxSfr_Dmu_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Dmu_Registers_Cfg
*
* \defgroup IfxSfr_Dmu_Registers_Cfg_Dmu 2-DMU
* \ingroup IfxSfr_Dmu_Registers_Cfg
*
*
*/
#ifndef IFXDMU_REG_H
#define IFXDMU_REG_H 1
/******************************************************************************/
#include "IfxDmu_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dmu_Registers_Cfg_BaseAddress
* \{ */
/** \brief DMU object */
#define MODULE_DMU /*lint --e(923, 9078)*/ ((*(Ifx_DMU*)0xF8040000u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dmu_Registers_Cfg_Dmu
* \{ */
/** \brief 8, Module Identification Register */
#define DMU_HF_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_ID*)0xF8040008u)
/** \brief 10, Flash Status Register */
#define DMU_HF_STATUS /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_STATUS*)0xF8040010u)
/** \brief 14, Flash Control Register */
#define DMU_HF_CONTROL /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_CONTROL*)0xF8040014u)
/** \brief 18, Flash Operation Register */
#define DMU_HF_OPERATION /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_OPERATION*)0xF8040018u)
/** \brief 1C, Flash Protection Status Register */
#define DMU_HF_PROTECT /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PROTECT*)0xF804001Cu)
/** \brief 20, Flash Confirm Status Register 0 */
#define DMU_HF_CONFIRM0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_CONFIRM0*)0xF8040020u)
/** \brief 24, Flash Confirm Status Register 1 */
#define DMU_HF_CONFIRM1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_CONFIRM1*)0xF8040024u)
/** \brief 28, Flash Confirm Status Register 2 */
#define DMU_HF_CONFIRM2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_CONFIRM2*)0xF8040028u)
/** \brief 30, Enable Error Interrupt Control Register */
#define DMU_HF_EER /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_EER*)0xF8040030u)
/** \brief 34, Error Status Register */
#define DMU_HF_ERRSR /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_ERRSR*)0xF8040034u)
/** \brief 38, Clear Error Register */
#define DMU_HF_CLRE /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_CLRE*)0xF8040038u)
/** \brief 40, DF0 ECC Read Register */
#define DMU_HF_ECCR /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_ECCR*)0xF8040040u)
/** \brief 44, DF0 ECC Status Register */
#define DMU_HF_ECCS /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_ECCS*)0xF8040044u)
/** \brief 48, DF0 ECC Control Register */
#define DMU_HF_ECCC /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_ECCC*)0xF8040048u)
/** \brief 4C, DF0 ECC Write Register */
#define DMU_HF_ECCW /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_ECCW*)0xF804004Cu)
/** \brief 50, Cranking Control Register */
#define DMU_HF_CCONTROL /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_CCONTROL*)0xF8040050u)
/** \brief 60, Power Status Register */
#define DMU_HF_PSTATUS /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PSTATUS*)0xF8040060u)
/** \brief 64, Power Control Register */
#define DMU_HF_PCONTROL /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PCONTROL*)0xF8040064u)
/** \brief 68, PFLASH Wait Cycle Register */
#define DMU_HF_PWAIT /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PWAIT*)0xF8040068u)
/** \brief 6C, DFLASH Wait Cycle Register */
#define DMU_HF_DWAIT /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_DWAIT*)0xF804006Cu)
/** \brief 74, DF0 User Mode Control */
#define DMU_HF_PROCONUSR /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PROCONUSR*)0xF8040074u)
/** \brief 80, PFLASH Protection Configuration */
#define DMU_HF_PROCONPF /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PROCONPF*)0xF8040080u)
/** \brief 84, Tuning Protection Configuration */
#define DMU_HF_PROCONTP /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PROCONTP*)0xF8040084u)
/** \brief 88, DFLASH Protection Configuration */
#define DMU_HF_PROCONDF /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PROCONDF*)0xF8040088u)
/** \brief 8C, RAM Configuration */
#define DMU_HF_PROCONRAM /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PROCONRAM*)0xF804008Cu)
/** \brief 90, Debug Interface Protection Configuration */
#define DMU_HF_PROCONDBG /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_PROCONDBG*)0xF8040090u)
/** \brief F0, Suspend Control Register */
#define DMU_HF_SUSPEND /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_SUSPEND*)0xF80400F0u)
/** \brief F4, Margin Control Register */
#define DMU_HF_MARGIN /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_MARGIN*)0xF80400F4u)
/** \brief F8, Access Enable Register 1 */
#define DMU_HF_ACCEN1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_ACCEN1*)0xF80400F8u)
/** \brief FC, Access Enable Register 0 */
#define DMU_HF_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HF_ACCEN0*)0xF80400FCu)
/** \brief 10000, PFLASH Bank 0 Protection Configuration 0 */
#define DMU_HP0_PROCON_P0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P0*)0xF8050000u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_P0.
* To use register names with standard convension, please use DMU_HP0_PROCON_P0.
*/
#define DMU_HP_PROCONP00 (DMU_HP0_PROCON_P0)
/** \brief 10004, PFLASH Bank 0 Protection Configuration 1 */
#define DMU_HP0_PROCON_P1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P1*)0xF8050004u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_P1.
* To use register names with standard convension, please use DMU_HP0_PROCON_P1.
*/
#define DMU_HP_PROCONP01 (DMU_HP0_PROCON_P1)
/** \brief 10008, PFLASH Bank 0 Protection Configuration 2 */
#define DMU_HP0_PROCON_P2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P2*)0xF8050008u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_P2.
* To use register names with standard convension, please use DMU_HP0_PROCON_P2.
*/
#define DMU_HP_PROCONP02 (DMU_HP0_PROCON_P2)
/** \brief 1000C, PFLASH Bank 0 Protection Configuration 3 */
#define DMU_HP0_PROCON_P3 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P3*)0xF805000Cu)
/** Alias (User Manual Name) for DMU_HP0_PROCON_P3.
* To use register names with standard convension, please use DMU_HP0_PROCON_P3.
*/
#define DMU_HP_PROCONP03 (DMU_HP0_PROCON_P3)
/** \brief 10010, PFLASH Bank 0 Protection Configuration 4 */
#define DMU_HP0_PROCON_P4 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P4*)0xF8050010u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_P4.
* To use register names with standard convension, please use DMU_HP0_PROCON_P4.
*/
#define DMU_HP_PROCONP04 (DMU_HP0_PROCON_P4)
/** \brief 10014, PFLASH Bank 0 Protection Configuration 5 */
#define DMU_HP0_PROCON_P5 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P5*)0xF8050014u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_P5.
* To use register names with standard convension, please use DMU_HP0_PROCON_P5.
*/
#define DMU_HP_PROCONP05 (DMU_HP0_PROCON_P5)
/** \brief 10040, PFLASH Bank 0 OTP Protection Configuration 0 */
#define DMU_HP0_PROCON_OTP0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP0*)0xF8050040u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_OTP0.
* To use register names with standard convension, please use DMU_HP0_PROCON_OTP0.
*/
#define DMU_HP_PROCONOTP00 (DMU_HP0_PROCON_OTP0)
/** \brief 10044, PFLASH Bank 0 OTP Protection Configuration 1 */
#define DMU_HP0_PROCON_OTP1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP1*)0xF8050044u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_OTP1.
* To use register names with standard convension, please use DMU_HP0_PROCON_OTP1.
*/
#define DMU_HP_PROCONOTP01 (DMU_HP0_PROCON_OTP1)
/** \brief 10048, PFLASH Bank 0 OTP Protection Configuration 2 */
#define DMU_HP0_PROCON_OTP2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP2*)0xF8050048u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_OTP2.
* To use register names with standard convension, please use DMU_HP0_PROCON_OTP2.
*/
#define DMU_HP_PROCONOTP02 (DMU_HP0_PROCON_OTP2)
/** \brief 1004C, PFLASH Bank 0 OTP Protection Configuration 3 */
#define DMU_HP0_PROCON_OTP3 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP3*)0xF805004Cu)
/** Alias (User Manual Name) for DMU_HP0_PROCON_OTP3.
* To use register names with standard convension, please use DMU_HP0_PROCON_OTP3.
*/
#define DMU_HP_PROCONOTP03 (DMU_HP0_PROCON_OTP3)
/** \brief 10050, PFLASH Bank 0 OTP Protection Configuration 4 */
#define DMU_HP0_PROCON_OTP4 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP4*)0xF8050050u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_OTP4.
* To use register names with standard convension, please use DMU_HP0_PROCON_OTP4.
*/
#define DMU_HP_PROCONOTP04 (DMU_HP0_PROCON_OTP4)
/** \brief 10054, PFLASH Bank 0 OTP Protection Configuration 5 */
#define DMU_HP0_PROCON_OTP5 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP5*)0xF8050054u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_OTP5.
* To use register names with standard convension, please use DMU_HP0_PROCON_OTP5.
*/
#define DMU_HP_PROCONOTP05 (DMU_HP0_PROCON_OTP5)
/** \brief 10080, PFLASH Bank 0 WOP Configuration 0 */
#define DMU_HP0_PROCON_WOP0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP0*)0xF8050080u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_WOP0.
* To use register names with standard convension, please use DMU_HP0_PROCON_WOP0.
*/
#define DMU_HP_PROCONWOP00 (DMU_HP0_PROCON_WOP0)
/** \brief 10084, PFLASH Bank 0 WOP Configuration 1 */
#define DMU_HP0_PROCON_WOP1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP1*)0xF8050084u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_WOP1.
* To use register names with standard convension, please use DMU_HP0_PROCON_WOP1.
*/
#define DMU_HP_PROCONWOP01 (DMU_HP0_PROCON_WOP1)
/** \brief 10088, PFLASH Bank 0 WOP Configuration 2 */
#define DMU_HP0_PROCON_WOP2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP2*)0xF8050088u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_WOP2.
* To use register names with standard convension, please use DMU_HP0_PROCON_WOP2.
*/
#define DMU_HP_PROCONWOP02 (DMU_HP0_PROCON_WOP2)
/** \brief 1008C, PFLASH Bank 0 WOP Configuration 3 */
#define DMU_HP0_PROCON_WOP3 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP3*)0xF805008Cu)
/** Alias (User Manual Name) for DMU_HP0_PROCON_WOP3.
* To use register names with standard convension, please use DMU_HP0_PROCON_WOP3.
*/
#define DMU_HP_PROCONWOP03 (DMU_HP0_PROCON_WOP3)
/** \brief 10090, PFLASH Bank 0 WOP Configuration 4 */
#define DMU_HP0_PROCON_WOP4 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP4*)0xF8050090u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_WOP4.
* To use register names with standard convension, please use DMU_HP0_PROCON_WOP4.
*/
#define DMU_HP_PROCONWOP04 (DMU_HP0_PROCON_WOP4)
/** \brief 10094, PFLASH Bank 0 WOP Configuration 5 */
#define DMU_HP0_PROCON_WOP5 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP5*)0xF8050094u)
/** Alias (User Manual Name) for DMU_HP0_PROCON_WOP5.
* To use register names with standard convension, please use DMU_HP0_PROCON_WOP5.
*/
#define DMU_HP_PROCONWOP05 (DMU_HP0_PROCON_WOP5)
/** \brief 100A0, PFLASH Bank 0 Erase Counter Priority configuration 0 */
#define DMU_HP0_ECPRIO_P0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P0*)0xF80500A0u)
/** Alias (User Manual Name) for DMU_HP0_ECPRIO_P0.
* To use register names with standard convension, please use DMU_HP0_ECPRIO_P0.
*/
#define DMU_HP_ECPRIO00 (DMU_HP0_ECPRIO_P0)
/** \brief 100A4, PFLASH Bank 0 Erase Counter Priority Configuration 1 */
#define DMU_HP0_ECPRIO_P1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P1*)0xF80500A4u)
/** Alias (User Manual Name) for DMU_HP0_ECPRIO_P1.
* To use register names with standard convension, please use DMU_HP0_ECPRIO_P1.
*/
#define DMU_HP_ECPRIO01 (DMU_HP0_ECPRIO_P1)
/** \brief 100A8, PFLASH Bank 0 Erase Counter Priority Configuration 2 */
#define DMU_HP0_ECPRIO_P2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P2*)0xF80500A8u)
/** Alias (User Manual Name) for DMU_HP0_ECPRIO_P2.
* To use register names with standard convension, please use DMU_HP0_ECPRIO_P2.
*/
#define DMU_HP_ECPRIO02 (DMU_HP0_ECPRIO_P2)
/** \brief 100AC, PFLASH Bank 0 Erase Counter Priority Configuration 3 */
#define DMU_HP0_ECPRIO_P3 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P3*)0xF80500ACu)
/** Alias (User Manual Name) for DMU_HP0_ECPRIO_P3.
* To use register names with standard convension, please use DMU_HP0_ECPRIO_P3.
*/
#define DMU_HP_ECPRIO03 (DMU_HP0_ECPRIO_P3)
/** \brief 100B0, PFLASH Bank 0 Erase Counter Priority Configuration 4 */
#define DMU_HP0_ECPRIO_P4 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P4*)0xF80500B0u)
/** Alias (User Manual Name) for DMU_HP0_ECPRIO_P4.
* To use register names with standard convension, please use DMU_HP0_ECPRIO_P4.
*/
#define DMU_HP_ECPRIO04 (DMU_HP0_ECPRIO_P4)
/** \brief 100B4, PFLASH Bank 0 Erase Counter Priority Configuration 5 */
#define DMU_HP0_ECPRIO_P5 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P5*)0xF80500B4u)
/** Alias (User Manual Name) for DMU_HP0_ECPRIO_P5.
* To use register names with standard convension, please use DMU_HP0_ECPRIO_P5.
*/
#define DMU_HP_ECPRIO05 (DMU_HP0_ECPRIO_P5)
/** \brief 10100, PFLASH Bank 1 Protection Configuration 0 */
#define DMU_HP1_PROCON_P0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P0*)0xF8050100u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_P0.
* To use register names with standard convension, please use DMU_HP1_PROCON_P0.
*/
#define DMU_HP_PROCONP10 (DMU_HP1_PROCON_P0)
/** \brief 10104, PFLASH Bank 1 Protection Configuration 1 */
#define DMU_HP1_PROCON_P1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P1*)0xF8050104u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_P1.
* To use register names with standard convension, please use DMU_HP1_PROCON_P1.
*/
#define DMU_HP_PROCONP11 (DMU_HP1_PROCON_P1)
/** \brief 10108, PFLASH Bank 1 Protection Configuration 2 */
#define DMU_HP1_PROCON_P2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P2*)0xF8050108u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_P2.
* To use register names with standard convension, please use DMU_HP1_PROCON_P2.
*/
#define DMU_HP_PROCONP12 (DMU_HP1_PROCON_P2)
/** \brief 1010C, PFLASH Bank 1 Protection Configuration 3 */
#define DMU_HP1_PROCON_P3 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P3*)0xF805010Cu)
/** Alias (User Manual Name) for DMU_HP1_PROCON_P3.
* To use register names with standard convension, please use DMU_HP1_PROCON_P3.
*/
#define DMU_HP_PROCONP13 (DMU_HP1_PROCON_P3)
/** \brief 10110, PFLASH Bank 1 Protection Configuration 4 */
#define DMU_HP1_PROCON_P4 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P4*)0xF8050110u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_P4.
* To use register names with standard convension, please use DMU_HP1_PROCON_P4.
*/
#define DMU_HP_PROCONP14 (DMU_HP1_PROCON_P4)
/** \brief 10114, PFLASH Bank 1 Protection Configuration 5 */
#define DMU_HP1_PROCON_P5 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_P5*)0xF8050114u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_P5.
* To use register names with standard convension, please use DMU_HP1_PROCON_P5.
*/
#define DMU_HP_PROCONP15 (DMU_HP1_PROCON_P5)
/** \brief 10140, PFLASH Bank 1 OTP Protection Configuration 0 */
#define DMU_HP1_PROCON_OTP0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP0*)0xF8050140u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_OTP0.
* To use register names with standard convension, please use DMU_HP1_PROCON_OTP0.
*/
#define DMU_HP_PROCONOTP10 (DMU_HP1_PROCON_OTP0)
/** \brief 10144, PFLASH Bank 1 OTP Protection Configuration 1 */
#define DMU_HP1_PROCON_OTP1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP1*)0xF8050144u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_OTP1.
* To use register names with standard convension, please use DMU_HP1_PROCON_OTP1.
*/
#define DMU_HP_PROCONOTP11 (DMU_HP1_PROCON_OTP1)
/** \brief 10148, PFLASH Bank 1 OTP Protection Configuration 2 */
#define DMU_HP1_PROCON_OTP2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP2*)0xF8050148u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_OTP2.
* To use register names with standard convension, please use DMU_HP1_PROCON_OTP2.
*/
#define DMU_HP_PROCONOTP12 (DMU_HP1_PROCON_OTP2)
/** \brief 1014C, PFLASH Bank 1 OTP Protection Configuration 3 */
#define DMU_HP1_PROCON_OTP3 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP3*)0xF805014Cu)
/** Alias (User Manual Name) for DMU_HP1_PROCON_OTP3.
* To use register names with standard convension, please use DMU_HP1_PROCON_OTP3.
*/
#define DMU_HP_PROCONOTP13 (DMU_HP1_PROCON_OTP3)
/** \brief 10150, PFLASH Bank 1 OTP Protection Configuration 4 */
#define DMU_HP1_PROCON_OTP4 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP4*)0xF8050150u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_OTP4.
* To use register names with standard convension, please use DMU_HP1_PROCON_OTP4.
*/
#define DMU_HP_PROCONOTP14 (DMU_HP1_PROCON_OTP4)
/** \brief 10154, PFLASH Bank 1 OTP Protection Configuration 5 */
#define DMU_HP1_PROCON_OTP5 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_OTP5*)0xF8050154u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_OTP5.
* To use register names with standard convension, please use DMU_HP1_PROCON_OTP5.
*/
#define DMU_HP_PROCONOTP15 (DMU_HP1_PROCON_OTP5)
/** \brief 10180, PFLASH Bank 1 WOP Configuration 0 */
#define DMU_HP1_PROCON_WOP0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP0*)0xF8050180u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_WOP0.
* To use register names with standard convension, please use DMU_HP1_PROCON_WOP0.
*/
#define DMU_HP_PROCONWOP10 (DMU_HP1_PROCON_WOP0)
/** \brief 10184, PFLASH Bank 1 WOP Configuration 1 */
#define DMU_HP1_PROCON_WOP1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP1*)0xF8050184u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_WOP1.
* To use register names with standard convension, please use DMU_HP1_PROCON_WOP1.
*/
#define DMU_HP_PROCONWOP11 (DMU_HP1_PROCON_WOP1)
/** \brief 10188, PFLASH Bank 1 WOP Configuration 2 */
#define DMU_HP1_PROCON_WOP2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP2*)0xF8050188u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_WOP2.
* To use register names with standard convension, please use DMU_HP1_PROCON_WOP2.
*/
#define DMU_HP_PROCONWOP12 (DMU_HP1_PROCON_WOP2)
/** \brief 1018C, PFLASH Bank 1 WOP Configuration 3 */
#define DMU_HP1_PROCON_WOP3 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP3*)0xF805018Cu)
/** Alias (User Manual Name) for DMU_HP1_PROCON_WOP3.
* To use register names with standard convension, please use DMU_HP1_PROCON_WOP3.
*/
#define DMU_HP_PROCONWOP13 (DMU_HP1_PROCON_WOP3)
/** \brief 10190, PFLASH Bank 1 WOP Configuration 4 */
#define DMU_HP1_PROCON_WOP4 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP4*)0xF8050190u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_WOP4.
* To use register names with standard convension, please use DMU_HP1_PROCON_WOP4.
*/
#define DMU_HP_PROCONWOP14 (DMU_HP1_PROCON_WOP4)
/** \brief 10194, PFLASH Bank 1 WOP Configuration 5 */
#define DMU_HP1_PROCON_WOP5 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_PROCON_WOP5*)0xF8050194u)
/** Alias (User Manual Name) for DMU_HP1_PROCON_WOP5.
* To use register names with standard convension, please use DMU_HP1_PROCON_WOP5.
*/
#define DMU_HP_PROCONWOP15 (DMU_HP1_PROCON_WOP5)
/** \brief 101A0, PFLASH Bank 1 Erase Counter Priority configuration 0 */
#define DMU_HP1_ECPRIO_P0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P0*)0xF80501A0u)
/** Alias (User Manual Name) for DMU_HP1_ECPRIO_P0.
* To use register names with standard convension, please use DMU_HP1_ECPRIO_P0.
*/
#define DMU_HP_ECPRIO10 (DMU_HP1_ECPRIO_P0)
/** \brief 101A4, PFLASH Bank 1 Erase Counter Priority Configuration 1 */
#define DMU_HP1_ECPRIO_P1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P1*)0xF80501A4u)
/** Alias (User Manual Name) for DMU_HP1_ECPRIO_P1.
* To use register names with standard convension, please use DMU_HP1_ECPRIO_P1.
*/
#define DMU_HP_ECPRIO11 (DMU_HP1_ECPRIO_P1)
/** \brief 101A8, PFLASH Bank 1 Erase Counter Priority Configuration 2 */
#define DMU_HP1_ECPRIO_P2 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P2*)0xF80501A8u)
/** Alias (User Manual Name) for DMU_HP1_ECPRIO_P2.
* To use register names with standard convension, please use DMU_HP1_ECPRIO_P2.
*/
#define DMU_HP_ECPRIO12 (DMU_HP1_ECPRIO_P2)
/** \brief 101AC, PFLASH Bank 1 Erase Counter Priority Configuration 3 */
#define DMU_HP1_ECPRIO_P3 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P3*)0xF80501ACu)
/** Alias (User Manual Name) for DMU_HP1_ECPRIO_P3.
* To use register names with standard convension, please use DMU_HP1_ECPRIO_P3.
*/
#define DMU_HP_ECPRIO13 (DMU_HP1_ECPRIO_P3)
/** \brief 101B0, PFLASH Bank 1 Erase Counter Priority Configuration 4 */
#define DMU_HP1_ECPRIO_P4 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P4*)0xF80501B0u)
/** Alias (User Manual Name) for DMU_HP1_ECPRIO_P4.
* To use register names with standard convension, please use DMU_HP1_ECPRIO_P4.
*/
#define DMU_HP_ECPRIO14 (DMU_HP1_ECPRIO_P4)
/** \brief 101B4, PFLASH Bank 1 Erase Counter Priority Configuration 5 */
#define DMU_HP1_ECPRIO_P5 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_HP_ECPRIO_P5*)0xF80501B4u)
/** Alias (User Manual Name) for DMU_HP1_ECPRIO_P5.
* To use register names with standard convension, please use DMU_HP1_ECPRIO_P5.
*/
#define DMU_HP_ECPRIO15 (DMU_HP1_ECPRIO_P5)
/** \brief 20010, HSM Flash Status Register */
#define DMU_SF_STATUS /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_STATUS*)0xF8060010u)
/** \brief 20014, HSM Flash Configuration Register */
#define DMU_SF_CONTROL /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_CONTROL*)0xF8060014u)
/** \brief 20018, HSM Flash Operation Register */
#define DMU_SF_OPERATION /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_OPERATION*)0xF8060018u)
/** \brief 20030, HSM Enable Error Interrupt Control Register */
#define DMU_SF_EER /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_EER*)0xF8060030u)
/** \brief 20034, HSM Error Status Register */
#define DMU_SF_ERRSR /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_ERRSR*)0xF8060034u)
/** \brief 20038, HSM Clear Error Register */
#define DMU_SF_CLRE /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_CLRE*)0xF8060038u)
/** \brief 20040, HSM DF1 ECC Read Register */
#define DMU_SF_ECCR /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_ECCR*)0xF8060040u)
/** \brief 20044, HSM DF1 ECC Status Register */
#define DMU_SF_ECCS /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_ECCS*)0xF8060044u)
/** \brief 20048, HSM DF1 ECC Control Register */
#define DMU_SF_ECCC /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_ECCC*)0xF8060048u)
/** \brief 2004C, HSM DF1 ECC Write Register */
#define DMU_SF_ECCW /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_ECCW*)0xF806004Cu)
/** \brief 20074, HSM DF1 User Mode Control */
#define DMU_SF_PROCONUSR /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_PROCONUSR*)0xF8060074u)
/** \brief 200E8, HSM Suspend Control Register */
#define DMU_SF_SUSPEND /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_SUSPEND*)0xF80600E8u)
/** \brief 200EC, HSM DF1 Margin Control Register */
#define DMU_SF_MARGIN /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SF_MARGIN*)0xF80600ECu)
/** \brief 30000, HSM Protection Configuration */
#define DMU_SP_PROCONHSMCFG /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SP_PROCONHSMCFG*)0xF8070000u)
/** \brief 30004, HSM Code Boot Sector */
#define DMU_SP_PROCONHSMCBS /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SP_PROCONHSMCBS*)0xF8070004u)
/** \brief 30008, HSM Code Exclusive Protection Configuration */
#define DMU_SP_PROCONHSMCX0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SP_PROCONHSMCX0*)0xF8070008u)
/** \brief 3000C, HSM Code Exclusive Protection Configuration */
#define DMU_SP_PROCONHSMCX1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SP_PROCONHSMCX1*)0xF807000Cu)
/** \brief 30010, HSM Code OTP Protection Configuration */
#define DMU_SP_PROCONHSMCOTP0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SP_PROCONHSMCOTP0*)0xF8070010u)
/** \brief 30014, HSM Code OTP Protection Configuration */
#define DMU_SP_PROCONHSMCOTP1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SP_PROCONHSMCOTP1*)0xF8070014u)
/** \brief 30040, HSM Interface Protection Configuration */
#define DMU_SP_PROCONHSM /*lint --e(923, 9078)*/ (*(volatile Ifx_DMU_SP_PROCONHSM*)0xF8070040u)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXDMU_REG_H */

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/**
* \file IfxDom_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Dom_Registers_Cfg Dom address
* \ingroup IfxSfr_Dom_Registers
*
* \defgroup IfxSfr_Dom_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Dom_Registers_Cfg
*
* \defgroup IfxSfr_Dom_Registers_Cfg_Dom0 2-DOM0
* \ingroup IfxSfr_Dom_Registers_Cfg
*
*
*/
#ifndef IFXDOM_REG_H
#define IFXDOM_REG_H 1
/******************************************************************************/
#include "IfxDom_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dom_Registers_Cfg_BaseAddress
* \{ */
/** \brief DOM object */
#define MODULE_DOM0 /*lint --e(923, 9078)*/ ((*(Ifx_DOM*)0xF8700000u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dom_Registers_Cfg_Dom0
* \{ */
/** \brief 0, Protocol Error Control Register 0 */
#define DOM0_SCICTRL0_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700000u)
/** Alias (User Manual Name) for DOM0_SCICTRL0_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL0_PECON.
*/
#define DOM0_PECON0 (DOM0_SCICTRL0_PECON)
/** \brief 8, SCI0 Arbiter Priority Register */
#define DOM0_SCICTRL0_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700008u)
/** Alias (User Manual Name) for DOM0_SCICTRL0_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL0_PRIORITY.
*/
#define DOM0_PRIORITY0 (DOM0_SCICTRL0_PRIORITY)
/** \brief 10, SCI 0 Error Address Capture Register */
#define DOM0_SCICTRL0_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700010u)
/** Alias (User Manual Name) for DOM0_SCICTRL0_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL0_ERRADDR.
*/
#define DOM0_ERRADDR0 (DOM0_SCICTRL0_ERRADDR)
/** \brief 18, SCI 0 Error Capture Register */
#define DOM0_SCICTRL0_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700018u)
/** Alias (User Manual Name) for DOM0_SCICTRL0_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL0_ERR.
*/
#define DOM0_ERR0 (DOM0_SCICTRL0_ERR)
/** \brief 20, Protocol Error Control Register 1 */
#define DOM0_SCICTRL1_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700020u)
/** Alias (User Manual Name) for DOM0_SCICTRL1_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL1_PECON.
*/
#define DOM0_PECON1 (DOM0_SCICTRL1_PECON)
/** \brief 28, SCI1 Arbiter Priority Register */
#define DOM0_SCICTRL1_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700028u)
/** Alias (User Manual Name) for DOM0_SCICTRL1_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL1_PRIORITY.
*/
#define DOM0_PRIORITY1 (DOM0_SCICTRL1_PRIORITY)
/** \brief 30, SCI 1 Error Address Capture Register */
#define DOM0_SCICTRL1_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700030u)
/** Alias (User Manual Name) for DOM0_SCICTRL1_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL1_ERRADDR.
*/
#define DOM0_ERRADDR1 (DOM0_SCICTRL1_ERRADDR)
/** \brief 38, SCI 1 Error Capture Register */
#define DOM0_SCICTRL1_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700038u)
/** Alias (User Manual Name) for DOM0_SCICTRL1_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL1_ERR.
*/
#define DOM0_ERR1 (DOM0_SCICTRL1_ERR)
/** \brief 40, Protocol Error Control Register 2 */
#define DOM0_SCICTRL2_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700040u)
/** Alias (User Manual Name) for DOM0_SCICTRL2_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL2_PECON.
*/
#define DOM0_PECON2 (DOM0_SCICTRL2_PECON)
/** \brief 48, SCI2 Arbiter Priority Register */
#define DOM0_SCICTRL2_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700048u)
/** Alias (User Manual Name) for DOM0_SCICTRL2_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL2_PRIORITY.
*/
#define DOM0_PRIORITY2 (DOM0_SCICTRL2_PRIORITY)
/** \brief 50, SCI 2 Error Address Capture Register */
#define DOM0_SCICTRL2_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700050u)
/** Alias (User Manual Name) for DOM0_SCICTRL2_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL2_ERRADDR.
*/
#define DOM0_ERRADDR2 (DOM0_SCICTRL2_ERRADDR)
/** \brief 58, SCI 2 Error Capture Register */
#define DOM0_SCICTRL2_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700058u)
/** Alias (User Manual Name) for DOM0_SCICTRL2_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL2_ERR.
*/
#define DOM0_ERR2 (DOM0_SCICTRL2_ERR)
/** \brief 60, Protocol Error Control Register 3 */
#define DOM0_SCICTRL3_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700060u)
/** Alias (User Manual Name) for DOM0_SCICTRL3_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL3_PECON.
*/
#define DOM0_PECON3 (DOM0_SCICTRL3_PECON)
/** \brief 68, SCI3 Arbiter Priority Register */
#define DOM0_SCICTRL3_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700068u)
/** Alias (User Manual Name) for DOM0_SCICTRL3_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL3_PRIORITY.
*/
#define DOM0_PRIORITY3 (DOM0_SCICTRL3_PRIORITY)
/** \brief 70, SCI 3 Error Address Capture Register */
#define DOM0_SCICTRL3_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700070u)
/** Alias (User Manual Name) for DOM0_SCICTRL3_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL3_ERRADDR.
*/
#define DOM0_ERRADDR3 (DOM0_SCICTRL3_ERRADDR)
/** \brief 78, SCI 3 Error Capture Register */
#define DOM0_SCICTRL3_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700078u)
/** Alias (User Manual Name) for DOM0_SCICTRL3_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL3_ERR.
*/
#define DOM0_ERR3 (DOM0_SCICTRL3_ERR)
/** \brief 80, Protocol Error Control Register 4 */
#define DOM0_SCICTRL4_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700080u)
/** Alias (User Manual Name) for DOM0_SCICTRL4_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL4_PECON.
*/
#define DOM0_PECON4 (DOM0_SCICTRL4_PECON)
/** \brief 88, SCI4 Arbiter Priority Register */
#define DOM0_SCICTRL4_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700088u)
/** Alias (User Manual Name) for DOM0_SCICTRL4_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL4_PRIORITY.
*/
#define DOM0_PRIORITY4 (DOM0_SCICTRL4_PRIORITY)
/** \brief 90, SCI 4 Error Address Capture Register */
#define DOM0_SCICTRL4_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700090u)
/** Alias (User Manual Name) for DOM0_SCICTRL4_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL4_ERRADDR.
*/
#define DOM0_ERRADDR4 (DOM0_SCICTRL4_ERRADDR)
/** \brief 98, SCI 4 Error Capture Register */
#define DOM0_SCICTRL4_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700098u)
/** Alias (User Manual Name) for DOM0_SCICTRL4_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL4_ERR.
*/
#define DOM0_ERR4 (DOM0_SCICTRL4_ERR)
/** \brief A0, Protocol Error Control Register 5 */
#define DOM0_SCICTRL5_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF87000A0u)
/** Alias (User Manual Name) for DOM0_SCICTRL5_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL5_PECON.
*/
#define DOM0_PECON5 (DOM0_SCICTRL5_PECON)
/** \brief A8, SCI5 Arbiter Priority Register */
#define DOM0_SCICTRL5_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF87000A8u)
/** Alias (User Manual Name) for DOM0_SCICTRL5_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL5_PRIORITY.
*/
#define DOM0_PRIORITY5 (DOM0_SCICTRL5_PRIORITY)
/** \brief B0, SCI 5 Error Address Capture Register */
#define DOM0_SCICTRL5_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF87000B0u)
/** Alias (User Manual Name) for DOM0_SCICTRL5_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL5_ERRADDR.
*/
#define DOM0_ERRADDR5 (DOM0_SCICTRL5_ERRADDR)
/** \brief B8, SCI 5 Error Capture Register */
#define DOM0_SCICTRL5_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF87000B8u)
/** Alias (User Manual Name) for DOM0_SCICTRL5_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL5_ERR.
*/
#define DOM0_ERR5 (DOM0_SCICTRL5_ERR)
/** \brief C0, Protocol Error Control Register 6 */
#define DOM0_SCICTRL6_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF87000C0u)
/** Alias (User Manual Name) for DOM0_SCICTRL6_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL6_PECON.
*/
#define DOM0_PECON6 (DOM0_SCICTRL6_PECON)
/** \brief C8, SCI6 Arbiter Priority Register */
#define DOM0_SCICTRL6_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF87000C8u)
/** Alias (User Manual Name) for DOM0_SCICTRL6_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL6_PRIORITY.
*/
#define DOM0_PRIORITY6 (DOM0_SCICTRL6_PRIORITY)
/** \brief D0, SCI 6 Error Address Capture Register */
#define DOM0_SCICTRL6_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF87000D0u)
/** Alias (User Manual Name) for DOM0_SCICTRL6_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL6_ERRADDR.
*/
#define DOM0_ERRADDR6 (DOM0_SCICTRL6_ERRADDR)
/** \brief D8, SCI 6 Error Capture Register */
#define DOM0_SCICTRL6_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF87000D8u)
/** Alias (User Manual Name) for DOM0_SCICTRL6_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL6_ERR.
*/
#define DOM0_ERR6 (DOM0_SCICTRL6_ERR)
/** \brief E0, Protocol Error Control Register 7 */
#define DOM0_SCICTRL7_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF87000E0u)
/** Alias (User Manual Name) for DOM0_SCICTRL7_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL7_PECON.
*/
#define DOM0_PECON7 (DOM0_SCICTRL7_PECON)
/** \brief E8, SCI7 Arbiter Priority Register */
#define DOM0_SCICTRL7_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF87000E8u)
/** Alias (User Manual Name) for DOM0_SCICTRL7_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL7_PRIORITY.
*/
#define DOM0_PRIORITY7 (DOM0_SCICTRL7_PRIORITY)
/** \brief F0, SCI 7 Error Address Capture Register */
#define DOM0_SCICTRL7_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF87000F0u)
/** Alias (User Manual Name) for DOM0_SCICTRL7_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL7_ERRADDR.
*/
#define DOM0_ERRADDR7 (DOM0_SCICTRL7_ERRADDR)
/** \brief F8, SCI 7 Error Capture Register */
#define DOM0_SCICTRL7_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF87000F8u)
/** Alias (User Manual Name) for DOM0_SCICTRL7_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL7_ERR.
*/
#define DOM0_ERR7 (DOM0_SCICTRL7_ERR)
/** \brief 100, Protocol Error Control Register 8 */
#define DOM0_SCICTRL8_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700100u)
/** Alias (User Manual Name) for DOM0_SCICTRL8_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL8_PECON.
*/
#define DOM0_PECON8 (DOM0_SCICTRL8_PECON)
/** \brief 108, SCI8 Arbiter Priority Register */
#define DOM0_SCICTRL8_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700108u)
/** Alias (User Manual Name) for DOM0_SCICTRL8_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL8_PRIORITY.
*/
#define DOM0_PRIORITY8 (DOM0_SCICTRL8_PRIORITY)
/** \brief 110, SCI 8 Error Address Capture Register */
#define DOM0_SCICTRL8_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700110u)
/** Alias (User Manual Name) for DOM0_SCICTRL8_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL8_ERRADDR.
*/
#define DOM0_ERRADDR8 (DOM0_SCICTRL8_ERRADDR)
/** \brief 118, SCI 8 Error Capture Register */
#define DOM0_SCICTRL8_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700118u)
/** Alias (User Manual Name) for DOM0_SCICTRL8_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL8_ERR.
*/
#define DOM0_ERR8 (DOM0_SCICTRL8_ERR)
/** \brief 120, Protocol Error Control Register 9 */
#define DOM0_SCICTRL9_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700120u)
/** Alias (User Manual Name) for DOM0_SCICTRL9_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL9_PECON.
*/
#define DOM0_PECON9 (DOM0_SCICTRL9_PECON)
/** \brief 128, SCI9 Arbiter Priority Register */
#define DOM0_SCICTRL9_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700128u)
/** Alias (User Manual Name) for DOM0_SCICTRL9_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL9_PRIORITY.
*/
#define DOM0_PRIORITY9 (DOM0_SCICTRL9_PRIORITY)
/** \brief 130, SCI 9 Error Address Capture Register */
#define DOM0_SCICTRL9_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700130u)
/** Alias (User Manual Name) for DOM0_SCICTRL9_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL9_ERRADDR.
*/
#define DOM0_ERRADDR9 (DOM0_SCICTRL9_ERRADDR)
/** \brief 138, SCI 9 Error Capture Register */
#define DOM0_SCICTRL9_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700138u)
/** Alias (User Manual Name) for DOM0_SCICTRL9_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL9_ERR.
*/
#define DOM0_ERR9 (DOM0_SCICTRL9_ERR)
/** \brief 140, Protocol Error Control Register 10 */
#define DOM0_SCICTRL10_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700140u)
/** Alias (User Manual Name) for DOM0_SCICTRL10_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL10_PECON.
*/
#define DOM0_PECON10 (DOM0_SCICTRL10_PECON)
/** \brief 148, SCI10 Arbiter Priority Register */
#define DOM0_SCICTRL10_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700148u)
/** Alias (User Manual Name) for DOM0_SCICTRL10_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL10_PRIORITY.
*/
#define DOM0_PRIORITY10 (DOM0_SCICTRL10_PRIORITY)
/** \brief 150, SCI 10 Error Address Capture Register */
#define DOM0_SCICTRL10_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700150u)
/** Alias (User Manual Name) for DOM0_SCICTRL10_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL10_ERRADDR.
*/
#define DOM0_ERRADDR10 (DOM0_SCICTRL10_ERRADDR)
/** \brief 158, SCI 10 Error Capture Register */
#define DOM0_SCICTRL10_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700158u)
/** Alias (User Manual Name) for DOM0_SCICTRL10_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL10_ERR.
*/
#define DOM0_ERR10 (DOM0_SCICTRL10_ERR)
/** \brief 160, Protocol Error Control Register 11 */
#define DOM0_SCICTRL11_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700160u)
/** Alias (User Manual Name) for DOM0_SCICTRL11_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL11_PECON.
*/
#define DOM0_PECON11 (DOM0_SCICTRL11_PECON)
/** \brief 168, SCI11 Arbiter Priority Register */
#define DOM0_SCICTRL11_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700168u)
/** Alias (User Manual Name) for DOM0_SCICTRL11_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL11_PRIORITY.
*/
#define DOM0_PRIORITY11 (DOM0_SCICTRL11_PRIORITY)
/** \brief 170, SCI 11 Error Address Capture Register */
#define DOM0_SCICTRL11_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700170u)
/** Alias (User Manual Name) for DOM0_SCICTRL11_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL11_ERRADDR.
*/
#define DOM0_ERRADDR11 (DOM0_SCICTRL11_ERRADDR)
/** \brief 178, SCI 11 Error Capture Register */
#define DOM0_SCICTRL11_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700178u)
/** Alias (User Manual Name) for DOM0_SCICTRL11_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL11_ERR.
*/
#define DOM0_ERR11 (DOM0_SCICTRL11_ERR)
/** \brief 180, Protocol Error Control Register 12 */
#define DOM0_SCICTRL12_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF8700180u)
/** Alias (User Manual Name) for DOM0_SCICTRL12_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL12_PECON.
*/
#define DOM0_PECON12 (DOM0_SCICTRL12_PECON)
/** \brief 188, SCI12 Arbiter Priority Register */
#define DOM0_SCICTRL12_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF8700188u)
/** Alias (User Manual Name) for DOM0_SCICTRL12_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL12_PRIORITY.
*/
#define DOM0_PRIORITY12 (DOM0_SCICTRL12_PRIORITY)
/** \brief 190, SCI 12 Error Address Capture Register */
#define DOM0_SCICTRL12_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF8700190u)
/** Alias (User Manual Name) for DOM0_SCICTRL12_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL12_ERRADDR.
*/
#define DOM0_ERRADDR12 (DOM0_SCICTRL12_ERRADDR)
/** \brief 198, SCI 12 Error Capture Register */
#define DOM0_SCICTRL12_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF8700198u)
/** Alias (User Manual Name) for DOM0_SCICTRL12_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL12_ERR.
*/
#define DOM0_ERR12 (DOM0_SCICTRL12_ERR)
/** \brief 1A0, Protocol Error Control Register 13 */
#define DOM0_SCICTRL13_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF87001A0u)
/** Alias (User Manual Name) for DOM0_SCICTRL13_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL13_PECON.
*/
#define DOM0_PECON13 (DOM0_SCICTRL13_PECON)
/** \brief 1A8, SCI13 Arbiter Priority Register */
#define DOM0_SCICTRL13_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF87001A8u)
/** Alias (User Manual Name) for DOM0_SCICTRL13_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL13_PRIORITY.
*/
#define DOM0_PRIORITY13 (DOM0_SCICTRL13_PRIORITY)
/** \brief 1B0, SCI 13 Error Address Capture Register */
#define DOM0_SCICTRL13_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF87001B0u)
/** Alias (User Manual Name) for DOM0_SCICTRL13_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL13_ERRADDR.
*/
#define DOM0_ERRADDR13 (DOM0_SCICTRL13_ERRADDR)
/** \brief 1B8, SCI 13 Error Capture Register */
#define DOM0_SCICTRL13_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF87001B8u)
/** Alias (User Manual Name) for DOM0_SCICTRL13_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL13_ERR.
*/
#define DOM0_ERR13 (DOM0_SCICTRL13_ERR)
/** \brief 1C0, Protocol Error Control Register 14 */
#define DOM0_SCICTRL14_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF87001C0u)
/** Alias (User Manual Name) for DOM0_SCICTRL14_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL14_PECON.
*/
#define DOM0_PECON14 (DOM0_SCICTRL14_PECON)
/** \brief 1C8, SCI14 Arbiter Priority Register */
#define DOM0_SCICTRL14_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF87001C8u)
/** Alias (User Manual Name) for DOM0_SCICTRL14_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL14_PRIORITY.
*/
#define DOM0_PRIORITY14 (DOM0_SCICTRL14_PRIORITY)
/** \brief 1D0, SCI 14 Error Address Capture Register */
#define DOM0_SCICTRL14_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF87001D0u)
/** Alias (User Manual Name) for DOM0_SCICTRL14_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL14_ERRADDR.
*/
#define DOM0_ERRADDR14 (DOM0_SCICTRL14_ERRADDR)
/** \brief 1D8, SCI 14 Error Capture Register */
#define DOM0_SCICTRL14_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF87001D8u)
/** Alias (User Manual Name) for DOM0_SCICTRL14_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL14_ERR.
*/
#define DOM0_ERR14 (DOM0_SCICTRL14_ERR)
/** \brief 1E0, Protocol Error Control Register 15 */
#define DOM0_SCICTRL15_PECON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PECON*)0xF87001E0u)
/** Alias (User Manual Name) for DOM0_SCICTRL15_PECON.
* To use register names with standard convension, please use DOM0_SCICTRL15_PECON.
*/
#define DOM0_PECON15 (DOM0_SCICTRL15_PECON)
/** \brief 1E8, SCI15 Arbiter Priority Register */
#define DOM0_SCICTRL15_PRIORITY /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_PRIORITY*)0xF87001E8u)
/** Alias (User Manual Name) for DOM0_SCICTRL15_PRIORITY.
* To use register names with standard convension, please use DOM0_SCICTRL15_PRIORITY.
*/
#define DOM0_PRIORITY15 (DOM0_SCICTRL15_PRIORITY)
/** \brief 1F0, SCI 15 Error Address Capture Register */
#define DOM0_SCICTRL15_ERRADDR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERRADDR*)0xF87001F0u)
/** Alias (User Manual Name) for DOM0_SCICTRL15_ERRADDR.
* To use register names with standard convension, please use DOM0_SCICTRL15_ERRADDR.
*/
#define DOM0_ERRADDR15 (DOM0_SCICTRL15_ERRADDR)
/** \brief 1F8, SCI 15 Error Capture Register */
#define DOM0_SCICTRL15_ERR /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_SCICTRL_ERR*)0xF87001F8u)
/** Alias (User Manual Name) for DOM0_SCICTRL15_ERR.
* To use register names with standard convension, please use DOM0_SCICTRL15_ERR.
*/
#define DOM0_ERR15 (DOM0_SCICTRL15_ERR)
/** \brief 408, Identification Register */
#define DOM0_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_ID*)0xF8700408u)
/** \brief 410, Protocol Error Status Register */
#define DOM0_PESTAT /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_PESTAT*)0xF8700410u)
/** \brief 418, Transaction ID Status Register */
#define DOM0_TIDSTAT /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_TIDSTAT*)0xF8700418u)
/** \brief 420, Transaction ID Enable Register */
#define DOM0_TIDEN /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_TIDEN*)0xF8700420u)
/** \brief 430, Domain 0 Bridge Control Register */
#define DOM0_BRCON /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_BRCON*)0xF8700430u)
/** \brief 4F0, Access Enable Register 0 */
#define DOM0_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_ACCEN0*)0xF87004F0u)
/** \brief 4F8, Access Enable Register 1 */
#define DOM0_ACCEN1 /*lint --e(923, 9078)*/ (*(volatile Ifx_DOM_ACCEN1*)0xF87004F8u)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXDOM_REG_H */

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/**
* \file IfxDom_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Dom_Registers Dom Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Dom_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Dom_Registers
*
* \defgroup IfxSfr_Dom_Registers_union Register unions
* \ingroup IfxSfr_Dom_Registers
*
* \defgroup IfxSfr_Dom_Registers_struct Memory map
* \ingroup IfxSfr_Dom_Registers
*/
#ifndef IFXDOM_REGDEF_H
#define IFXDOM_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dom_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_DOM_ACCEN0_Bits
{
Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_DOM_ACCEN0_Bits;
/** \brief Access Enable Register 1 */
typedef struct _Ifx_DOM_ACCEN1_Bits
{
Ifx_Strict_32Bit reserved_0:32; /**< \brief [31:0] \internal Reserved */
} Ifx_DOM_ACCEN1_Bits;
/** \brief Bridge Control Register */
typedef struct _Ifx_DOM_BRCON_Bits
{
Ifx_Strict_32Bit OLDAEN:1; /**< \brief [0:0] Online Data Acquisition Enable - OLDAEN (rw) */
Ifx_Strict_32Bit reserved_1:5; /**< \brief [5:1] \internal Reserved */
Ifx_Strict_32Bit reserved_6:1; /**< \brief [6:6] \internal Reserved */
Ifx_Strict_32Bit reserved_7:2; /**< \brief [8:7] \internal Reserved */
Ifx_Strict_32Bit reserved_9:2; /**< \brief [10:9] \internal Reserved */
Ifx_Strict_32Bit reserved_11:2; /**< \brief [12:11] \internal Reserved */
Ifx_Strict_32Bit reserved_13:7; /**< \brief [19:13] \internal Reserved */
Ifx_Strict_32Bit reserved_20:12; /**< \brief [31:20] \internal Reserved */
} Ifx_DOM_BRCON_Bits;
/** \brief Identification Register */
typedef struct _Ifx_DOM_ID_Bits
{
Ifx_Strict_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number - MOD_REV (r) */
Ifx_Strict_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Type - MOD_TYPE (r) */
Ifx_Strict_32Bit MOD_NUMBER:16; /**< \brief [31:16] Module Number Value - MOD_NUMBER (r) */
} Ifx_DOM_ID_Bits;
/** \brief Protocol Error Status Register */
typedef struct _Ifx_DOM_PESTAT_Bits
{
Ifx_Strict_32Bit reserved_0:16; /**< \brief [15:0] \internal Reserved */
Ifx_Strict_32Bit PESCI0:1; /**< \brief [16:16] Protocol Error status of SCI0 - PESCI0 (rwh) */
Ifx_Strict_32Bit PESCI1:1; /**< \brief [17:17] Protocol Error status of SCI1 - PESCI1 (rwh) */
Ifx_Strict_32Bit PESCI2:1; /**< \brief [18:18] Protocol Error status of SCI2 - PESCI2 (rwh) */
Ifx_Strict_32Bit PESCI3:1; /**< \brief [19:19] Protocol Error status of SCI3 - PESCI3 (rwh) */
Ifx_Strict_32Bit PESCI4:1; /**< \brief [20:20] Protocol Error status of SCI4 - PESCI4 (rwh) */
Ifx_Strict_32Bit PESCI5:1; /**< \brief [21:21] Protocol Error status of SCI5 - PESCI5 (rwh) */
Ifx_Strict_32Bit PESCI6:1; /**< \brief [22:22] Protocol Error status of SCI6 - PESCI6 (rwh) */
Ifx_Strict_32Bit PESCI7:1; /**< \brief [23:23] Protocol Error status of SCI7 - PESCI7 (rwh) */
Ifx_Strict_32Bit PESCI8:1; /**< \brief [24:24] Protocol Error status of SCI8 - PESCI8 (rwh) */
Ifx_Strict_32Bit PESCI9:1; /**< \brief [25:25] Protocol Error status of SCI9 - PESCI9 (rwh) */
Ifx_Strict_32Bit PESCI10:1; /**< \brief [26:26] Protocol Error status of SCI10 - PESCI10 (rwh) */
Ifx_Strict_32Bit PESCI11:1; /**< \brief [27:27] Protocol Error status of SCI11 - PESCI11 (rwh) */
Ifx_Strict_32Bit PESCI12:1; /**< \brief [28:28] Protocol Error status of SCI12 - PESCI12 (rwh) */
Ifx_Strict_32Bit PESCI13:1; /**< \brief [29:29] Protocol Error status of SCI13 - PESCI13 (rwh) */
Ifx_Strict_32Bit PESCI14:1; /**< \brief [30:30] Protocol Error status of SCI14 - PESCI14 (rwh) */
Ifx_Strict_32Bit PESCI15:1; /**< \brief [31:31] Protocol Error status of SCI15 - PESCI15 (rwh) */
} Ifx_DOM_PESTAT_Bits;
/** \brief SCI ${x} Error Capture Register */
typedef struct _Ifx_DOM_SCICTRL_ERR_Bits
{
Ifx_Strict_32Bit RD_N:1; /**< \brief [0:0] Read Status - RD (rh) */
Ifx_Strict_32Bit WR_N:1; /**< \brief [1:1] Write Status - WR (rh) */
Ifx_Strict_32Bit SVM:1; /**< \brief [2:2] Supervisor Mode Status - SVM (rh) */
Ifx_Strict_32Bit reserved_3:1; /**< \brief [3:3] \internal Reserved */
Ifx_Strict_32Bit OPC:4; /**< \brief [7:4] Operation Code - OPC (rh) */
Ifx_Strict_32Bit TR_ID:8; /**< \brief [15:8] Transaction ID - TR_ID (rh) */
Ifx_Strict_32Bit ADDR_EDC:8; /**< \brief [23:16] Address Phase Error Detection Information - ADDR_EDC (rh) */
Ifx_Strict_32Bit MCI_SBS:8; /**< \brief [31:24] MCI Sideband Signals [7:0] - MCI_SBS (rh) */
} Ifx_DOM_SCICTRL_ERR_Bits;
/** \brief SCI ${x} Error Address Capture Register */
typedef struct _Ifx_DOM_SCICTRL_ERRADDR_Bits
{
Ifx_Strict_32Bit ADDR:32; /**< \brief [31:0] Transaction Address - ADDR (rh) */
} Ifx_DOM_SCICTRL_ERRADDR_Bits;
/** \brief Protocol Error Control Register ${x} */
typedef struct _Ifx_DOM_SCICTRL_PECON_Bits
{
Ifx_Strict_32Bit PEEN:1; /**< \brief [0:0] Protocol Error Enable - PEEN (rw) */
Ifx_Strict_32Bit reserved_1:1; /**< \brief [1:1] \internal Reserved */
Ifx_Strict_32Bit SETPE:1; /**< \brief [2:2] Set Protocol Error - SETPE (rwh) */
Ifx_Strict_32Bit reserved_3:1; /**< \brief [3:3] \internal Reserved */
Ifx_Strict_32Bit PEACK:1; /**< \brief [4:4] Protocol Error Acknowledge - PEACK (rwh) */
Ifx_Strict_32Bit reserved_5:27; /**< \brief [31:5] \internal Reserved */
} Ifx_DOM_SCICTRL_PECON_Bits;
/** \brief SCI${x} Arbiter Priority Register */
typedef struct _Ifx_DOM_SCICTRL_PRIORITY_Bits
{
Ifx_Strict_32Bit MCI0_P:1; /**< \brief [0:0] MCI0 Priority - MCI0_P (rw) */
Ifx_Strict_32Bit MCI1_P:1; /**< \brief [1:1] MCI1 Priority - MCI1_P (rw) */
Ifx_Strict_32Bit MCI2_P:1; /**< \brief [2:2] MCI2 Priority - MCI2_P (rw) */
Ifx_Strict_32Bit MCI3_P:1; /**< \brief [3:3] MCI3 Priority - MCI3_P (rw) */
Ifx_Strict_32Bit MCI4_P:1; /**< \brief [4:4] MCI4 Priority - MCI4_P (rw) */
Ifx_Strict_32Bit MCI5_P:1; /**< \brief [5:5] MCI5 Priority - MCI5_P (rw) */
Ifx_Strict_32Bit MCI6_P:1; /**< \brief [6:6] MCI6 Priority - MCI6_P (rw) */
Ifx_Strict_32Bit MCI7_P:1; /**< \brief [7:7] MCI7 Priority - MCI7_P (rw) */
Ifx_Strict_32Bit MCI8_P:1; /**< \brief [8:8] MCI8 Priority - MCI8_P (rw) */
Ifx_Strict_32Bit MCI9_P:1; /**< \brief [9:9] MCI9 Priority - MCI9_P (rw) */
Ifx_Strict_32Bit MCI10_P:1; /**< \brief [10:10] MCI10 Priority - MCI10_P (rw) */
Ifx_Strict_32Bit MCI11_P:1; /**< \brief [11:11] MCI11 Priority - MCI11_P (rw) */
Ifx_Strict_32Bit reserved_12:4; /**< \brief [15:12] \internal Reserved */
Ifx_Strict_32Bit HPRS:3; /**< \brief [18:16] High Priority Round Share - HPRS (rw) */
Ifx_Strict_32Bit reserved_19:13; /**< \brief [31:19] \internal Reserved */
} Ifx_DOM_SCICTRL_PRIORITY_Bits;
/** \brief Transaction ID Enable Register */
typedef struct _Ifx_DOM_TIDEN_Bits
{
Ifx_Strict_32Bit ENSCI0:1; /**< \brief [0:0] E0able Transaction ID Error from SCIn - ENSCI0 (rw) */
Ifx_Strict_32Bit ENSCI1:1; /**< \brief [1:1] E1able Transaction ID Error from SCIn - ENSCI1 (rw) */
Ifx_Strict_32Bit ENSCI2:1; /**< \brief [2:2] E2able Transaction ID Error from SCIn - ENSCI2 (rw) */
Ifx_Strict_32Bit ENSCI3:1; /**< \brief [3:3] E3able Transaction ID Error from SCIn - ENSCI3 (rw) */
Ifx_Strict_32Bit ENSCI4:1; /**< \brief [4:4] E4able Transaction ID Error from SCIn - ENSCI4 (rw) */
Ifx_Strict_32Bit ENSCI5:1; /**< \brief [5:5] E5able Transaction ID Error from SCIn - ENSCI5 (rw) */
Ifx_Strict_32Bit ENSCI6:1; /**< \brief [6:6] E6able Transaction ID Error from SCIn - ENSCI6 (rw) */
Ifx_Strict_32Bit ENSCI7:1; /**< \brief [7:7] E7able Transaction ID Error from SCIn - ENSCI7 (rw) */
Ifx_Strict_32Bit ENSCI8:1; /**< \brief [8:8] E8able Transaction ID Error from SCIn - ENSCI8 (rw) */
Ifx_Strict_32Bit ENSCI9:1; /**< \brief [9:9] E9able Transaction ID Error from SCIn - ENSCI9 (rw) */
Ifx_Strict_32Bit ENSCI10:1; /**< \brief [10:10] E10able Transaction ID Error from SCIn - ENSCI10 (rw) */
Ifx_Strict_32Bit ENSCI11:1; /**< \brief [11:11] E11able Transaction ID Error from SCIn - ENSCI11 (rw) */
Ifx_Strict_32Bit ENSCI12:1; /**< \brief [12:12] E12able Transaction ID Error from SCIn - ENSCI12 (rw) */
Ifx_Strict_32Bit ENSCI13:1; /**< \brief [13:13] E13able Transaction ID Error from SCIn - ENSCI13 (rw) */
Ifx_Strict_32Bit ENSCI14:1; /**< \brief [14:14] E14able Transaction ID Error from SCIn - ENSCI14 (rw) */
Ifx_Strict_32Bit ENSCI15:1; /**< \brief [15:15] E15able Transaction ID Error from SCIn - ENSCI15 (rw) */
Ifx_Strict_32Bit ENMCI0:1; /**< \brief [16:16] E0able Transaction ID Error from MCIn - ENMCI0 (rw) */
Ifx_Strict_32Bit ENMCI1:1; /**< \brief [17:17] E1able Transaction ID Error from MCIn - ENMCI1 (rw) */
Ifx_Strict_32Bit ENMCI2:1; /**< \brief [18:18] E2able Transaction ID Error from MCIn - ENMCI2 (rw) */
Ifx_Strict_32Bit ENMCI3:1; /**< \brief [19:19] E3able Transaction ID Error from MCIn - ENMCI3 (rw) */
Ifx_Strict_32Bit ENMCI4:1; /**< \brief [20:20] E4able Transaction ID Error from MCIn - ENMCI4 (rw) */
Ifx_Strict_32Bit ENMCI5:1; /**< \brief [21:21] E5able Transaction ID Error from MCIn - ENMCI5 (rw) */
Ifx_Strict_32Bit ENMCI6:1; /**< \brief [22:22] E6able Transaction ID Error from MCIn - ENMCI6 (rw) */
Ifx_Strict_32Bit ENMCI7:1; /**< \brief [23:23] E7able Transaction ID Error from MCIn - ENMCI7 (rw) */
Ifx_Strict_32Bit ENMCI8:1; /**< \brief [24:24] E8able Transaction ID Error from MCIn - ENMCI8 (rw) */
Ifx_Strict_32Bit ENMCI9:1; /**< \brief [25:25] E9able Transaction ID Error from MCIn - ENMCI9 (rw) */
Ifx_Strict_32Bit ENMCI10:1; /**< \brief [26:26] E10able Transaction ID Error from MCIn - ENMCI10 (rw) */
Ifx_Strict_32Bit ENMCI11:1; /**< \brief [27:27] E11able Transaction ID Error from MCIn - ENMCI11 (rw) */
Ifx_Strict_32Bit reserved_28:4; /**< \brief [31:28] \internal Reserved */
} Ifx_DOM_TIDEN_Bits;
/** \brief Transaction ID Status Register */
typedef struct _Ifx_DOM_TIDSTAT_Bits
{
Ifx_Strict_32Bit TIDSCI0:1; /**< \brief [0:0] Tra0saction ID Error from SCIn Status - TIDSCI0 (rwh) */
Ifx_Strict_32Bit TIDSCI1:1; /**< \brief [1:1] Tra1saction ID Error from SCIn Status - TIDSCI1 (rwh) */
Ifx_Strict_32Bit TIDSCI2:1; /**< \brief [2:2] Tra2saction ID Error from SCIn Status - TIDSCI2 (rwh) */
Ifx_Strict_32Bit TIDSCI3:1; /**< \brief [3:3] Tra3saction ID Error from SCIn Status - TIDSCI3 (rwh) */
Ifx_Strict_32Bit TIDSCI4:1; /**< \brief [4:4] Tra4saction ID Error from SCIn Status - TIDSCI4 (rwh) */
Ifx_Strict_32Bit TIDSCI5:1; /**< \brief [5:5] Tra5saction ID Error from SCIn Status - TIDSCI5 (rwh) */
Ifx_Strict_32Bit TIDSCI6:1; /**< \brief [6:6] Tra6saction ID Error from SCIn Status - TIDSCI6 (rwh) */
Ifx_Strict_32Bit TIDSCI7:1; /**< \brief [7:7] Tra7saction ID Error from SCIn Status - TIDSCI7 (rwh) */
Ifx_Strict_32Bit TIDSCI8:1; /**< \brief [8:8] Tra8saction ID Error from SCIn Status - TIDSCI8 (rwh) */
Ifx_Strict_32Bit TIDSCI9:1; /**< \brief [9:9] Tra9saction ID Error from SCIn Status - TIDSCI9 (rwh) */
Ifx_Strict_32Bit TIDSCI10:1; /**< \brief [10:10] Tra10saction ID Error from SCIn Status - TIDSCI10 (rwh) */
Ifx_Strict_32Bit TIDSCI11:1; /**< \brief [11:11] Tra11saction ID Error from SCIn Status - TIDSCI11 (rwh) */
Ifx_Strict_32Bit TIDSCI12:1; /**< \brief [12:12] Tra12saction ID Error from SCIn Status - TIDSCI12 (rwh) */
Ifx_Strict_32Bit TIDSCI13:1; /**< \brief [13:13] Tra13saction ID Error from SCIn Status - TIDSCI13 (rwh) */
Ifx_Strict_32Bit TIDSCI14:1; /**< \brief [14:14] Tra14saction ID Error from SCIn Status - TIDSCI14 (rwh) */
Ifx_Strict_32Bit TIDSCI15:1; /**< \brief [15:15] Tra15saction ID Error from SCIn Status - TIDSCI15 (rwh) */
Ifx_Strict_32Bit TIDMCI0:1; /**< \brief [16:16] Tra0saction ID Error from MCIn Status - TIDMCI0 (rwh) */
Ifx_Strict_32Bit TIDMCI1:1; /**< \brief [17:17] Tra1saction ID Error from MCIn Status - TIDMCI1 (rwh) */
Ifx_Strict_32Bit TIDMCI2:1; /**< \brief [18:18] Tra2saction ID Error from MCIn Status - TIDMCI2 (rwh) */
Ifx_Strict_32Bit TIDMCI3:1; /**< \brief [19:19] Tra3saction ID Error from MCIn Status - TIDMCI3 (rwh) */
Ifx_Strict_32Bit TIDMCI4:1; /**< \brief [20:20] Tra4saction ID Error from MCIn Status - TIDMCI4 (rwh) */
Ifx_Strict_32Bit TIDMCI5:1; /**< \brief [21:21] Tra5saction ID Error from MCIn Status - TIDMCI5 (rwh) */
Ifx_Strict_32Bit TIDMCI6:1; /**< \brief [22:22] Tra6saction ID Error from MCIn Status - TIDMCI6 (rwh) */
Ifx_Strict_32Bit TIDMCI7:1; /**< \brief [23:23] Tra7saction ID Error from MCIn Status - TIDMCI7 (rwh) */
Ifx_Strict_32Bit TIDMCI8:1; /**< \brief [24:24] Tra8saction ID Error from MCIn Status - TIDMCI8 (rwh) */
Ifx_Strict_32Bit TIDMCI9:1; /**< \brief [25:25] Tra9saction ID Error from MCIn Status - TIDMCI9 (rwh) */
Ifx_Strict_32Bit TIDMCI10:1; /**< \brief [26:26] Tra10saction ID Error from MCIn Status - TIDMCI10 (rwh) */
Ifx_Strict_32Bit TIDMCI11:1; /**< \brief [27:27] Tra11saction ID Error from MCIn Status - TIDMCI11 (rwh) */
Ifx_Strict_32Bit reserved_28:4; /**< \brief [31:28] \internal Reserved */
} Ifx_DOM_TIDSTAT_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_dom_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_ACCEN0;
/** \brief Access Enable Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_ACCEN1_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_ACCEN1;
/** \brief Bridge Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_BRCON_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_BRCON;
/** \brief Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_ID_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_ID;
/** \brief Protocol Error Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_PESTAT_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_PESTAT;
/** \brief SCI ${x} Error Capture Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_SCICTRL_ERR_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_SCICTRL_ERR;
/** \brief SCI ${x} Error Address Capture Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_SCICTRL_ERRADDR_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_SCICTRL_ERRADDR;
/** \brief Protocol Error Control Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_SCICTRL_PECON_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_SCICTRL_PECON;
/** \brief SCI${x} Arbiter Priority Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_SCICTRL_PRIORITY_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_SCICTRL_PRIORITY;
/** \brief Transaction ID Enable Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_TIDEN_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_TIDEN;
/** \brief Transaction ID Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_DOM_TIDSTAT_Bits B; /**< \brief Bitfield access */
} Ifx_DOM_TIDSTAT;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dom_SCICTRL_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief SCICTRL object */
typedef volatile struct _Ifx_DOM_SCICTRL
{
Ifx_DOM_SCICTRL_PECON PECON; /**< \brief 0, Protocol Error Control Register ${x}*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_DOM_SCICTRL_PRIORITY PRIORITY; /**< \brief 8, SCI${x} Arbiter Priority Register*/
Ifx_UReg_8Bit reserved_C[4]; /**< \brief C, \internal Reserved */
Ifx_DOM_SCICTRL_ERRADDR ERRADDR; /**< \brief 10, SCI ${x} Error Address Capture Register*/
Ifx_UReg_8Bit reserved_14[4]; /**< \brief 14, \internal Reserved */
Ifx_DOM_SCICTRL_ERR ERR; /**< \brief 18, SCI ${x} Error Capture Register*/
Ifx_UReg_8Bit reserved_1C[4]; /**< \brief 1C, \internal Reserved */
} Ifx_DOM_SCICTRL;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Dom_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief DOM object */
typedef volatile struct _Ifx_DOM
{
Ifx_DOM_SCICTRL SCICTRL[16]; /**< \brief 0, */
Ifx_UReg_8Bit reserved_200[520]; /**< \brief 200, \internal Reserved */
Ifx_DOM_ID ID; /**< \brief 408, Identification Register*/
Ifx_UReg_8Bit reserved_40C[4]; /**< \brief 40C, \internal Reserved */
Ifx_DOM_PESTAT PESTAT; /**< \brief 410, Protocol Error Status Register*/
Ifx_UReg_8Bit reserved_414[4]; /**< \brief 414, \internal Reserved */
Ifx_DOM_TIDSTAT TIDSTAT; /**< \brief 418, Transaction ID Status Register*/
Ifx_UReg_8Bit reserved_41C[4]; /**< \brief 41C, \internal Reserved */
Ifx_DOM_TIDEN TIDEN; /**< \brief 420, Transaction ID Enable Register*/
Ifx_UReg_8Bit reserved_424[12]; /**< \brief 424, \internal Reserved */
Ifx_DOM_BRCON BRCON; /**< \brief 430, */
Ifx_UReg_8Bit reserved_434[188]; /**< \brief 434, \internal Reserved */
Ifx_DOM_ACCEN0 ACCEN0; /**< \brief 4F0, Access Enable Register 0*/
Ifx_UReg_8Bit reserved_4F4[4]; /**< \brief 4F4, \internal Reserved */
Ifx_DOM_ACCEN1 ACCEN1; /**< \brief 4F8, Access Enable Register 1*/
Ifx_UReg_8Bit reserved_4FC[64260]; /**< \brief 4FC, \internal Reserved */
} Ifx_DOM;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXDOM_REGDEF_H */

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/**
* \file IfxEdsadc_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Edsadc_Registers Edsadc Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Edsadc_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Edsadc_Registers
*
* \defgroup IfxSfr_Edsadc_Registers_union Register unions
* \ingroup IfxSfr_Edsadc_Registers
*
* \defgroup IfxSfr_Edsadc_Registers_struct Memory map
* \ingroup IfxSfr_Edsadc_Registers
*/
#ifndef IFXEDSADC_REGDEF_H
#define IFXEDSADC_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Edsadc_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_EDSADC_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_EDSADC_ACCEN0_Bits;
/** \brief Access Protection Register */
typedef struct _Ifx_EDSADC_ACCPROT_Bits
{
Ifx_UReg_32Bit RG00:1; /**< \brief [0:0] Register Group 0 - RG00 (rw) */
Ifx_UReg_32Bit RG01:1; /**< \brief [1:1] Register Group 1 - RG01 (rw) */
Ifx_UReg_32Bit RG02:1; /**< \brief [2:2] Register Group 2 - RG02 (rw) */
Ifx_UReg_32Bit RG03:1; /**< \brief [3:3] Register Group 3 - RG03 (rw) */
Ifx_UReg_32Bit RG04:1; /**< \brief [4:4] Register Group 4 - RG04 (rw) */
Ifx_UReg_32Bit RG05:1; /**< \brief [5:5] Register Group 5 - RG05 (rw) */
Ifx_UReg_32Bit RG06:1; /**< \brief [6:6] Register Group 6 - RG06 (rw) */
Ifx_UReg_32Bit RG07:1; /**< \brief [7:7] Register Group 7 - RG07 (rw) */
Ifx_UReg_32Bit reserved_8:8; /**< \brief [15:8] \internal Reserved */
Ifx_UReg_32Bit RG10:1; /**< \brief [16:16] Register Group 10 - RG10 (rw) */
Ifx_UReg_32Bit reserved_17:14; /**< \brief [30:17] \internal Reserved */
Ifx_UReg_32Bit RGG:1; /**< \brief [31:31] Register Group Global - RGG (rw) */
} Ifx_EDSADC_ACCPROT_Bits;
/** \brief Carrier Generator Configuration Register */
typedef struct _Ifx_EDSADC_CGCFG_Bits
{
Ifx_UReg_32Bit CGMOD:2; /**< \brief [1:0] Carrier Generator Operating Mode - CGMOD (rw) */
Ifx_UReg_32Bit BREV:1; /**< \brief [2:2] Bit-Reverse PWM Generation - BREV (rw) */
Ifx_UReg_32Bit SIGPOL:1; /**< \brief [3:3] Signal Polarity - SIGPOL (rw) */
Ifx_UReg_32Bit DIVCG:4; /**< \brief [7:4] Divider Factor for the PWM Pattern Signal Generator - DIVCG (rw) */
Ifx_UReg_32Bit reserved_8:7; /**< \brief [14:8] \internal Reserved */
Ifx_UReg_32Bit RUN:1; /**< \brief [15:15] Run Indicator - RUN (rh) */
Ifx_UReg_32Bit BITCOUNT:5; /**< \brief [20:16] Bit Counter - BITCOUNT (rh) */
Ifx_UReg_32Bit reserved_21:3; /**< \brief [23:21] \internal Reserved */
Ifx_UReg_32Bit STEPCOUNT:3; /**< \brief [26:24] Step Counter - STEPCOUNT (rh) */
Ifx_UReg_32Bit reserved_27:1; /**< \brief [27:27] \internal Reserved */
Ifx_UReg_32Bit STEPS:1; /**< \brief [28:28] Step Counter Sign - STEPS (rh) */
Ifx_UReg_32Bit STEPD:1; /**< \brief [29:29] Step Counter Direction - STEPD (rh) */
Ifx_UReg_32Bit SGNCG:1; /**< \brief [30:30] Sign Signal from Carrier Generator - SGNCG (rh) */
Ifx_UReg_32Bit reserved_31:1; /**< \brief [31:31] \internal Reserved */
} Ifx_EDSADC_CGCFG_Bits;
/** \brief Boundary Select Register ${x} */
typedef struct _Ifx_EDSADC_CH_BOUNDSEL_Bits
{
Ifx_UReg_32Bit BOUNDARYL:16; /**< \brief [15:0] Lower Boundary Value for Limit Checking - BOUNDARYL (rw) */
Ifx_UReg_32Bit BOUNDARYU:16; /**< \brief [31:16] Upper Boundary Value for Limit Checking - BOUNDARYU (rw) */
} Ifx_EDSADC_CH_BOUNDSEL_Bits;
/** \brief Carrier Generator Synchronization Reg. ${x} */
typedef struct _Ifx_EDSADC_CH_CGSYNC_Bits
{
Ifx_UReg_32Bit SDCOUNT:8; /**< \brief [7:0] Sign Delay Counter - SDCOUNT (rh) */
Ifx_UReg_32Bit SDCAP:8; /**< \brief [15:8] Sign Delay Capture Value - SDCAP (rh) */
Ifx_UReg_32Bit SDPOS:8; /**< \brief [23:16] Sign Delay Value for Positive Halfwave - SDPOS (rw) */
Ifx_UReg_32Bit SDNEG:8; /**< \brief [31:24] Sign Delay Value for Negative Halfwave - SDNEG (rw) */
} Ifx_EDSADC_CH_CGSYNC_Bits;
/** \brief Demodulator Input Config. Register ${x} */
typedef struct _Ifx_EDSADC_CH_DICFG_Bits
{
Ifx_UReg_32Bit DSS:3; /**< \brief [2:0] Data Stream Select - DSS (rw) */
Ifx_UReg_32Bit reserved_3:1; /**< \brief [3:3] \internal Reserved */
Ifx_UReg_32Bit DSRCEX:3; /**< \brief [6:4] Data Source for External Modulator - DSRCEX (rw) */
Ifx_UReg_32Bit reserved_7:1; /**< \brief [7:7] \internal Reserved */
Ifx_UReg_32Bit CSRCEX:3; /**< \brief [10:8] Clock Source for External Modulator - CSRCEX (rw) */
Ifx_UReg_32Bit reserved_11:4; /**< \brief [14:11] \internal Reserved */
Ifx_UReg_32Bit DSWC:1; /**< \brief [15:15] Write Control for Data Stream Selection - DSWC (w) */
Ifx_UReg_32Bit TRSEL:4; /**< \brief [19:16] Trigger Select - TRSEL (rw) */
Ifx_UReg_32Bit ITRMODE:2; /**< \brief [21:20] Integrator Trigger Mode - ITRMODE (rw) */
Ifx_UReg_32Bit TSTRMODE:2; /**< \brief [23:22] Timestamp Trigger Mode - TSTRMODE (rw) */
Ifx_UReg_32Bit reserved_24:2; /**< \brief [25:24] \internal Reserved */
Ifx_UReg_32Bit DRM:2; /**< \brief [27:26] Data Read Mode - DRM (rw) */
Ifx_UReg_32Bit TSM:1; /**< \brief [28:28] Time-Stamp Mode - TSM (rw) */
Ifx_UReg_32Bit RDM:1; /**< \brief [29:29] Result Display Mode - RDM (rw) */
Ifx_UReg_32Bit reserved_30:1; /**< \brief [30:30] \internal Reserved */
Ifx_UReg_32Bit MSWC:1; /**< \brief [31:31] Write Control for Mode Settings - MSWC (w) */
} Ifx_EDSADC_CH_DICFG_Bits;
/** \brief Auxiliary Filter Configuration Register ${x} */
typedef struct _Ifx_EDSADC_CH_FCFGA_Bits
{
Ifx_UReg_32Bit CFAEN:1; /**< \brief [0:0] CIC Filter (Auxiliary) Enable (rw) */
Ifx_UReg_32Bit CFADF:1; /**< \brief [1:1] CIC Filter (Auxiliary) Decimation Factor (rw) */
Ifx_UReg_32Bit reserved_2:14; /**< \brief [15:2] \internal Reserved */
Ifx_UReg_32Bit CFACNT:5; /**< \brief [20:16] CIC Filter (Auxiliary) Decimation Counter (rh) */
Ifx_UReg_32Bit reserved_21:11; /**< \brief [31:21] \internal Reserved */
} Ifx_EDSADC_CH_FCFGA_Bits;
/** \brief Filter Configuration Register ${x}, CIC Filter */
typedef struct _Ifx_EDSADC_CH_FCFGC_Bits
{
Ifx_UReg_32Bit CFMDF:9; /**< \brief [8:0] CIC Filter Decimation Factor - CFMDF (rw) */
Ifx_UReg_32Bit reserved_9:7; /**< \brief [15:9] \internal Reserved */
Ifx_UReg_32Bit CFMSV:9; /**< \brief [24:16] CIC Filter Start Value - CFMSV (rw) */
Ifx_UReg_32Bit reserved_25:7; /**< \brief [31:25] \internal Reserved */
} Ifx_EDSADC_CH_FCFGC_Bits;
/** \brief Filter Configuration Register ${x}, Main */
typedef struct _Ifx_EDSADC_CH_FCFGM_Bits
{
Ifx_UReg_32Bit FIR0EN:1; /**< \brief [0:0] FIR0 Filter Enable - FIR0EN (rw) */
Ifx_UReg_32Bit FIR1EN:1; /**< \brief [1:1] FIR1 Filter Enable - FIR1EN (rw) */
Ifx_UReg_32Bit OVCEN:1; /**< \brief [2:2] Overshoot Compensation Enable (rw) */
Ifx_UReg_32Bit FIR1DEC:1; /**< \brief [3:3] FIR1 Filter Decimation Rate - FIR1DEC (rw) */
Ifx_UReg_32Bit CICMOD:1; /**< \brief [4:4] CIC Filter Mode - CICMOD (rw) */
Ifx_UReg_32Bit PFEN:1; /**< \brief [5:5] Prefilter Enable - PFEN (rw) */
Ifx_UReg_32Bit reserved_6:2; /**< \brief [7:6] \internal Reserved */
Ifx_UReg_32Bit OCEN:3; /**< \brief [10:8] Offset Compensation Filter Enable - OCEN (rw) */
Ifx_UReg_32Bit OFFPROT:1; /**< \brief [11:11] Offset Protection - OFFPROT (rw) */
Ifx_UReg_32Bit reserved_12:3; /**< \brief [14:12] \internal Reserved */
Ifx_UReg_32Bit FMWC:1; /**< \brief [15:15] Write Control for Filter Modes - FMWC (w) */
Ifx_UReg_32Bit SRGM:2; /**< \brief [17:16] Service Request Generation for Main Service Request - SRGM (rw) */
Ifx_UReg_32Bit reserved_18:2; /**< \brief [19:18] \internal Reserved */
Ifx_UReg_32Bit SRGA:2; /**< \brief [21:20] Service Request Generation for Alternate Service Request - SRGA (rw) */
Ifx_UReg_32Bit ESEL:2; /**< \brief [23:22] Event Select - ESEL (rw) */
Ifx_UReg_32Bit EGT:1; /**< \brief [24:24] Event Gating (rw) */
Ifx_UReg_32Bit reserved_25:3; /**< \brief [27:25] \internal Reserved */
Ifx_UReg_32Bit CALIB:1; /**< \brief [28:28] Calibration Trigger - CALIB (w) */
Ifx_UReg_32Bit AUTOCAL:1; /**< \brief [29:29] Automatic Calibration Control - AUTOCAL (rw) */
Ifx_UReg_32Bit reserved_30:1; /**< \brief [30:30] \internal Reserved */
Ifx_UReg_32Bit CSRWC:1; /**< \brief [31:31] Write Control for Calibration and Service Request Modes - CSRWC (w) */
} Ifx_EDSADC_CH_FCFGM_Bits;
/** \brief Filter Counter Register ${x}, CIC Filter */
typedef struct _Ifx_EDSADC_CH_FCNTC_Bits
{
Ifx_UReg_32Bit CFMDCNT:9; /**< \brief [8:0] CIC Filter Decimation Counter - CFMDCNT (rh) */
Ifx_UReg_32Bit reserved_9:21; /**< \brief [29:9] \internal Reserved */
Ifx_UReg_32Bit CAL:2; /**< \brief [31:30] Calibration Status Flag - CAL (rh) */
} Ifx_EDSADC_CH_FCNTC_Bits;
/** \brief Gain Calibration Register ${x} */
typedef struct _Ifx_EDSADC_CH_GAINCAL_Bits
{
Ifx_UReg_32Bit CALFACTOR:13; /**< \brief [12:0] Multiplication Factor for Gain Calibration - CALFACTOR (rwh) */
Ifx_UReg_32Bit reserved_13:3; /**< \brief [15:13] \internal Reserved */
Ifx_UReg_32Bit CALTARGET:15; /**< \brief [30:16] Target Value for Calibrated Fullscale - CALTARGET (rw) */
Ifx_UReg_32Bit reserved_31:1; /**< \brief [31:31] \internal Reserved */
} Ifx_EDSADC_CH_GAINCAL_Bits;
/** \brief Gain Correction Register ${x} */
typedef struct _Ifx_EDSADC_CH_GAINCORR_Bits
{
Ifx_UReg_32Bit GAINFACTOR:13; /**< \brief [12:0] Multiplication Factor for Gain Correction - GAINFACTOR (rw) */
Ifx_UReg_32Bit reserved_13:3; /**< \brief [15:13] \internal Reserved */
Ifx_UReg_32Bit CICSHIFT:5; /**< \brief [20:16] Position of the CIC Filter Output Shifter (rw) */
Ifx_UReg_32Bit reserved_21:11; /**< \brief [31:21] \internal Reserved */
} Ifx_EDSADC_CH_GAINCORR_Bits;
/** \brief Gain Control Register ${x} */
typedef struct _Ifx_EDSADC_CH_GAINCTR_Bits
{
Ifx_UReg_32Bit GAINFACTOR:13; /**< \brief [12:0] Multiplication Factor for Gain Correction During Calibration - GAINFACTOR (rw) */
Ifx_UReg_32Bit reserved_13:3; /**< \brief [15:13] \internal Reserved */
Ifx_UReg_32Bit CICSHIFT:5; /**< \brief [20:16] Position of the CIC Filter Output Shifter During Calibration - CICSHIFT (rw) */
Ifx_UReg_32Bit reserved_21:3; /**< \brief [23:21] \internal Reserved */
Ifx_UReg_32Bit CICDEC:3; /**< \brief [26:24] Decimation Rate of the CIC Filter During Calibration - CICDEC (rw) */
Ifx_UReg_32Bit reserved_27:5; /**< \brief [31:27] \internal Reserved */
} Ifx_EDSADC_CH_GAINCTR_Bits;
/** \brief Intermediate Integration Value */
typedef struct _Ifx_EDSADC_CH_IIVAL_Bits
{
Ifx_UReg_32Bit IVAL:26; /**< \brief [25:0] Result of most recent accumulation - IVAL (rh) */
Ifx_UReg_32Bit reserved_26:6; /**< \brief [31:26] \internal Reserved */
} Ifx_EDSADC_CH_IIVAL_Bits;
/** \brief Integrator Status Register ${x} */
typedef struct _Ifx_EDSADC_CH_ISTAT_Bits
{
Ifx_UReg_32Bit NVALCNT:6; /**< \brief [5:0] Number of Values Counted - NVALCNT (rh) */
Ifx_UReg_32Bit reserved_6:2; /**< \brief [7:6] \internal Reserved */
Ifx_UReg_32Bit REPCNT:4; /**< \brief [11:8] Integration Cycle Counter - REPCNT (rh) */
Ifx_UReg_32Bit reserved_12:3; /**< \brief [14:12] \internal Reserved */
Ifx_UReg_32Bit INTEN:1; /**< \brief [15:15] Integration Enable - INTEN (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_EDSADC_CH_ISTAT_Bits;
/** \brief Integration Window Control Register ${x} */
typedef struct _Ifx_EDSADC_CH_IWCTR_Bits
{
Ifx_UReg_32Bit ISC:3; /**< \brief [2:0] Integrator Shift Control - ISC (rw) */
Ifx_UReg_32Bit reserved_3:1; /**< \brief [3:3] \internal Reserved */
Ifx_UReg_32Bit IWS:1; /**< \brief [4:4] Integration Window Size - IWS (rw) */
Ifx_UReg_32Bit FRC:1; /**< \brief [5:5] Filter Chain Restart Control (rw) */
Ifx_UReg_32Bit reserved_6:2; /**< \brief [7:6] \internal Reserved */
Ifx_UReg_32Bit REPVAL:4; /**< \brief [11:8] Number of Integration Cycles - REPVAL (rw) */
Ifx_UReg_32Bit reserved_12:4; /**< \brief [15:12] \internal Reserved */
Ifx_UReg_32Bit NVALDIS:6; /**< \brief [21:16] Number of Values Discarded - NVALDIS (rw) */
Ifx_UReg_32Bit reserved_22:2; /**< \brief [23:22] \internal Reserved */
Ifx_UReg_32Bit NVALINT:6; /**< \brief [29:24] Number of Values to be Accumulated - NVALINT (rw) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_EDSADC_CH_IWCTR_Bits;
/** \brief Modulator Configuration Register ${x} */
typedef struct _Ifx_EDSADC_CH_MODCFG_Bits
{
Ifx_UReg_32Bit INCFGP:2; /**< \brief [1:0] Configuration of Positive Input Line - INCFGP (rw) */
Ifx_UReg_32Bit INCFGN:2; /**< \brief [3:2] Configuration of Negative Input Line - INCFGN (rw) */
Ifx_UReg_32Bit GAINSEL:4; /**< \brief [7:4] Gain Select of Analog Input Path - GAINSEL (rw) */
Ifx_UReg_32Bit INSEL:2; /**< \brief [9:8] Input Pin Selection - INSEL (rw) */
Ifx_UReg_32Bit INMUX:2; /**< \brief [11:10] Input Multiplexer Setting - INMUX (rh) */
Ifx_UReg_32Bit INMODE:2; /**< \brief [13:12] Input Multiplexer Control Mode - INMODE (rw) */
Ifx_UReg_32Bit INMAC:1; /**< \brief [14:14] Input Multiplexer Action Control - INMAC (rw) */
Ifx_UReg_32Bit INCWC:1; /**< \brief [15:15] Write Control for Input Parameters - INCWC (w) */
Ifx_UReg_32Bit DIVM:3; /**< \brief [18:16] Modulator Clock Period - DIVM (rw) */
Ifx_UReg_32Bit reserved_19:1; /**< \brief [19:19] \internal Reserved */
Ifx_UReg_32Bit ACSD:3; /**< \brief [22:20] Analog Clock Synchronization Delay - ACSD (rw) */
Ifx_UReg_32Bit reserved_23:3; /**< \brief [25:23] \internal Reserved */
Ifx_UReg_32Bit DITHEN:1; /**< \brief [26:26] Dithering Function Enable - DITHEN (rw) */
Ifx_UReg_32Bit IREN:1; /**< \brief [27:27] Integrator Reset Enable - IREN (rw) */
Ifx_UReg_32Bit APC:2; /**< \brief [29:28] Automatic Power Control - APC (rw) */
Ifx_UReg_32Bit reserved_30:1; /**< \brief [30:30] \internal Reserved */
Ifx_UReg_32Bit MMWC:1; /**< \brief [31:31] Write Control for Modulator Mode Settings - MMWC (w) */
} Ifx_EDSADC_CH_MODCFG_Bits;
/** \brief Offset Compensation Register ${x} */
typedef struct _Ifx_EDSADC_CH_OFFCOMP_Bits
{
Ifx_UReg_32Bit OFFSET:16; /**< \brief [15:0] Offset Value - OFFSET (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_EDSADC_CH_OFFCOMP_Bits;
/** \brief Overshoot Compensation Cfg. Register ${x} */
typedef struct _Ifx_EDSADC_CH_OVSCFG_Bits
{
Ifx_UReg_32Bit SRFS:2; /**< \brief [1:0] Slew Rate Filter Strength (rw) */
Ifx_UReg_32Bit SRFRT:2; /**< \brief [3:2] Slew Rate Filter Run Time (rw) */
Ifx_UReg_32Bit SDM:1; /**< \brief [4:4] Step Detection Mode (rw) */
Ifx_UReg_32Bit reserved_5:11; /**< \brief [15:5] \internal Reserved */
Ifx_UReg_32Bit SDTH:11; /**< \brief [26:16] Step Detection Threshold (rw) */
Ifx_UReg_32Bit reserved_27:5; /**< \brief [31:27] \internal Reserved */
} Ifx_EDSADC_CH_OVSCFG_Bits;
/** \brief Rectification Configuration Register ${x} */
typedef struct _Ifx_EDSADC_CH_RECTCFG_Bits
{
Ifx_UReg_32Bit RFEN:1; /**< \brief [0:0] Rectification Enable - RFEN (rw) */
Ifx_UReg_32Bit reserved_1:3; /**< \brief [3:1] \internal Reserved */
Ifx_UReg_32Bit SSRC:2; /**< \brief [5:4] Sign Source (rw) */
Ifx_UReg_32Bit reserved_6:2; /**< \brief [7:6] \internal Reserved */
Ifx_UReg_32Bit SSCH:4; /**< \brief [11:8] Sign Source Channel (rw) */
Ifx_UReg_32Bit reserved_12:3; /**< \brief [14:12] \internal Reserved */
Ifx_UReg_32Bit SDCVAL:1; /**< \brief [15:15] Valid Flag - SDCVAL (rh) */
Ifx_UReg_32Bit reserved_16:14; /**< \brief [29:16] \internal Reserved */
Ifx_UReg_32Bit SGNCS:1; /**< \brief [30:30] Selected Carrier Sign Signal - SGNCS (rh) */
Ifx_UReg_32Bit SGND:1; /**< \brief [31:31] Sign Signal Delayed - SGND (rh) */
} Ifx_EDSADC_CH_RECTCFG_Bits;
/** \brief Result Register ${x} Auxiliary */
typedef struct _Ifx_EDSADC_CH_RESA_Bits
{
Ifx_UReg_32Bit RESULT:16; /**< \brief [15:0] Most Recent Result of Auxiliary Filter (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_EDSADC_CH_RESA_Bits;
/** \brief Result Register ${x} Main */
typedef struct _Ifx_EDSADC_CH_RESM_Bits
{
Ifx_UReg_32Bit RESULTLO:16; /**< \brief [15:0] Result Value Lower Part - RESULTLO (rh) */
Ifx_UReg_32Bit RESULTHI:16; /**< \brief [31:16] Result Value Higher Part - RESULTHI (rh) */
} Ifx_EDSADC_CH_RESM_Bits;
/** \brief Result FIFO Control Register ${x} */
typedef struct _Ifx_EDSADC_CH_RFC_Bits
{
Ifx_UReg_32Bit SRLVL:2; /**< \brief [1:0] Service Request FIFO Level (rw) */
Ifx_UReg_32Bit reserved_2:2; /**< \brief [3:2] \internal Reserved */
Ifx_UReg_32Bit RDEC:1; /**< \brief [4:4] Read Error Flag Clear (w) */
Ifx_UReg_32Bit WREC:1; /**< \brief [5:5] Write Error Flag Clear (w) */
Ifx_UReg_32Bit FIFL:1; /**< \brief [6:6] FIFO Flush (w) */
Ifx_UReg_32Bit reserved_7:9; /**< \brief [15:7] \internal Reserved */
Ifx_UReg_32Bit FILL:3; /**< \brief [18:16] FIFO Fill Level (rh) */
Ifx_UReg_32Bit reserved_19:1; /**< \brief [19:19] \internal Reserved */
Ifx_UReg_32Bit RDERR:1; /**< \brief [20:20] Read Error Flag (rh) */
Ifx_UReg_32Bit WRERR:1; /**< \brief [21:21] Write Error Flag (rh) */
Ifx_UReg_32Bit reserved_22:10; /**< \brief [31:22] \internal Reserved */
} Ifx_EDSADC_CH_RFC_Bits;
/** \brief Time-Stamp Counter ${x} */
typedef struct _Ifx_EDSADC_CH_TSCNT_Bits
{
Ifx_UReg_32Bit TSCOUNT:16; /**< \brief [15:0] Timestamp Counter Value - TSCOUNT (rh) */
Ifx_UReg_32Bit TSCLK:2; /**< \brief [17:16] Timestamp Counter Clock Selection - TSCLK (rw) */
Ifx_UReg_32Bit reserved_18:1; /**< \brief [18:18] \internal Reserved */
Ifx_UReg_32Bit TSCRUN:1; /**< \brief [19:19] Timestamp Counter Run Control - TSCRUN (rw) */
Ifx_UReg_32Bit AMXCOPY:1; /**< \brief [20:20] Analog MUX Setting Copy Enable - AMXCOPY (rw) */
Ifx_UReg_32Bit reserved_21:11; /**< \brief [31:21] \internal Reserved */
} Ifx_EDSADC_CH_TSCNT_Bits;
/** \brief Time-Stamp Register ${x} */
typedef struct _Ifx_EDSADC_CH_TSTMP_Bits
{
Ifx_UReg_32Bit TIMESTAMP:16; /**< \brief [15:0] The Most Recent Captured Timestamp Value - TIMESTAMP (rh) */
Ifx_UReg_32Bit AMX:2; /**< \brief [17:16] Analog Multiplexer Setting - AMX (rh) */
Ifx_UReg_32Bit reserved_18:13; /**< \brief [30:18] \internal Reserved */
Ifx_UReg_32Bit TSVAL:1; /**< \brief [31:31] Timestamp Valid - TSVAL (rh) */
} Ifx_EDSADC_CH_TSTMP_Bits;
/** \brief Common Mode Voltage Register ${x} */
typedef struct _Ifx_EDSADC_CH_VCM_Bits
{
Ifx_UReg_32Bit VREFXSEL:2; /**< \brief [1:0] Fractional Reference Voltage Selection - VREFXSEL (rw) */
Ifx_UReg_32Bit VXON:1; /**< \brief [2:2] Fractional Reference Voltage Enable - VXON (rw) */
Ifx_UReg_32Bit reserved_3:13; /**< \brief [15:3] \internal Reserved */
Ifx_UReg_32Bit INPVC0:1; /**< \brief [16:16] Voltage Control of Positive Inputs 0 of CH0 (rw) */
Ifx_UReg_32Bit INPVC1:1; /**< \brief [17:17] Voltage Control of Positive Inputs 1 of CH0 (rw) */
Ifx_UReg_32Bit INPVC2:1; /**< \brief [18:18] Voltage Control of Positive Inputs 2 of CH0 (rw) */
Ifx_UReg_32Bit INPVC3:1; /**< \brief [19:19] Voltage Control of Positive Inputs 3 of CH0 (rw) */
Ifx_UReg_32Bit INNVC0:1; /**< \brief [20:20] Voltage Control of Negative Inputs 0 of CH0 (rw) */
Ifx_UReg_32Bit INNVC1:1; /**< \brief [21:21] Voltage Control of Negative Inputs 1 of CH0 (rw) */
Ifx_UReg_32Bit INNVC2:1; /**< \brief [22:22] Voltage Control of Negative Inputs 2 of CH0 (rw) */
Ifx_UReg_32Bit INNVC3:1; /**< \brief [23:23] Voltage Control of Negative Inputs 3 of CH0 (rw) */
Ifx_UReg_32Bit reserved_24:8; /**< \brief [31:24] \internal Reserved */
} Ifx_EDSADC_CH_VCM_Bits;
/** \brief Clock Control Register */
typedef struct _Ifx_EDSADC_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (r) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control - EDIS (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_EDSADC_CLC_Bits;
/** \brief Event Flag Register */
typedef struct _Ifx_EDSADC_EVFLAG_Bits
{
Ifx_UReg_32Bit RESEV0:1; /**< \brief [0:0] Result Event - RESEV0 (rwh) */
Ifx_UReg_32Bit RESEV1:1; /**< \brief [1:1] Result Event - RESEV1 (rwh) */
Ifx_UReg_32Bit RESEV2:1; /**< \brief [2:2] Result Event - RESEV2 (rwh) */
Ifx_UReg_32Bit RESEV3:1; /**< \brief [3:3] Result Event - RESEV3 (rwh) */
Ifx_UReg_32Bit RESEV4:1; /**< \brief [4:4] Result Event - RESEV4 (rwh) */
Ifx_UReg_32Bit RESEV5:1; /**< \brief [5:5] Result Event - RESEV5 (rwh) */
Ifx_UReg_32Bit reserved_6:10; /**< \brief [15:6] \internal Reserved */
Ifx_UReg_32Bit ALEV0:1; /**< \brief [16:16] Alarm Event - ALEV0 (rwh) */
Ifx_UReg_32Bit ALEV1:1; /**< \brief [17:17] Alarm Event - ALEV1 (rwh) */
Ifx_UReg_32Bit ALEV2:1; /**< \brief [18:18] Alarm Event - ALEV2 (rwh) */
Ifx_UReg_32Bit ALEV3:1; /**< \brief [19:19] Alarm Event - ALEV3 (rwh) */
Ifx_UReg_32Bit ALEV4:1; /**< \brief [20:20] Alarm Event - ALEV4 (rwh) */
Ifx_UReg_32Bit ALEV5:1; /**< \brief [21:21] Alarm Event - ALEV5 (rwh) */
Ifx_UReg_32Bit reserved_22:10; /**< \brief [31:22] \internal Reserved */
} Ifx_EDSADC_EVFLAG_Bits;
/** \brief Event Flag Clear Register */
typedef struct _Ifx_EDSADC_EVFLAGCLR_Bits
{
Ifx_UReg_32Bit RESEC0:1; /**< \brief [0:0] Result Event Clear - RESEC0 (w) */
Ifx_UReg_32Bit RESEC1:1; /**< \brief [1:1] Result Event Clear - RESEC1 (w) */
Ifx_UReg_32Bit RESEC2:1; /**< \brief [2:2] Result Event Clear - RESEC2 (w) */
Ifx_UReg_32Bit RESEC3:1; /**< \brief [3:3] Result Event Clear - RESEC3 (w) */
Ifx_UReg_32Bit RESEC4:1; /**< \brief [4:4] Result Event Clear - RESEC4 (w) */
Ifx_UReg_32Bit RESEC5:1; /**< \brief [5:5] Result Event Clear - RESEC5 (w) */
Ifx_UReg_32Bit reserved_6:10; /**< \brief [15:6] \internal Reserved */
Ifx_UReg_32Bit ALEC0:1; /**< \brief [16:16] Alarm Event Clear - ALEC0 (w) */
Ifx_UReg_32Bit ALEC1:1; /**< \brief [17:17] Alarm Event Clear - ALEC1 (w) */
Ifx_UReg_32Bit ALEC2:1; /**< \brief [18:18] Alarm Event Clear - ALEC2 (w) */
Ifx_UReg_32Bit ALEC3:1; /**< \brief [19:19] Alarm Event Clear - ALEC3 (w) */
Ifx_UReg_32Bit ALEC4:1; /**< \brief [20:20] Alarm Event Clear - ALEC4 (w) */
Ifx_UReg_32Bit ALEC5:1; /**< \brief [21:21] Alarm Event Clear - ALEC5 (w) */
Ifx_UReg_32Bit reserved_22:10; /**< \brief [31:22] \internal Reserved */
} Ifx_EDSADC_EVFLAGCLR_Bits;
/** \brief Global Configuration Register */
typedef struct _Ifx_EDSADC_GLOBCFG_Bits
{
Ifx_UReg_32Bit reserved_0:8; /**< \brief [7:0] \internal Reserved */
Ifx_UReg_32Bit DITRIM:3; /**< \brief [10:8] Trimming Value for the Dithering Function - DITRIM (rw) */
Ifx_UReg_32Bit reserved_11:1; /**< \brief [11:11] \internal Reserved */
Ifx_UReg_32Bit USC:1; /**< \brief [12:12] Unsynchronized Clock Generation - USC (rw) */
Ifx_UReg_32Bit SUPLEV:2; /**< \brief [14:13] Supply Voltage Level (rw) */
Ifx_UReg_32Bit CPWC:1; /**< \brief [15:15] Write Control for Clock Parameters - CPWC (w) */
Ifx_UReg_32Bit reserved_16:8; /**< \brief [23:16] \internal Reserved */
Ifx_UReg_32Bit SVCH:4; /**< \brief [27:24] Supervision Channel Select (rw) */
Ifx_UReg_32Bit SVSIG:2; /**< \brief [29:28] Supervision Signal Select (rw) */
Ifx_UReg_32Bit reserved_30:1; /**< \brief [30:30] \internal Reserved */
Ifx_UReg_32Bit SVWC:1; /**< \brief [31:31] Write Control for Supervision Parameters (w) */
} Ifx_EDSADC_GLOBCFG_Bits;
/** \brief Global Run Control Register */
typedef struct _Ifx_EDSADC_GLOBRC_Bits
{
Ifx_UReg_32Bit CH0RUN:1; /**< \brief [0:0] Channel 0 Run Control - CH0RUN (rw) */
Ifx_UReg_32Bit CH1RUN:1; /**< \brief [1:1] Channel 1 Run Control - CH1RUN (rw) */
Ifx_UReg_32Bit CH2RUN:1; /**< \brief [2:2] Channel 2 Run Control - CH2RUN (rw) */
Ifx_UReg_32Bit CH3RUN:1; /**< \brief [3:3] Channel 3 Run Control - CH3RUN (rw) */
Ifx_UReg_32Bit CH4RUN:1; /**< \brief [4:4] Channel 4 Run Control - CH4RUN (rw) */
Ifx_UReg_32Bit CH5RUN:1; /**< \brief [5:5] Channel 5 Run Control - CH5RUN (rw) */
Ifx_UReg_32Bit reserved_6:10; /**< \brief [15:6] \internal Reserved */
Ifx_UReg_32Bit M0RUN:1; /**< \brief [16:16] Modulator 0 Run Control - M0RUN (rw) */
Ifx_UReg_32Bit M1RUN:1; /**< \brief [17:17] Modulator 1 Run Control - M1RUN (rw) */
Ifx_UReg_32Bit M2RUN:1; /**< \brief [18:18] Modulator 2 Run Control - M2RUN (rw) */
Ifx_UReg_32Bit M3RUN:1; /**< \brief [19:19] Modulator 3 Run Control - M3RUN (rw) */
Ifx_UReg_32Bit M4RUN:1; /**< \brief [20:20] Modulator 4 Run Control - M4RUN (rw) */
Ifx_UReg_32Bit M5RUN:1; /**< \brief [21:21] Modulator 5 Run Control - M5RUN (rw) */
Ifx_UReg_32Bit reserved_22:10; /**< \brief [31:22] \internal Reserved */
} Ifx_EDSADC_GLOBRC_Bits;
/** \brief Module Identification Register */
typedef struct _Ifx_EDSADC_ID_Bits
{
Ifx_UReg_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision - MOD_REV (r) */
Ifx_UReg_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Type - MOD_TYPE (r) */
Ifx_UReg_32Bit MOD_NUMBER:16; /**< \brief [31:16] Module Number - MOD_NUMBER (r) */
} Ifx_EDSADC_ID_Bits;
/** \brief Kernel Reset Register 0 */
typedef struct _Ifx_EDSADC_KRST0_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status - RSTSTAT (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_EDSADC_KRST0_Bits;
/** \brief Kernel Reset Register 1 */
typedef struct _Ifx_EDSADC_KRST1_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_EDSADC_KRST1_Bits;
/** \brief Kernel Reset Status Clear Register */
typedef struct _Ifx_EDSADC_KRSTCLR_Bits
{
Ifx_UReg_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear - CLR (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_EDSADC_KRSTCLR_Bits;
/** \brief OCDS Control and Status Register */
typedef struct _Ifx_EDSADC_OCS_Bits
{
Ifx_UReg_32Bit reserved_0:24; /**< \brief [23:0] \internal Reserved */
Ifx_UReg_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control - SUS (rw) */
Ifx_UReg_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection - SUS_P (w) */
Ifx_UReg_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State - SUSSTA (rh) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_EDSADC_OCS_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_edsadc_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_ACCEN0;
/** \brief Access Protection Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_ACCPROT_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_ACCPROT;
/** \brief Carrier Generator Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CGCFG_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CGCFG;
/** \brief Boundary Select Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_BOUNDSEL_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_BOUNDSEL;
/** \brief Carrier Generator Synchronization Reg. ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_CGSYNC_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_CGSYNC;
/** \brief Demodulator Input Config. Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_DICFG_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_DICFG;
/** \brief Auxiliary Filter Configuration Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_FCFGA_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_FCFGA;
/** \brief Filter Configuration Register ${x}, CIC Filter */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_FCFGC_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_FCFGC;
/** \brief Filter Configuration Register ${x}, Main */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_FCFGM_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_FCFGM;
/** \brief Filter Counter Register ${x}, CIC Filter */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_FCNTC_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_FCNTC;
/** \brief Gain Calibration Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_GAINCAL_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_GAINCAL;
/** \brief Gain Correction Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_GAINCORR_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_GAINCORR;
/** \brief Gain Control Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_GAINCTR_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_GAINCTR;
/** \brief Intermediate Integration Value */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_IIVAL_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_IIVAL;
/** \brief Integrator Status Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_ISTAT_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_ISTAT;
/** \brief Integration Window Control Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_IWCTR_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_IWCTR;
/** \brief Modulator Configuration Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_MODCFG_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_MODCFG;
/** \brief Offset Compensation Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_OFFCOMP_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_OFFCOMP;
/** \brief Overshoot Compensation Cfg. Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_OVSCFG_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_OVSCFG;
/** \brief Rectification Configuration Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_RECTCFG_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_RECTCFG;
/** \brief Result Register ${x} Auxiliary */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_RESA_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_RESA;
/** \brief Result Register ${x} Main */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_RESM_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_RESM;
/** \brief Result FIFO Control Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_RFC_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_RFC;
/** \brief Time-Stamp Counter ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_TSCNT_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_TSCNT;
/** \brief Time-Stamp Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_TSTMP_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_TSTMP;
/** \brief Common Mode Voltage Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CH_VCM_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CH_VCM;
/** \brief Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_CLC;
/** \brief Event Flag Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_EVFLAG_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_EVFLAG;
/** \brief Event Flag Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_EVFLAGCLR_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_EVFLAGCLR;
/** \brief Global Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_GLOBCFG_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_GLOBCFG;
/** \brief Global Run Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_GLOBRC_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_GLOBRC;
/** \brief Module Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_ID_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_ID;
/** \brief Kernel Reset Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_KRST0_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_KRST0;
/** \brief Kernel Reset Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_KRST1_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_KRST1;
/** \brief Kernel Reset Status Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_KRSTCLR_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_KRSTCLR;
/** \brief OCDS Control and Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_EDSADC_OCS_Bits B; /**< \brief Bitfield access */
} Ifx_EDSADC_OCS;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Edsadc_CH_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief CH object */
typedef volatile struct _Ifx_EDSADC_CH
{
Ifx_EDSADC_CH_MODCFG MODCFG; /**< \brief 0, Modulator Configuration Register ${x}*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_EDSADC_CH_DICFG DICFG; /**< \brief 8, Demodulator Input Config. Register ${x}*/
Ifx_UReg_8Bit reserved_C[4]; /**< \brief C, \internal Reserved */
Ifx_EDSADC_CH_FCFGM FCFGM; /**< \brief 10, Filter Configuration Register ${x}, Main*/
Ifx_EDSADC_CH_FCFGC FCFGC; /**< \brief 14, Filter Configuration Register ${x}, CIC Filter*/
Ifx_EDSADC_CH_FCNTC FCNTC; /**< \brief 18, Filter Counter Register ${x}, CIC Filter*/
Ifx_EDSADC_CH_OVSCFG OVSCFG; /**< \brief 1C, Overshoot Compensation Cfg. Register ${x}*/
Ifx_EDSADC_CH_IWCTR IWCTR; /**< \brief 20, Integration Window Control Register ${x}*/
Ifx_EDSADC_CH_IIVAL IIVAL; /**< \brief 24, Intermediate Integration Value*/
Ifx_EDSADC_CH_ISTAT ISTAT; /**< \brief 28, Integrator Status Register ${x}*/
Ifx_EDSADC_CH_RFC RFC; /**< \brief 2C, Result FIFO Control Register ${x}*/
Ifx_EDSADC_CH_RESM RESM; /**< \brief 30, Result Register ${x} Main*/
Ifx_UReg_8Bit reserved_34[4]; /**< \brief 34, \internal Reserved */
Ifx_EDSADC_CH_OFFCOMP OFFCOMP; /**< \brief 38, Offset Compensation Register ${x}*/
Ifx_EDSADC_CH_GAINCAL GAINCAL; /**< \brief 3C, Gain Calibration Register ${x}*/
Ifx_EDSADC_CH_GAINCTR GAINCTR; /**< \brief 40, Gain Control Register ${x}*/
Ifx_EDSADC_CH_GAINCORR GAINCORR; /**< \brief 44, Gain Correction Register ${x}*/
Ifx_UReg_8Bit reserved_48[8]; /**< \brief 48, \internal Reserved */
Ifx_EDSADC_CH_TSTMP TSTMP; /**< \brief 50, Time-Stamp Register ${x}*/
Ifx_EDSADC_CH_TSCNT TSCNT; /**< \brief 54, Time-Stamp Counter ${x}*/
Ifx_UReg_8Bit reserved_58[24]; /**< \brief 58, \internal Reserved */
Ifx_EDSADC_CH_FCFGA FCFGA; /**< \brief 70, Auxiliary Filter Configuration Register ${x}*/
Ifx_UReg_8Bit reserved_74[4]; /**< \brief 74, \internal Reserved */
Ifx_EDSADC_CH_BOUNDSEL BOUNDSEL; /**< \brief 78, Boundary Select Register ${x}*/
Ifx_UReg_8Bit reserved_7C[4]; /**< \brief 7C, \internal Reserved */
Ifx_EDSADC_CH_RESA RESA; /**< \brief 80, Result Register ${x} Auxiliary*/
Ifx_UReg_8Bit reserved_84[28]; /**< \brief 84, \internal Reserved */
Ifx_EDSADC_CH_CGSYNC CGSYNC; /**< \brief A0, Carrier Generator Synchronization Reg. ${x}*/
Ifx_UReg_8Bit reserved_A4[4]; /**< \brief A4, \internal Reserved */
Ifx_EDSADC_CH_RECTCFG RECTCFG; /**< \brief A8, Rectification Configuration Register ${x}*/
Ifx_UReg_8Bit reserved_AC[4]; /**< \brief AC, \internal Reserved */
Ifx_EDSADC_CH_VCM VCM; /**< \brief B0, Common Mode Voltage Register ${x}*/
Ifx_UReg_8Bit reserved_B4[76]; /**< \brief B4, \internal Reserved */
} Ifx_EDSADC_CH;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Edsadc_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief EDSADC object */
typedef volatile struct _Ifx_EDSADC
{
Ifx_EDSADC_CLC CLC; /**< \brief 0, Clock Control Register*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_EDSADC_ID ID; /**< \brief 8, Module Identification Register*/
Ifx_UReg_8Bit reserved_C[28]; /**< \brief C, \internal Reserved */
Ifx_EDSADC_OCS OCS; /**< \brief 28, OCDS Control and Status Register*/
Ifx_EDSADC_KRSTCLR KRSTCLR; /**< \brief 2C, Kernel Reset Status Clear Register*/
Ifx_EDSADC_KRST1 KRST1; /**< \brief 30, Kernel Reset Register 1*/
Ifx_EDSADC_KRST0 KRST0; /**< \brief 34, Kernel Reset Register 0*/
Ifx_UReg_8Bit reserved_38[4]; /**< \brief 38, \internal Reserved */
Ifx_EDSADC_ACCEN0 ACCEN0; /**< \brief 3C, Access Enable Register 0*/
Ifx_UReg_8Bit reserved_40[64]; /**< \brief 40, \internal Reserved */
Ifx_EDSADC_GLOBCFG GLOBCFG; /**< \brief 80, Global Configuration Register*/
Ifx_UReg_8Bit reserved_84[4]; /**< \brief 84, \internal Reserved */
Ifx_EDSADC_GLOBRC GLOBRC; /**< \brief 88, Global Run Control Register*/
Ifx_UReg_8Bit reserved_8C[4]; /**< \brief 8C, \internal Reserved */
Ifx_EDSADC_ACCPROT ACCPROT; /**< \brief 90, Access Protection Register*/
Ifx_UReg_8Bit reserved_94[12]; /**< \brief 94, \internal Reserved */
Ifx_EDSADC_CGCFG CGCFG; /**< \brief A0, Carrier Generator Configuration Register*/
Ifx_UReg_8Bit reserved_A4[60]; /**< \brief A4, \internal Reserved */
Ifx_EDSADC_EVFLAG EVFLAG; /**< \brief E0, Event Flag Register*/
Ifx_EDSADC_EVFLAGCLR EVFLAGCLR; /**< \brief E4, Event Flag Clear Register*/
Ifx_UReg_8Bit reserved_E8[24]; /**< \brief E8, \internal Reserved */
Ifx_EDSADC_CH CH[6]; /**< \brief 100, */
Ifx_UReg_8Bit reserved_700[2304]; /**< \brief 700, \internal Reserved */
} Ifx_EDSADC;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXEDSADC_REGDEF_H */

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/**
* \file IfxFce_bf.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Fce_Registers_BitfieldsMask Bitfields mask and offset
* \ingroup IfxSfr_Fce_Registers
*
*/
#ifndef IFXFCE_BF_H
#define IFXFCE_BF_H 1
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fce_Registers_BitfieldsMask
* \{ */
/** \brief Length for Ifx_FCE_CLC_Bits.DISR */
#define IFX_FCE_CLC_DISR_LEN (1u)
/** \brief Mask for Ifx_FCE_CLC_Bits.DISR */
#define IFX_FCE_CLC_DISR_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CLC_Bits.DISR */
#define IFX_FCE_CLC_DISR_OFF (0u)
/** \brief Length for Ifx_FCE_CLC_Bits.DISS */
#define IFX_FCE_CLC_DISS_LEN (1u)
/** \brief Mask for Ifx_FCE_CLC_Bits.DISS */
#define IFX_FCE_CLC_DISS_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CLC_Bits.DISS */
#define IFX_FCE_CLC_DISS_OFF (1u)
/** \brief Length for Ifx_FCE_ID_Bits.MOD_REV */
#define IFX_FCE_ID_MOD_REV_LEN (8u)
/** \brief Mask for Ifx_FCE_ID_Bits.MOD_REV */
#define IFX_FCE_ID_MOD_REV_MSK (0xffu)
/** \brief Offset for Ifx_FCE_ID_Bits.MOD_REV */
#define IFX_FCE_ID_MOD_REV_OFF (0u)
/** \brief Length for Ifx_FCE_ID_Bits.MOD_TYPE */
#define IFX_FCE_ID_MOD_TYPE_LEN (8u)
/** \brief Mask for Ifx_FCE_ID_Bits.MOD_TYPE */
#define IFX_FCE_ID_MOD_TYPE_MSK (0xffu)
/** \brief Offset for Ifx_FCE_ID_Bits.MOD_TYPE */
#define IFX_FCE_ID_MOD_TYPE_OFF (8u)
/** \brief Length for Ifx_FCE_ID_Bits.MOD_NUMBER */
#define IFX_FCE_ID_MOD_NUMBER_LEN (16u)
/** \brief Mask for Ifx_FCE_ID_Bits.MOD_NUMBER */
#define IFX_FCE_ID_MOD_NUMBER_MSK (0xffffu)
/** \brief Offset for Ifx_FCE_ID_Bits.MOD_NUMBER */
#define IFX_FCE_ID_MOD_NUMBER_OFF (16u)
/** \brief Length for Ifx_FCE_CHSTS_Bits.CH0 */
#define IFX_FCE_CHSTS_CH0_LEN (1u)
/** \brief Mask for Ifx_FCE_CHSTS_Bits.CH0 */
#define IFX_FCE_CHSTS_CH0_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CHSTS_Bits.CH0 */
#define IFX_FCE_CHSTS_CH0_OFF (0u)
/** \brief Length for Ifx_FCE_CHSTS_Bits.CH1 */
#define IFX_FCE_CHSTS_CH1_LEN (1u)
/** \brief Mask for Ifx_FCE_CHSTS_Bits.CH1 */
#define IFX_FCE_CHSTS_CH1_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CHSTS_Bits.CH1 */
#define IFX_FCE_CHSTS_CH1_OFF (1u)
/** \brief Length for Ifx_FCE_CHSTS_Bits.CH2 */
#define IFX_FCE_CHSTS_CH2_LEN (1u)
/** \brief Mask for Ifx_FCE_CHSTS_Bits.CH2 */
#define IFX_FCE_CHSTS_CH2_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CHSTS_Bits.CH2 */
#define IFX_FCE_CHSTS_CH2_OFF (2u)
/** \brief Length for Ifx_FCE_CHSTS_Bits.CH3 */
#define IFX_FCE_CHSTS_CH3_LEN (1u)
/** \brief Mask for Ifx_FCE_CHSTS_Bits.CH3 */
#define IFX_FCE_CHSTS_CH3_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CHSTS_Bits.CH3 */
#define IFX_FCE_CHSTS_CH3_OFF (3u)
/** \brief Length for Ifx_FCE_CHSTS_Bits.CH4 */
#define IFX_FCE_CHSTS_CH4_LEN (1u)
/** \brief Mask for Ifx_FCE_CHSTS_Bits.CH4 */
#define IFX_FCE_CHSTS_CH4_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CHSTS_Bits.CH4 */
#define IFX_FCE_CHSTS_CH4_OFF (4u)
/** \brief Length for Ifx_FCE_CHSTS_Bits.CH5 */
#define IFX_FCE_CHSTS_CH5_LEN (1u)
/** \brief Mask for Ifx_FCE_CHSTS_Bits.CH5 */
#define IFX_FCE_CHSTS_CH5_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CHSTS_Bits.CH5 */
#define IFX_FCE_CHSTS_CH5_OFF (5u)
/** \brief Length for Ifx_FCE_CHSTS_Bits.CH6 */
#define IFX_FCE_CHSTS_CH6_LEN (1u)
/** \brief Mask for Ifx_FCE_CHSTS_Bits.CH6 */
#define IFX_FCE_CHSTS_CH6_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CHSTS_Bits.CH6 */
#define IFX_FCE_CHSTS_CH6_OFF (6u)
/** \brief Length for Ifx_FCE_CHSTS_Bits.CH7 */
#define IFX_FCE_CHSTS_CH7_LEN (1u)
/** \brief Mask for Ifx_FCE_CHSTS_Bits.CH7 */
#define IFX_FCE_CHSTS_CH7_MSK (0x1u)
/** \brief Offset for Ifx_FCE_CHSTS_Bits.CH7 */
#define IFX_FCE_CHSTS_CH7_OFF (7u)
/** \brief Length for Ifx_FCE_KRSTCLR_Bits.CLR */
#define IFX_FCE_KRSTCLR_CLR_LEN (1u)
/** \brief Mask for Ifx_FCE_KRSTCLR_Bits.CLR */
#define IFX_FCE_KRSTCLR_CLR_MSK (0x1u)
/** \brief Offset for Ifx_FCE_KRSTCLR_Bits.CLR */
#define IFX_FCE_KRSTCLR_CLR_OFF (0u)
/** \brief Length for Ifx_FCE_KRST1_Bits.RST */
#define IFX_FCE_KRST1_RST_LEN (1u)
/** \brief Mask for Ifx_FCE_KRST1_Bits.RST */
#define IFX_FCE_KRST1_RST_MSK (0x1u)
/** \brief Offset for Ifx_FCE_KRST1_Bits.RST */
#define IFX_FCE_KRST1_RST_OFF (0u)
/** \brief Length for Ifx_FCE_KRST0_Bits.RST */
#define IFX_FCE_KRST0_RST_LEN (1u)
/** \brief Mask for Ifx_FCE_KRST0_Bits.RST */
#define IFX_FCE_KRST0_RST_MSK (0x1u)
/** \brief Offset for Ifx_FCE_KRST0_Bits.RST */
#define IFX_FCE_KRST0_RST_OFF (0u)
/** \brief Length for Ifx_FCE_KRST0_Bits.RSTSTAT */
#define IFX_FCE_KRST0_RSTSTAT_LEN (1u)
/** \brief Mask for Ifx_FCE_KRST0_Bits.RSTSTAT */
#define IFX_FCE_KRST0_RSTSTAT_MSK (0x1u)
/** \brief Offset for Ifx_FCE_KRST0_Bits.RSTSTAT */
#define IFX_FCE_KRST0_RSTSTAT_OFF (1u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN0 */
#define IFX_FCE_ACCEN0_EN0_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN0 */
#define IFX_FCE_ACCEN0_EN0_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN0 */
#define IFX_FCE_ACCEN0_EN0_OFF (0u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN1 */
#define IFX_FCE_ACCEN0_EN1_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN1 */
#define IFX_FCE_ACCEN0_EN1_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN1 */
#define IFX_FCE_ACCEN0_EN1_OFF (1u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN2 */
#define IFX_FCE_ACCEN0_EN2_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN2 */
#define IFX_FCE_ACCEN0_EN2_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN2 */
#define IFX_FCE_ACCEN0_EN2_OFF (2u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN3 */
#define IFX_FCE_ACCEN0_EN3_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN3 */
#define IFX_FCE_ACCEN0_EN3_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN3 */
#define IFX_FCE_ACCEN0_EN3_OFF (3u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN4 */
#define IFX_FCE_ACCEN0_EN4_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN4 */
#define IFX_FCE_ACCEN0_EN4_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN4 */
#define IFX_FCE_ACCEN0_EN4_OFF (4u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN5 */
#define IFX_FCE_ACCEN0_EN5_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN5 */
#define IFX_FCE_ACCEN0_EN5_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN5 */
#define IFX_FCE_ACCEN0_EN5_OFF (5u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN6 */
#define IFX_FCE_ACCEN0_EN6_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN6 */
#define IFX_FCE_ACCEN0_EN6_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN6 */
#define IFX_FCE_ACCEN0_EN6_OFF (6u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN7 */
#define IFX_FCE_ACCEN0_EN7_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN7 */
#define IFX_FCE_ACCEN0_EN7_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN7 */
#define IFX_FCE_ACCEN0_EN7_OFF (7u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN8 */
#define IFX_FCE_ACCEN0_EN8_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN8 */
#define IFX_FCE_ACCEN0_EN8_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN8 */
#define IFX_FCE_ACCEN0_EN8_OFF (8u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN9 */
#define IFX_FCE_ACCEN0_EN9_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN9 */
#define IFX_FCE_ACCEN0_EN9_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN9 */
#define IFX_FCE_ACCEN0_EN9_OFF (9u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN10 */
#define IFX_FCE_ACCEN0_EN10_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN10 */
#define IFX_FCE_ACCEN0_EN10_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN10 */
#define IFX_FCE_ACCEN0_EN10_OFF (10u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN11 */
#define IFX_FCE_ACCEN0_EN11_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN11 */
#define IFX_FCE_ACCEN0_EN11_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN11 */
#define IFX_FCE_ACCEN0_EN11_OFF (11u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN12 */
#define IFX_FCE_ACCEN0_EN12_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN12 */
#define IFX_FCE_ACCEN0_EN12_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN12 */
#define IFX_FCE_ACCEN0_EN12_OFF (12u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN13 */
#define IFX_FCE_ACCEN0_EN13_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN13 */
#define IFX_FCE_ACCEN0_EN13_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN13 */
#define IFX_FCE_ACCEN0_EN13_OFF (13u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN14 */
#define IFX_FCE_ACCEN0_EN14_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN14 */
#define IFX_FCE_ACCEN0_EN14_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN14 */
#define IFX_FCE_ACCEN0_EN14_OFF (14u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN15 */
#define IFX_FCE_ACCEN0_EN15_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN15 */
#define IFX_FCE_ACCEN0_EN15_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN15 */
#define IFX_FCE_ACCEN0_EN15_OFF (15u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN16 */
#define IFX_FCE_ACCEN0_EN16_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN16 */
#define IFX_FCE_ACCEN0_EN16_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN16 */
#define IFX_FCE_ACCEN0_EN16_OFF (16u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN17 */
#define IFX_FCE_ACCEN0_EN17_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN17 */
#define IFX_FCE_ACCEN0_EN17_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN17 */
#define IFX_FCE_ACCEN0_EN17_OFF (17u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN18 */
#define IFX_FCE_ACCEN0_EN18_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN18 */
#define IFX_FCE_ACCEN0_EN18_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN18 */
#define IFX_FCE_ACCEN0_EN18_OFF (18u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN19 */
#define IFX_FCE_ACCEN0_EN19_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN19 */
#define IFX_FCE_ACCEN0_EN19_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN19 */
#define IFX_FCE_ACCEN0_EN19_OFF (19u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN20 */
#define IFX_FCE_ACCEN0_EN20_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN20 */
#define IFX_FCE_ACCEN0_EN20_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN20 */
#define IFX_FCE_ACCEN0_EN20_OFF (20u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN21 */
#define IFX_FCE_ACCEN0_EN21_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN21 */
#define IFX_FCE_ACCEN0_EN21_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN21 */
#define IFX_FCE_ACCEN0_EN21_OFF (21u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN22 */
#define IFX_FCE_ACCEN0_EN22_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN22 */
#define IFX_FCE_ACCEN0_EN22_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN22 */
#define IFX_FCE_ACCEN0_EN22_OFF (22u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN23 */
#define IFX_FCE_ACCEN0_EN23_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN23 */
#define IFX_FCE_ACCEN0_EN23_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN23 */
#define IFX_FCE_ACCEN0_EN23_OFF (23u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN24 */
#define IFX_FCE_ACCEN0_EN24_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN24 */
#define IFX_FCE_ACCEN0_EN24_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN24 */
#define IFX_FCE_ACCEN0_EN24_OFF (24u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN25 */
#define IFX_FCE_ACCEN0_EN25_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN25 */
#define IFX_FCE_ACCEN0_EN25_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN25 */
#define IFX_FCE_ACCEN0_EN25_OFF (25u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN26 */
#define IFX_FCE_ACCEN0_EN26_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN26 */
#define IFX_FCE_ACCEN0_EN26_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN26 */
#define IFX_FCE_ACCEN0_EN26_OFF (26u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN27 */
#define IFX_FCE_ACCEN0_EN27_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN27 */
#define IFX_FCE_ACCEN0_EN27_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN27 */
#define IFX_FCE_ACCEN0_EN27_OFF (27u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN28 */
#define IFX_FCE_ACCEN0_EN28_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN28 */
#define IFX_FCE_ACCEN0_EN28_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN28 */
#define IFX_FCE_ACCEN0_EN28_OFF (28u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN29 */
#define IFX_FCE_ACCEN0_EN29_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN29 */
#define IFX_FCE_ACCEN0_EN29_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN29 */
#define IFX_FCE_ACCEN0_EN29_OFF (29u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN30 */
#define IFX_FCE_ACCEN0_EN30_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN30 */
#define IFX_FCE_ACCEN0_EN30_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN30 */
#define IFX_FCE_ACCEN0_EN30_OFF (30u)
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN31 */
#define IFX_FCE_ACCEN0_EN31_LEN (1u)
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN31 */
#define IFX_FCE_ACCEN0_EN31_MSK (0x1u)
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN31 */
#define IFX_FCE_ACCEN0_EN31_OFF (31u)
/** \brief Length for Ifx_FCE_IN_IR_Bits.IR */
#define IFX_FCE_IN_IR_IR_LEN (32u)
/** \brief Mask for Ifx_FCE_IN_IR_Bits.IR */
#define IFX_FCE_IN_IR_IR_MSK (0xffffffffu)
/** \brief Offset for Ifx_FCE_IN_IR_Bits.IR */
#define IFX_FCE_IN_IR_IR_OFF (0u)
/** \brief Length for Ifx_FCE_IN_RES_Bits.RES */
#define IFX_FCE_IN_RES_RES_LEN (32u)
/** \brief Mask for Ifx_FCE_IN_RES_Bits.RES */
#define IFX_FCE_IN_RES_RES_MSK (0xffffffffu)
/** \brief Offset for Ifx_FCE_IN_RES_Bits.RES */
#define IFX_FCE_IN_RES_RES_OFF (0u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.CMI */
#define IFX_FCE_IN_CFG_CMI_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.CMI */
#define IFX_FCE_IN_CFG_CMI_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.CMI */
#define IFX_FCE_IN_CFG_CMI_OFF (0u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.CEI */
#define IFX_FCE_IN_CFG_CEI_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.CEI */
#define IFX_FCE_IN_CFG_CEI_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.CEI */
#define IFX_FCE_IN_CFG_CEI_OFF (1u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.LEI */
#define IFX_FCE_IN_CFG_LEI_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.LEI */
#define IFX_FCE_IN_CFG_LEI_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.LEI */
#define IFX_FCE_IN_CFG_LEI_OFF (2u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.BEI */
#define IFX_FCE_IN_CFG_BEI_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.BEI */
#define IFX_FCE_IN_CFG_BEI_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.BEI */
#define IFX_FCE_IN_CFG_BEI_OFF (3u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.CCE */
#define IFX_FCE_IN_CFG_CCE_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.CCE */
#define IFX_FCE_IN_CFG_CCE_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.CCE */
#define IFX_FCE_IN_CFG_CCE_OFF (4u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.ALR */
#define IFX_FCE_IN_CFG_ALR_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.ALR */
#define IFX_FCE_IN_CFG_ALR_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.ALR */
#define IFX_FCE_IN_CFG_ALR_OFF (5u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.REFIN */
#define IFX_FCE_IN_CFG_REFIN_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.REFIN */
#define IFX_FCE_IN_CFG_REFIN_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.REFIN */
#define IFX_FCE_IN_CFG_REFIN_OFF (8u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.REFOUT */
#define IFX_FCE_IN_CFG_REFOUT_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.REFOUT */
#define IFX_FCE_IN_CFG_REFOUT_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.REFOUT */
#define IFX_FCE_IN_CFG_REFOUT_OFF (9u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.XSEL */
#define IFX_FCE_IN_CFG_XSEL_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.XSEL */
#define IFX_FCE_IN_CFG_XSEL_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.XSEL */
#define IFX_FCE_IN_CFG_XSEL_OFF (10u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.BYTESWAP */
#define IFX_FCE_IN_CFG_BYTESWAP_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.BYTESWAP */
#define IFX_FCE_IN_CFG_BYTESWAP_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.BYTESWAP */
#define IFX_FCE_IN_CFG_BYTESWAP_OFF (11u)
/** \brief Length for Ifx_FCE_IN_CFG_Bits.KERNEL */
#define IFX_FCE_IN_CFG_KERNEL_LEN (4u)
/** \brief Mask for Ifx_FCE_IN_CFG_Bits.KERNEL */
#define IFX_FCE_IN_CFG_KERNEL_MSK (0xfu)
/** \brief Offset for Ifx_FCE_IN_CFG_Bits.KERNEL */
#define IFX_FCE_IN_CFG_KERNEL_OFF (16u)
/** \brief Length for Ifx_FCE_IN_STS_Bits.CMF */
#define IFX_FCE_IN_STS_CMF_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_STS_Bits.CMF */
#define IFX_FCE_IN_STS_CMF_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_STS_Bits.CMF */
#define IFX_FCE_IN_STS_CMF_OFF (0u)
/** \brief Length for Ifx_FCE_IN_STS_Bits.CEF */
#define IFX_FCE_IN_STS_CEF_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_STS_Bits.CEF */
#define IFX_FCE_IN_STS_CEF_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_STS_Bits.CEF */
#define IFX_FCE_IN_STS_CEF_OFF (1u)
/** \brief Length for Ifx_FCE_IN_STS_Bits.LEF */
#define IFX_FCE_IN_STS_LEF_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_STS_Bits.LEF */
#define IFX_FCE_IN_STS_LEF_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_STS_Bits.LEF */
#define IFX_FCE_IN_STS_LEF_OFF (2u)
/** \brief Length for Ifx_FCE_IN_STS_Bits.BEF */
#define IFX_FCE_IN_STS_BEF_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_STS_Bits.BEF */
#define IFX_FCE_IN_STS_BEF_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_STS_Bits.BEF */
#define IFX_FCE_IN_STS_BEF_OFF (3u)
/** \brief Length for Ifx_FCE_IN_LENGTH_Bits.LENGTH */
#define IFX_FCE_IN_LENGTH_LENGTH_LEN (16u)
/** \brief Mask for Ifx_FCE_IN_LENGTH_Bits.LENGTH */
#define IFX_FCE_IN_LENGTH_LENGTH_MSK (0xffffu)
/** \brief Offset for Ifx_FCE_IN_LENGTH_Bits.LENGTH */
#define IFX_FCE_IN_LENGTH_LENGTH_OFF (0u)
/** \brief Length for Ifx_FCE_IN_CHECK_Bits.CHECK */
#define IFX_FCE_IN_CHECK_CHECK_LEN (32u)
/** \brief Mask for Ifx_FCE_IN_CHECK_Bits.CHECK */
#define IFX_FCE_IN_CHECK_CHECK_MSK (0xffffffffu)
/** \brief Offset for Ifx_FCE_IN_CHECK_Bits.CHECK */
#define IFX_FCE_IN_CHECK_CHECK_OFF (0u)
/** \brief Length for Ifx_FCE_IN_CRC_Bits.CRC */
#define IFX_FCE_IN_CRC_CRC_LEN (32u)
/** \brief Mask for Ifx_FCE_IN_CRC_Bits.CRC */
#define IFX_FCE_IN_CRC_CRC_MSK (0xffffffffu)
/** \brief Offset for Ifx_FCE_IN_CRC_Bits.CRC */
#define IFX_FCE_IN_CRC_CRC_OFF (0u)
/** \brief Length for Ifx_FCE_IN_CTR_Bits.FCM */
#define IFX_FCE_IN_CTR_FCM_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CTR_Bits.FCM */
#define IFX_FCE_IN_CTR_FCM_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CTR_Bits.FCM */
#define IFX_FCE_IN_CTR_FCM_OFF (0u)
/** \brief Length for Ifx_FCE_IN_CTR_Bits.FRM_CFG */
#define IFX_FCE_IN_CTR_FRM_CFG_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CTR_Bits.FRM_CFG */
#define IFX_FCE_IN_CTR_FRM_CFG_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CTR_Bits.FRM_CFG */
#define IFX_FCE_IN_CTR_FRM_CFG_OFF (1u)
/** \brief Length for Ifx_FCE_IN_CTR_Bits.FRM_CHECK */
#define IFX_FCE_IN_CTR_FRM_CHECK_LEN (1u)
/** \brief Mask for Ifx_FCE_IN_CTR_Bits.FRM_CHECK */
#define IFX_FCE_IN_CTR_FRM_CHECK_MSK (0x1u)
/** \brief Offset for Ifx_FCE_IN_CTR_Bits.FRM_CHECK */
#define IFX_FCE_IN_CTR_FRM_CHECK_OFF (2u)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXFCE_BF_H */

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/**
* \file IfxFce_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Fce_Registers_Cfg Fce address
* \ingroup IfxSfr_Fce_Registers
*
* \defgroup IfxSfr_Fce_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Fce_Registers_Cfg
*
* \defgroup IfxSfr_Fce_Registers_Cfg_Fce 2-FCE
* \ingroup IfxSfr_Fce_Registers_Cfg
*
*
*/
#ifndef IFXFCE_REG_H
#define IFXFCE_REG_H 1
/******************************************************************************/
#include "IfxFce_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fce_Registers_Cfg_BaseAddress
* \{ */
/** \brief FCE object */
#define MODULE_FCE /*lint --e(923, 9078)*/ ((*(Ifx_FCE*)0xF0000000u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fce_Registers_Cfg_Fce
* \{ */
/** \brief 0, Clock Control Register */
#define FCE_CLC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_CLC*)0xF0000000u)
/** \brief 8, Module Identification Register */
#define FCE_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_ID*)0xF0000008u)
/** \brief 20, Channels Status Register */
#define FCE_CHSTS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_CHSTS*)0xF0000020u)
/** \brief EC, Kernel Reset Status Clear Register */
#define FCE_KRSTCLR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_KRSTCLR*)0xF00000ECu)
/** \brief F0, Kernel Reset Register 1 */
#define FCE_KRST1 /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_KRST1*)0xF00000F0u)
/** \brief F4, Kernel Reset Register 0 */
#define FCE_KRST0 /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_KRST0*)0xF00000F4u)
/** \brief F8, Access Enable Register 1 */
#define FCE_ACCEN1 /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_ACCEN1*)0xF00000F8u)
/** \brief FC, Access Enable Register 0 */
#define FCE_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_ACCEN0*)0xF00000FCu)
/** \brief 100, Input Register 0 */
#define FCE_IN0_IR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_IR*)0xF0000100u)
/** Alias (User Manual Name) for FCE_IN0_IR.
* To use register names with standard convension, please use FCE_IN0_IR.
*/
#define FCE_IR0 (FCE_IN0_IR)
/** \brief 104, CRC Result Register 0 */
#define FCE_IN0_RES /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_RES*)0xF0000104u)
/** Alias (User Manual Name) for FCE_IN0_RES.
* To use register names with standard convension, please use FCE_IN0_RES.
*/
#define FCE_RES0 (FCE_IN0_RES)
/** \brief 108, CRC Configuration Register 0 */
#define FCE_IN0_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CFG*)0xF0000108u)
/** Alias (User Manual Name) for FCE_IN0_CFG.
* To use register names with standard convension, please use FCE_IN0_CFG.
*/
#define FCE_CFG0 (FCE_IN0_CFG)
/** \brief 10C, CRC Status Register 0 */
#define FCE_IN0_STS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_STS*)0xF000010Cu)
/** Alias (User Manual Name) for FCE_IN0_STS.
* To use register names with standard convension, please use FCE_IN0_STS.
*/
#define FCE_STS0 (FCE_IN0_STS)
/** \brief 110, CRC Length Register 0 */
#define FCE_IN0_LENGTH /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_LENGTH*)0xF0000110u)
/** Alias (User Manual Name) for FCE_IN0_LENGTH.
* To use register names with standard convension, please use FCE_IN0_LENGTH.
*/
#define FCE_LENGTH0 (FCE_IN0_LENGTH)
/** \brief 114, CRC Check Register 0 */
#define FCE_IN0_CHECK /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CHECK*)0xF0000114u)
/** Alias (User Manual Name) for FCE_IN0_CHECK.
* To use register names with standard convension, please use FCE_IN0_CHECK.
*/
#define FCE_CHECK0 (FCE_IN0_CHECK)
/** \brief 118, CRC Regsister 0 */
#define FCE_IN0_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CRC*)0xF0000118u)
/** Alias (User Manual Name) for FCE_IN0_CRC.
* To use register names with standard convension, please use FCE_IN0_CRC.
*/
#define FCE_CRC0 (FCE_IN0_CRC)
/** \brief 11C, CRC Test Register 0 */
#define FCE_IN0_CTR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CTR*)0xF000011Cu)
/** Alias (User Manual Name) for FCE_IN0_CTR.
* To use register names with standard convension, please use FCE_IN0_CTR.
*/
#define FCE_CTR0 (FCE_IN0_CTR)
/** \brief 120, Input Register 1 */
#define FCE_IN1_IR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_IR*)0xF0000120u)
/** Alias (User Manual Name) for FCE_IN1_IR.
* To use register names with standard convension, please use FCE_IN1_IR.
*/
#define FCE_IR1 (FCE_IN1_IR)
/** \brief 124, CRC Result Register 1 */
#define FCE_IN1_RES /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_RES*)0xF0000124u)
/** Alias (User Manual Name) for FCE_IN1_RES.
* To use register names with standard convension, please use FCE_IN1_RES.
*/
#define FCE_RES1 (FCE_IN1_RES)
/** \brief 128, CRC Configuration Register 1 */
#define FCE_IN1_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CFG*)0xF0000128u)
/** Alias (User Manual Name) for FCE_IN1_CFG.
* To use register names with standard convension, please use FCE_IN1_CFG.
*/
#define FCE_CFG1 (FCE_IN1_CFG)
/** \brief 12C, CRC Status Register 1 */
#define FCE_IN1_STS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_STS*)0xF000012Cu)
/** Alias (User Manual Name) for FCE_IN1_STS.
* To use register names with standard convension, please use FCE_IN1_STS.
*/
#define FCE_STS1 (FCE_IN1_STS)
/** \brief 130, CRC Length Register 1 */
#define FCE_IN1_LENGTH /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_LENGTH*)0xF0000130u)
/** Alias (User Manual Name) for FCE_IN1_LENGTH.
* To use register names with standard convension, please use FCE_IN1_LENGTH.
*/
#define FCE_LENGTH1 (FCE_IN1_LENGTH)
/** \brief 134, CRC Check Register 1 */
#define FCE_IN1_CHECK /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CHECK*)0xF0000134u)
/** Alias (User Manual Name) for FCE_IN1_CHECK.
* To use register names with standard convension, please use FCE_IN1_CHECK.
*/
#define FCE_CHECK1 (FCE_IN1_CHECK)
/** \brief 138, CRC Regsister 1 */
#define FCE_IN1_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CRC*)0xF0000138u)
/** Alias (User Manual Name) for FCE_IN1_CRC.
* To use register names with standard convension, please use FCE_IN1_CRC.
*/
#define FCE_CRC1 (FCE_IN1_CRC)
/** \brief 13C, CRC Test Register 1 */
#define FCE_IN1_CTR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CTR*)0xF000013Cu)
/** Alias (User Manual Name) for FCE_IN1_CTR.
* To use register names with standard convension, please use FCE_IN1_CTR.
*/
#define FCE_CTR1 (FCE_IN1_CTR)
/** \brief 140, Input Register 2 */
#define FCE_IN2_IR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_IR*)0xF0000140u)
/** Alias (User Manual Name) for FCE_IN2_IR.
* To use register names with standard convension, please use FCE_IN2_IR.
*/
#define FCE_IR2 (FCE_IN2_IR)
/** \brief 144, CRC Result Register 2 */
#define FCE_IN2_RES /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_RES*)0xF0000144u)
/** Alias (User Manual Name) for FCE_IN2_RES.
* To use register names with standard convension, please use FCE_IN2_RES.
*/
#define FCE_RES2 (FCE_IN2_RES)
/** \brief 148, CRC Configuration Register 2 */
#define FCE_IN2_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CFG*)0xF0000148u)
/** Alias (User Manual Name) for FCE_IN2_CFG.
* To use register names with standard convension, please use FCE_IN2_CFG.
*/
#define FCE_CFG2 (FCE_IN2_CFG)
/** \brief 14C, CRC Status Register 2 */
#define FCE_IN2_STS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_STS*)0xF000014Cu)
/** Alias (User Manual Name) for FCE_IN2_STS.
* To use register names with standard convension, please use FCE_IN2_STS.
*/
#define FCE_STS2 (FCE_IN2_STS)
/** \brief 150, CRC Length Register 2 */
#define FCE_IN2_LENGTH /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_LENGTH*)0xF0000150u)
/** Alias (User Manual Name) for FCE_IN2_LENGTH.
* To use register names with standard convension, please use FCE_IN2_LENGTH.
*/
#define FCE_LENGTH2 (FCE_IN2_LENGTH)
/** \brief 154, CRC Check Register 2 */
#define FCE_IN2_CHECK /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CHECK*)0xF0000154u)
/** Alias (User Manual Name) for FCE_IN2_CHECK.
* To use register names with standard convension, please use FCE_IN2_CHECK.
*/
#define FCE_CHECK2 (FCE_IN2_CHECK)
/** \brief 158, CRC Regsister 2 */
#define FCE_IN2_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CRC*)0xF0000158u)
/** Alias (User Manual Name) for FCE_IN2_CRC.
* To use register names with standard convension, please use FCE_IN2_CRC.
*/
#define FCE_CRC2 (FCE_IN2_CRC)
/** \brief 15C, CRC Test Register 2 */
#define FCE_IN2_CTR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CTR*)0xF000015Cu)
/** Alias (User Manual Name) for FCE_IN2_CTR.
* To use register names with standard convension, please use FCE_IN2_CTR.
*/
#define FCE_CTR2 (FCE_IN2_CTR)
/** \brief 160, Input Register 3 */
#define FCE_IN3_IR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_IR*)0xF0000160u)
/** Alias (User Manual Name) for FCE_IN3_IR.
* To use register names with standard convension, please use FCE_IN3_IR.
*/
#define FCE_IR3 (FCE_IN3_IR)
/** \brief 164, CRC Result Register 3 */
#define FCE_IN3_RES /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_RES*)0xF0000164u)
/** Alias (User Manual Name) for FCE_IN3_RES.
* To use register names with standard convension, please use FCE_IN3_RES.
*/
#define FCE_RES3 (FCE_IN3_RES)
/** \brief 168, CRC Configuration Register 3 */
#define FCE_IN3_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CFG*)0xF0000168u)
/** Alias (User Manual Name) for FCE_IN3_CFG.
* To use register names with standard convension, please use FCE_IN3_CFG.
*/
#define FCE_CFG3 (FCE_IN3_CFG)
/** \brief 16C, CRC Status Register 3 */
#define FCE_IN3_STS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_STS*)0xF000016Cu)
/** Alias (User Manual Name) for FCE_IN3_STS.
* To use register names with standard convension, please use FCE_IN3_STS.
*/
#define FCE_STS3 (FCE_IN3_STS)
/** \brief 170, CRC Length Register 3 */
#define FCE_IN3_LENGTH /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_LENGTH*)0xF0000170u)
/** Alias (User Manual Name) for FCE_IN3_LENGTH.
* To use register names with standard convension, please use FCE_IN3_LENGTH.
*/
#define FCE_LENGTH3 (FCE_IN3_LENGTH)
/** \brief 174, CRC Check Register 3 */
#define FCE_IN3_CHECK /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CHECK*)0xF0000174u)
/** Alias (User Manual Name) for FCE_IN3_CHECK.
* To use register names with standard convension, please use FCE_IN3_CHECK.
*/
#define FCE_CHECK3 (FCE_IN3_CHECK)
/** \brief 178, CRC Regsister 3 */
#define FCE_IN3_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CRC*)0xF0000178u)
/** Alias (User Manual Name) for FCE_IN3_CRC.
* To use register names with standard convension, please use FCE_IN3_CRC.
*/
#define FCE_CRC3 (FCE_IN3_CRC)
/** \brief 17C, CRC Test Register 3 */
#define FCE_IN3_CTR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CTR*)0xF000017Cu)
/** Alias (User Manual Name) for FCE_IN3_CTR.
* To use register names with standard convension, please use FCE_IN3_CTR.
*/
#define FCE_CTR3 (FCE_IN3_CTR)
/** \brief 180, Input Register 4 */
#define FCE_IN4_IR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_IR*)0xF0000180u)
/** Alias (User Manual Name) for FCE_IN4_IR.
* To use register names with standard convension, please use FCE_IN4_IR.
*/
#define FCE_IR4 (FCE_IN4_IR)
/** \brief 184, CRC Result Register 4 */
#define FCE_IN4_RES /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_RES*)0xF0000184u)
/** Alias (User Manual Name) for FCE_IN4_RES.
* To use register names with standard convension, please use FCE_IN4_RES.
*/
#define FCE_RES4 (FCE_IN4_RES)
/** \brief 188, CRC Configuration Register 4 */
#define FCE_IN4_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CFG*)0xF0000188u)
/** Alias (User Manual Name) for FCE_IN4_CFG.
* To use register names with standard convension, please use FCE_IN4_CFG.
*/
#define FCE_CFG4 (FCE_IN4_CFG)
/** \brief 18C, CRC Status Register 4 */
#define FCE_IN4_STS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_STS*)0xF000018Cu)
/** Alias (User Manual Name) for FCE_IN4_STS.
* To use register names with standard convension, please use FCE_IN4_STS.
*/
#define FCE_STS4 (FCE_IN4_STS)
/** \brief 190, CRC Length Register 4 */
#define FCE_IN4_LENGTH /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_LENGTH*)0xF0000190u)
/** Alias (User Manual Name) for FCE_IN4_LENGTH.
* To use register names with standard convension, please use FCE_IN4_LENGTH.
*/
#define FCE_LENGTH4 (FCE_IN4_LENGTH)
/** \brief 194, CRC Check Register 4 */
#define FCE_IN4_CHECK /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CHECK*)0xF0000194u)
/** Alias (User Manual Name) for FCE_IN4_CHECK.
* To use register names with standard convension, please use FCE_IN4_CHECK.
*/
#define FCE_CHECK4 (FCE_IN4_CHECK)
/** \brief 198, CRC Regsister 4 */
#define FCE_IN4_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CRC*)0xF0000198u)
/** Alias (User Manual Name) for FCE_IN4_CRC.
* To use register names with standard convension, please use FCE_IN4_CRC.
*/
#define FCE_CRC4 (FCE_IN4_CRC)
/** \brief 19C, CRC Test Register 4 */
#define FCE_IN4_CTR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CTR*)0xF000019Cu)
/** Alias (User Manual Name) for FCE_IN4_CTR.
* To use register names with standard convension, please use FCE_IN4_CTR.
*/
#define FCE_CTR4 (FCE_IN4_CTR)
/** \brief 1A0, Input Register 5 */
#define FCE_IN5_IR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_IR*)0xF00001A0u)
/** Alias (User Manual Name) for FCE_IN5_IR.
* To use register names with standard convension, please use FCE_IN5_IR.
*/
#define FCE_IR5 (FCE_IN5_IR)
/** \brief 1A4, CRC Result Register 5 */
#define FCE_IN5_RES /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_RES*)0xF00001A4u)
/** Alias (User Manual Name) for FCE_IN5_RES.
* To use register names with standard convension, please use FCE_IN5_RES.
*/
#define FCE_RES5 (FCE_IN5_RES)
/** \brief 1A8, CRC Configuration Register 5 */
#define FCE_IN5_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CFG*)0xF00001A8u)
/** Alias (User Manual Name) for FCE_IN5_CFG.
* To use register names with standard convension, please use FCE_IN5_CFG.
*/
#define FCE_CFG5 (FCE_IN5_CFG)
/** \brief 1AC, CRC Status Register 5 */
#define FCE_IN5_STS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_STS*)0xF00001ACu)
/** Alias (User Manual Name) for FCE_IN5_STS.
* To use register names with standard convension, please use FCE_IN5_STS.
*/
#define FCE_STS5 (FCE_IN5_STS)
/** \brief 1B0, CRC Length Register 5 */
#define FCE_IN5_LENGTH /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_LENGTH*)0xF00001B0u)
/** Alias (User Manual Name) for FCE_IN5_LENGTH.
* To use register names with standard convension, please use FCE_IN5_LENGTH.
*/
#define FCE_LENGTH5 (FCE_IN5_LENGTH)
/** \brief 1B4, CRC Check Register 5 */
#define FCE_IN5_CHECK /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CHECK*)0xF00001B4u)
/** Alias (User Manual Name) for FCE_IN5_CHECK.
* To use register names with standard convension, please use FCE_IN5_CHECK.
*/
#define FCE_CHECK5 (FCE_IN5_CHECK)
/** \brief 1B8, CRC Regsister 5 */
#define FCE_IN5_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CRC*)0xF00001B8u)
/** Alias (User Manual Name) for FCE_IN5_CRC.
* To use register names with standard convension, please use FCE_IN5_CRC.
*/
#define FCE_CRC5 (FCE_IN5_CRC)
/** \brief 1BC, CRC Test Register 5 */
#define FCE_IN5_CTR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CTR*)0xF00001BCu)
/** Alias (User Manual Name) for FCE_IN5_CTR.
* To use register names with standard convension, please use FCE_IN5_CTR.
*/
#define FCE_CTR5 (FCE_IN5_CTR)
/** \brief 1C0, Input Register 6 */
#define FCE_IN6_IR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_IR*)0xF00001C0u)
/** Alias (User Manual Name) for FCE_IN6_IR.
* To use register names with standard convension, please use FCE_IN6_IR.
*/
#define FCE_IR6 (FCE_IN6_IR)
/** \brief 1C4, CRC Result Register 6 */
#define FCE_IN6_RES /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_RES*)0xF00001C4u)
/** Alias (User Manual Name) for FCE_IN6_RES.
* To use register names with standard convension, please use FCE_IN6_RES.
*/
#define FCE_RES6 (FCE_IN6_RES)
/** \brief 1C8, CRC Configuration Register 6 */
#define FCE_IN6_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CFG*)0xF00001C8u)
/** Alias (User Manual Name) for FCE_IN6_CFG.
* To use register names with standard convension, please use FCE_IN6_CFG.
*/
#define FCE_CFG6 (FCE_IN6_CFG)
/** \brief 1CC, CRC Status Register 6 */
#define FCE_IN6_STS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_STS*)0xF00001CCu)
/** Alias (User Manual Name) for FCE_IN6_STS.
* To use register names with standard convension, please use FCE_IN6_STS.
*/
#define FCE_STS6 (FCE_IN6_STS)
/** \brief 1D0, CRC Length Register 6 */
#define FCE_IN6_LENGTH /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_LENGTH*)0xF00001D0u)
/** Alias (User Manual Name) for FCE_IN6_LENGTH.
* To use register names with standard convension, please use FCE_IN6_LENGTH.
*/
#define FCE_LENGTH6 (FCE_IN6_LENGTH)
/** \brief 1D4, CRC Check Register 6 */
#define FCE_IN6_CHECK /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CHECK*)0xF00001D4u)
/** Alias (User Manual Name) for FCE_IN6_CHECK.
* To use register names with standard convension, please use FCE_IN6_CHECK.
*/
#define FCE_CHECK6 (FCE_IN6_CHECK)
/** \brief 1D8, CRC Regsister 6 */
#define FCE_IN6_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CRC*)0xF00001D8u)
/** Alias (User Manual Name) for FCE_IN6_CRC.
* To use register names with standard convension, please use FCE_IN6_CRC.
*/
#define FCE_CRC6 (FCE_IN6_CRC)
/** \brief 1DC, CRC Test Register 6 */
#define FCE_IN6_CTR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CTR*)0xF00001DCu)
/** Alias (User Manual Name) for FCE_IN6_CTR.
* To use register names with standard convension, please use FCE_IN6_CTR.
*/
#define FCE_CTR6 (FCE_IN6_CTR)
/** \brief 1E0, Input Register 7 */
#define FCE_IN7_IR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_IR*)0xF00001E0u)
/** Alias (User Manual Name) for FCE_IN7_IR.
* To use register names with standard convension, please use FCE_IN7_IR.
*/
#define FCE_IR7 (FCE_IN7_IR)
/** \brief 1E4, CRC Result Register 7 */
#define FCE_IN7_RES /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_RES*)0xF00001E4u)
/** Alias (User Manual Name) for FCE_IN7_RES.
* To use register names with standard convension, please use FCE_IN7_RES.
*/
#define FCE_RES7 (FCE_IN7_RES)
/** \brief 1E8, CRC Configuration Register 7 */
#define FCE_IN7_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CFG*)0xF00001E8u)
/** Alias (User Manual Name) for FCE_IN7_CFG.
* To use register names with standard convension, please use FCE_IN7_CFG.
*/
#define FCE_CFG7 (FCE_IN7_CFG)
/** \brief 1EC, CRC Status Register 7 */
#define FCE_IN7_STS /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_STS*)0xF00001ECu)
/** Alias (User Manual Name) for FCE_IN7_STS.
* To use register names with standard convension, please use FCE_IN7_STS.
*/
#define FCE_STS7 (FCE_IN7_STS)
/** \brief 1F0, CRC Length Register 7 */
#define FCE_IN7_LENGTH /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_LENGTH*)0xF00001F0u)
/** Alias (User Manual Name) for FCE_IN7_LENGTH.
* To use register names with standard convension, please use FCE_IN7_LENGTH.
*/
#define FCE_LENGTH7 (FCE_IN7_LENGTH)
/** \brief 1F4, CRC Check Register 7 */
#define FCE_IN7_CHECK /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CHECK*)0xF00001F4u)
/** Alias (User Manual Name) for FCE_IN7_CHECK.
* To use register names with standard convension, please use FCE_IN7_CHECK.
*/
#define FCE_CHECK7 (FCE_IN7_CHECK)
/** \brief 1F8, CRC Regsister 7 */
#define FCE_IN7_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CRC*)0xF00001F8u)
/** Alias (User Manual Name) for FCE_IN7_CRC.
* To use register names with standard convension, please use FCE_IN7_CRC.
*/
#define FCE_CRC7 (FCE_IN7_CRC)
/** \brief 1FC, CRC Test Register 7 */
#define FCE_IN7_CTR /*lint --e(923, 9078)*/ (*(volatile Ifx_FCE_IN_CTR*)0xF00001FCu)
/** Alias (User Manual Name) for FCE_IN7_CTR.
* To use register names with standard convension, please use FCE_IN7_CTR.
*/
#define FCE_CTR7 (FCE_IN7_CTR)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXFCE_REG_H */

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/**
* \file IfxFce_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Fce_Registers Fce Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Fce_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Fce_Registers
*
* \defgroup IfxSfr_Fce_Registers_union Register unions
* \ingroup IfxSfr_Fce_Registers
*
* \defgroup IfxSfr_Fce_Registers_struct Memory map
* \ingroup IfxSfr_Fce_Registers
*/
#ifndef IFXFCE_REGDEF_H
#define IFXFCE_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fce_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_FCE_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_FCE_ACCEN0_Bits;
/** \brief Access Enable Register 1 */
typedef struct _Ifx_FCE_ACCEN1_Bits
{
Ifx_UReg_32Bit reserved_0:32; /**< \brief [31:0] \internal Reserved */
} Ifx_FCE_ACCEN1_Bits;
/** \brief Channels Status Register */
typedef struct _Ifx_FCE_CHSTS_Bits
{
Ifx_UReg_32Bit CH0:1; /**< \brief [0:0] Channel0 Status - CH0 (rh) */
Ifx_UReg_32Bit CH1:1; /**< \brief [1:1] Channel1 Status - CH1 (rh) */
Ifx_UReg_32Bit CH2:1; /**< \brief [2:2] Channel2 Status - CH2 (rh) */
Ifx_UReg_32Bit CH3:1; /**< \brief [3:3] Channel3 Status - CH3 (rh) */
Ifx_UReg_32Bit CH4:1; /**< \brief [4:4] Channel4 Status - CH4 (rh) */
Ifx_UReg_32Bit CH5:1; /**< \brief [5:5] Channel5 Status - CH5 (rh) */
Ifx_UReg_32Bit CH6:1; /**< \brief [6:6] Channel6 Status - CH6 (rh) */
Ifx_UReg_32Bit CH7:1; /**< \brief [7:7] Channel7 Status - CH7 (rh) */
Ifx_UReg_32Bit reserved_8:24; /**< \brief [31:8] \internal Reserved */
} Ifx_FCE_CHSTS_Bits;
/** \brief Clock Control Register */
typedef struct _Ifx_FCE_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_FCE_CLC_Bits;
/** \brief Module Identification Register */
typedef struct _Ifx_FCE_ID_Bits
{
Ifx_UReg_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number - MOD_REV (r) */
Ifx_UReg_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Type - MOD_TYPE (r) */
Ifx_UReg_32Bit MOD_NUMBER:16; /**< \brief [31:16] Module Number Value - MOD_NUMBER (r) */
} Ifx_FCE_ID_Bits;
/** \brief CRC Configuration Register ${i} */
typedef struct _Ifx_FCE_IN_CFG_Bits
{
Ifx_UReg_32Bit CMI:1; /**< \brief [0:0] CRC Mismatch Interrupt - CMI (rw) */
Ifx_UReg_32Bit CEI:1; /**< \brief [1:1] Configuration Error Interrupt - CEI (rw) */
Ifx_UReg_32Bit LEI:1; /**< \brief [2:2] Length Error Interrupt - LEI (rw) */
Ifx_UReg_32Bit BEI:1; /**< \brief [3:3] Bus Error Interrupt - BEI (rw) */
Ifx_UReg_32Bit CCE:1; /**< \brief [4:4] CRC Check Comparison - CCE (rw) */
Ifx_UReg_32Bit ALR:1; /**< \brief [5:5] Automatic Length Reload - ALR (rw) */
Ifx_UReg_32Bit reserved_6:2; /**< \brief [7:6] \internal Reserved */
Ifx_UReg_32Bit REFIN:1; /**< \brief [8:8] IR Byte Wise Reflection - REFIN (rw) */
Ifx_UReg_32Bit REFOUT:1; /**< \brief [9:9] CRC Bit Wise Reflection - REFOUT (rw) */
Ifx_UReg_32Bit XSEL:1; /**< \brief [10:10] Selects the value to be xored with the final CRC - XSEL (rw) */
Ifx_UReg_32Bit BYTESWAP:1; /**< \brief [11:11] Swaps the order of the bytes in the IR input register. - BYTESWAP (rw) */
Ifx_UReg_32Bit reserved_12:4; /**< \brief [15:12] \internal Reserved */
Ifx_UReg_32Bit KERNEL:4; /**< \brief [19:16] Selects the CRC Kernel (Polynomial Engine) used by this channel. - KERNEL (rw) */
Ifx_UReg_32Bit reserved_20:12; /**< \brief [31:20] \internal Reserved */
} Ifx_FCE_IN_CFG_Bits;
/** \brief CRC Check Register ${i} */
typedef struct _Ifx_FCE_IN_CHECK_Bits
{
Ifx_UReg_32Bit CHECK:32; /**< \brief [31:0] CHECK Register - CHECK (rw) */
} Ifx_FCE_IN_CHECK_Bits;
/** \brief CRC Regsister ${i} */
typedef struct _Ifx_FCE_IN_CRC_Bits
{
Ifx_UReg_32Bit CRC:32; /**< \brief [31:0] CRC Register - CRC (rwh) */
} Ifx_FCE_IN_CRC_Bits;
/** \brief CRC Test Register ${i} */
typedef struct _Ifx_FCE_IN_CTR_Bits
{
Ifx_UReg_32Bit FCM:1; /**< \brief [0:0] Force CRC Mismatch - FCM (rw) */
Ifx_UReg_32Bit FRM_CFG:1; /**< \brief [1:1] Force CFG Register Mismatch - FRM_CFG (rw) */
Ifx_UReg_32Bit FRM_CHECK:1; /**< \brief [2:2] Force Check Register Mismatch - FRM_CHECK (rw) */
Ifx_UReg_32Bit reserved_3:29; /**< \brief [31:3] \internal Reserved */
} Ifx_FCE_IN_CTR_Bits;
/** \brief Input Register ${i} */
typedef struct _Ifx_FCE_IN_IR_Bits
{
Ifx_UReg_32Bit IR:32; /**< \brief [31:0] Input Register - IR (rw) */
} Ifx_FCE_IN_IR_Bits;
/** \brief CRC Length Register ${i} */
typedef struct _Ifx_FCE_IN_LENGTH_Bits
{
Ifx_UReg_32Bit LENGTH:16; /**< \brief [15:0] Message Length Register - LENGTH (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_FCE_IN_LENGTH_Bits;
/** \brief CRC Result Register ${i} */
typedef struct _Ifx_FCE_IN_RES_Bits
{
Ifx_UReg_32Bit RES:32; /**< \brief [31:0] Result Register - RES (rh) */
} Ifx_FCE_IN_RES_Bits;
/** \brief CRC Status Register ${i} */
typedef struct _Ifx_FCE_IN_STS_Bits
{
Ifx_UReg_32Bit CMF:1; /**< \brief [0:0] CRC Mismatch Flag - CMF (rwh) */
Ifx_UReg_32Bit CEF:1; /**< \brief [1:1] Configuration Error Flag - CEF (rwh) */
Ifx_UReg_32Bit LEF:1; /**< \brief [2:2] Length Error Flag - LEF (rwh) */
Ifx_UReg_32Bit BEF:1; /**< \brief [3:3] Bus Error Flag - BEF (rwh) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_FCE_IN_STS_Bits;
/** \brief Kernel Reset Register 0 */
typedef struct _Ifx_FCE_KRST0_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status - RSTSTAT (r) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_FCE_KRST0_Bits;
/** \brief Kernel Reset Register 1 */
typedef struct _Ifx_FCE_KRST1_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_FCE_KRST1_Bits;
/** \brief Kernel Reset Status Clear Register */
typedef struct _Ifx_FCE_KRSTCLR_Bits
{
Ifx_UReg_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear - CLR (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_FCE_KRSTCLR_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_fce_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_ACCEN0;
/** \brief Access Enable Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_ACCEN1_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_ACCEN1;
/** \brief Channels Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_CHSTS_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_CHSTS;
/** \brief Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_CLC;
/** \brief Module Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_ID_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_ID;
/** \brief CRC Configuration Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_IN_CFG_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_IN_CFG;
/** \brief CRC Check Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_IN_CHECK_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_IN_CHECK;
/** \brief CRC Regsister ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_IN_CRC_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_IN_CRC;
/** \brief CRC Test Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_IN_CTR_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_IN_CTR;
/** \brief Input Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_IN_IR_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_IN_IR;
/** \brief CRC Length Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_IN_LENGTH_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_IN_LENGTH;
/** \brief CRC Result Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_IN_RES_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_IN_RES;
/** \brief CRC Status Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_IN_STS_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_IN_STS;
/** \brief Kernel Reset Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_KRST0_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_KRST0;
/** \brief Kernel Reset Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_KRST1_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_KRST1;
/** \brief Kernel Reset Status Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_FCE_KRSTCLR_Bits B; /**< \brief Bitfield access */
} Ifx_FCE_KRSTCLR;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fce_IN_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief IN object */
typedef volatile struct _Ifx_FCE_IN
{
Ifx_FCE_IN_IR IR; /**< \brief 0, Input Register ${i}*/
Ifx_FCE_IN_RES RES; /**< \brief 4, CRC Result Register ${i}*/
Ifx_FCE_IN_CFG CFG; /**< \brief 8, CRC Configuration Register ${i}*/
Ifx_FCE_IN_STS STS; /**< \brief C, CRC Status Register ${i}*/
Ifx_FCE_IN_LENGTH LENGTH; /**< \brief 10, CRC Length Register ${i}*/
Ifx_FCE_IN_CHECK CHECK; /**< \brief 14, CRC Check Register ${i}*/
Ifx_FCE_IN_CRC CRC; /**< \brief 18, CRC Regsister ${i}*/
Ifx_FCE_IN_CTR CTR; /**< \brief 1C, CRC Test Register ${i}*/
} Ifx_FCE_IN;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fce_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief FCE object */
typedef volatile struct _Ifx_FCE
{
Ifx_FCE_CLC CLC; /**< \brief 0, Clock Control Register*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_FCE_ID ID; /**< \brief 8, Module Identification Register*/
Ifx_UReg_8Bit reserved_C[20]; /**< \brief C, \internal Reserved */
Ifx_FCE_CHSTS CHSTS; /**< \brief 20, Channels Status Register*/
Ifx_UReg_8Bit reserved_24[200]; /**< \brief 24, \internal Reserved */
Ifx_FCE_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register*/
Ifx_FCE_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1*/
Ifx_FCE_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0*/
Ifx_FCE_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1*/
Ifx_FCE_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0*/
Ifx_FCE_IN IN[8]; /**< \brief 100, CRC Test Register ${i}*/
} Ifx_FCE;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXFCE_REGDEF_H */

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/**
* \file IfxFsi_bf.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Fsi_Registers_BitfieldsMask Bitfields mask and offset
* \ingroup IfxSfr_Fsi_Registers
*
*/
#ifndef IFXFSI_BF_H
#define IFXFSI_BF_H 1
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fsi_Registers_BitfieldsMask
* \{ */
/** \brief Length for Ifx_FSI_COMM_1_Bits.COMM1 */
#define IFX_FSI_COMM_1_COMM1_LEN (8u)
/** \brief Mask for Ifx_FSI_COMM_1_Bits.COMM1 */
#define IFX_FSI_COMM_1_COMM1_MSK (0xffu)
/** \brief Offset for Ifx_FSI_COMM_1_Bits.COMM1 */
#define IFX_FSI_COMM_1_COMM1_OFF (0u)
/** \brief Length for Ifx_FSI_COMM_2_Bits.COMM2 */
#define IFX_FSI_COMM_2_COMM2_LEN (8u)
/** \brief Mask for Ifx_FSI_COMM_2_Bits.COMM2 */
#define IFX_FSI_COMM_2_COMM2_MSK (0xffu)
/** \brief Offset for Ifx_FSI_COMM_2_Bits.COMM2 */
#define IFX_FSI_COMM_2_COMM2_OFF (0u)
/** \brief Length for Ifx_FSI_HSMCOMM_1_Bits.HSMCOMM1 */
#define IFX_FSI_HSMCOMM_1_HSMCOMM1_LEN (8u)
/** \brief Mask for Ifx_FSI_HSMCOMM_1_Bits.HSMCOMM1 */
#define IFX_FSI_HSMCOMM_1_HSMCOMM1_MSK (0xffu)
/** \brief Offset for Ifx_FSI_HSMCOMM_1_Bits.HSMCOMM1 */
#define IFX_FSI_HSMCOMM_1_HSMCOMM1_OFF (0u)
/** \brief Length for Ifx_FSI_HSMCOMM_2_Bits.HSMCOMM2 */
#define IFX_FSI_HSMCOMM_2_HSMCOMM2_LEN (8u)
/** \brief Mask for Ifx_FSI_HSMCOMM_2_Bits.HSMCOMM2 */
#define IFX_FSI_HSMCOMM_2_HSMCOMM2_MSK (0xffu)
/** \brief Offset for Ifx_FSI_HSMCOMM_2_Bits.HSMCOMM2 */
#define IFX_FSI_HSMCOMM_2_HSMCOMM2_OFF (0u)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXFSI_BF_H */

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/**
* \file IfxFsi_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Fsi_Registers_Cfg Fsi address
* \ingroup IfxSfr_Fsi_Registers
*
* \defgroup IfxSfr_Fsi_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Fsi_Registers_Cfg
*
* \defgroup IfxSfr_Fsi_Registers_Cfg_Fsi 2-FSI
* \ingroup IfxSfr_Fsi_Registers_Cfg
*
*
*/
#ifndef IFXFSI_REG_H
#define IFXFSI_REG_H 1
/******************************************************************************/
#include "IfxFsi_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fsi_Registers_Cfg_BaseAddress
* \{ */
/** \brief FSI object */
#define MODULE_FSI /*lint --e(923, 9078)*/ ((*(Ifx_FSI*)0xF8030000u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fsi_Registers_Cfg_Fsi
* \{ */
/** \brief 4, Communication Register 1 */
#define FSI_COMM_1 /*lint --e(923, 9078)*/ (*(volatile Ifx_FSI_COMM_1*)0xF8030004u)
/** \brief 5, Communication Register 2 */
#define FSI_COMM_2 /*lint --e(923, 9078)*/ (*(volatile Ifx_FSI_COMM_2*)0xF8030005u)
/** \brief 6, HSM Communication Register 1 */
#define FSI_HSMCOMM_1 /*lint --e(923, 9078)*/ (*(volatile Ifx_FSI_HSMCOMM_1*)0xF8030006u)
/** \brief 7, HSM Communication Register 2 */
#define FSI_HSMCOMM_2 /*lint --e(923, 9078)*/ (*(volatile Ifx_FSI_HSMCOMM_2*)0xF8030007u)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXFSI_REG_H */

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/**
* \file IfxFsi_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Fsi_Registers Fsi Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Fsi_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Fsi_Registers
*
* \defgroup IfxSfr_Fsi_Registers_union Register unions
* \ingroup IfxSfr_Fsi_Registers
*
* \defgroup IfxSfr_Fsi_Registers_struct Memory map
* \ingroup IfxSfr_Fsi_Registers
*/
#ifndef IFXFSI_REGDEF_H
#define IFXFSI_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Fsi_Registers_Bitfields
* \{ */
/** \brief Communication Register 1 */
typedef struct _Ifx_FSI_COMM_1_Bits
{
Ifx_UReg_8Bit COMM1:8; /**< \brief [7:0] FSI Communication 1 - COMM1 (rw) */
} Ifx_FSI_COMM_1_Bits;
/** \brief Communication Register 2 */
typedef struct _Ifx_FSI_COMM_2_Bits
{
Ifx_UReg_8Bit COMM2:8; /**< \brief [7:0] FSI Communication 2 - COMM2 (rw) */
} Ifx_FSI_COMM_2_Bits;
/** \brief HSM Communication Register 1 */
typedef struct _Ifx_FSI_HSMCOMM_1_Bits
{
Ifx_UReg_8Bit HSMCOMM1:8; /**< \brief [7:0] HSM FSI Communication 1 - HSMCOMM1 (rw) */
} Ifx_FSI_HSMCOMM_1_Bits;
/** \brief HSM Communication Register 2 */
typedef struct _Ifx_FSI_HSMCOMM_2_Bits
{
Ifx_UReg_8Bit HSMCOMM2:8; /**< \brief [7:0] HSM FSI Communication 2 - HSMCOMM2 (rw) */
} Ifx_FSI_HSMCOMM_2_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_fsi_Registers_union
* \{ */
/** \brief Communication Register 1 */
typedef union
{
Ifx_UReg_8Bit U; /**< \brief Unsigned access */
Ifx_SReg_8Bit I; /**< \brief Signed access */
Ifx_FSI_COMM_1_Bits B; /**< \brief Bitfield access */
} Ifx_FSI_COMM_1;
/** \brief Communication Register 2 */
typedef union
{
Ifx_UReg_8Bit U; /**< \brief Unsigned access */
Ifx_SReg_8Bit I; /**< \brief Signed access */
Ifx_FSI_COMM_2_Bits B; /**< \brief Bitfield access */
} Ifx_FSI_COMM_2;
/** \brief HSM Communication Register 1 */
typedef union
{
Ifx_UReg_8Bit U; /**< \brief Unsigned access */
Ifx_SReg_8Bit I; /**< \brief Signed access */
Ifx_FSI_HSMCOMM_1_Bits B; /**< \brief Bitfield access */
} Ifx_FSI_HSMCOMM_1;
/** \brief HSM Communication Register 2 */
typedef union
{
Ifx_UReg_8Bit U; /**< \brief Unsigned access */
Ifx_SReg_8Bit I; /**< \brief Signed access */
Ifx_FSI_HSMCOMM_2_Bits B; /**< \brief Bitfield access */
} Ifx_FSI_HSMCOMM_2;
/** \} */
/******************************************************************************/
/** \addtogroup IfxSfr_Fsi_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief FSI object */
typedef volatile struct _Ifx_FSI
{
Ifx_UReg_8Bit reserved_0[4]; /**< \brief 0, \internal Reserved */
Ifx_FSI_COMM_1 COMM_1; /**< \brief 4, Communication Register 1*/
Ifx_FSI_COMM_2 COMM_2; /**< \brief 5, Communication Register 2*/
Ifx_FSI_HSMCOMM_1 HSMCOMM_1; /**< \brief 6, HSM Communication Register 1*/
Ifx_FSI_HSMCOMM_2 HSMCOMM_2; /**< \brief 7, HSM Communication Register 2*/
Ifx_UReg_8Bit reserved_8[248]; /**< \brief 8, \internal Reserved */
} Ifx_FSI;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXFSI_REGDEF_H */

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/**
* \file IfxGpt12_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Gpt12_Registers_Cfg Gpt12 address
* \ingroup IfxSfr_Gpt12_Registers
*
* \defgroup IfxSfr_Gpt12_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Gpt12_Registers_Cfg
*
* \defgroup IfxSfr_Gpt12_Registers_Cfg_Gpt120 2-GPT120
* \ingroup IfxSfr_Gpt12_Registers_Cfg
*
*
*/
#ifndef IFXGPT12_REG_H
#define IFXGPT12_REG_H 1
/******************************************************************************/
#include "IfxGpt12_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Gpt12_Registers_Cfg_BaseAddress
* \{ */
/** \brief GPT12 object */
#define MODULE_GPT120 /*lint --e(923, 9078)*/ ((*(Ifx_GPT12*)0xF0001800u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Gpt12_Registers_Cfg_Gpt120
* \{ */
/** \brief 0, Clock Control Register */
#define GPT120_CLC /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_CLC*)0xF0001800u)
/** \brief 4, Port Input Select Register */
#define GPT120_PISEL /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_PISEL*)0xF0001804u)
/** \brief 8, Identification Register */
#define GPT120_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_ID*)0xF0001808u)
/** \brief 10, Timer T2 Control Register */
#define GPT120_T2CON /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T2CON*)0xF0001810u)
/** \brief 14, Timer T3 Control Register */
#define GPT120_T3CON /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T3CON*)0xF0001814u)
/** \brief 18, Timer T4 Control Register */
#define GPT120_T4CON /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T4CON*)0xF0001818u)
/** \brief 1C, Timer T5 Control Register */
#define GPT120_T5CON /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T5CON*)0xF000181Cu)
/** \brief 20, Timer T6 Control Register */
#define GPT120_T6CON /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T6CON*)0xF0001820u)
/** \brief 30, Capture and Reload Register */
#define GPT120_CAPREL /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_CAPREL*)0xF0001830u)
/** \brief 34, Timer T2 Register */
#define GPT120_T2 /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T2*)0xF0001834u)
/** \brief 38, Timer T3 Register */
#define GPT120_T3 /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T3*)0xF0001838u)
/** \brief 3C, Timer T4 Register */
#define GPT120_T4 /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T4*)0xF000183Cu)
/** \brief 40, Timer T5 Register */
#define GPT120_T5 /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T5*)0xF0001840u)
/** \brief 44, Timer T6 Register */
#define GPT120_T6 /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_T6*)0xF0001844u)
/** \brief E8, OCDS Control and Status Register */
#define GPT120_OCS /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_OCS*)0xF00018E8u)
/** \brief EC, Kernel Reset Status Clear Register */
#define GPT120_KRSTCLR /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_KRSTCLR*)0xF00018ECu)
/** \brief F0, Kernel Reset Register 1 */
#define GPT120_KRST1 /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_KRST1*)0xF00018F0u)
/** \brief F4, Kernel Reset Register 0 */
#define GPT120_KRST0 /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_KRST0*)0xF00018F4u)
/** \brief FC, Access Enable Register 0 */
#define GPT120_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_GPT12_ACCEN0*)0xF00018FCu)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXGPT12_REG_H */

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/**
* \file IfxGpt12_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Gpt12_Registers Gpt12 Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Gpt12_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Gpt12_Registers
*
* \defgroup IfxSfr_Gpt12_Registers_union Register unions
* \ingroup IfxSfr_Gpt12_Registers
*
* \defgroup IfxSfr_Gpt12_Registers_struct Memory map
* \ingroup IfxSfr_Gpt12_Registers
*/
#ifndef IFXGPT12_REGDEF_H
#define IFXGPT12_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Gpt12_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_GPT12_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_GPT12_ACCEN0_Bits;
/** \brief Capture and Reload Register */
typedef struct _Ifx_GPT12_CAPREL_Bits
{
Ifx_UReg_32Bit CAPREL:16; /**< \brief [15:0] Current reload value or Captured value - CAPREL (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_CAPREL_Bits;
/** \brief Clock Control Register */
typedef struct _Ifx_GPT12_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (rh) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control - EDIS (rw) */
Ifx_UReg_32Bit reserved_4:12; /**< \brief [15:4] \internal Reserved */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_CLC_Bits;
/** \brief Identification Register */
typedef struct _Ifx_GPT12_ID_Bits
{
Ifx_UReg_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number - MODREV (r) */
Ifx_UReg_32Bit MODTYPE:8; /**< \brief [15:8] Module Type - MODTYPE (r) */
Ifx_UReg_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number - MODNUMBER (r) */
} Ifx_GPT12_ID_Bits;
/** \brief Kernel Reset Register 0 */
typedef struct _Ifx_GPT12_KRST0_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status - RSTSTAT (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_GPT12_KRST0_Bits;
/** \brief Kernel Reset Register 1 */
typedef struct _Ifx_GPT12_KRST1_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_GPT12_KRST1_Bits;
/** \brief Kernel Reset Status Clear Register */
typedef struct _Ifx_GPT12_KRSTCLR_Bits
{
Ifx_UReg_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear - CLR (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_GPT12_KRSTCLR_Bits;
/** \brief OCDS Control and Status Register */
typedef struct _Ifx_GPT12_OCS_Bits
{
Ifx_UReg_32Bit reserved_0:4; /**< \brief [3:0] \internal Reserved */
Ifx_UReg_32Bit reserved_4:20; /**< \brief [23:4] \internal Reserved */
Ifx_UReg_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control - SUS (rw) */
Ifx_UReg_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection - SUS_P (w) */
Ifx_UReg_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State - SUSSTA (rh) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_GPT12_OCS_Bits;
/** \brief Port Input Select Register */
typedef struct _Ifx_GPT12_PISEL_Bits
{
Ifx_UReg_32Bit IST2IN:1; /**< \brief [0:0] Input Select for T2IN - IST2IN (rw) */
Ifx_UReg_32Bit IST2EUD:1; /**< \brief [1:1] Input Select for T2EUD - IST2EUD (rw) */
Ifx_UReg_32Bit IST3IN:2; /**< \brief [3:2] Input Select for T3IN - IST3IN (rw) */
Ifx_UReg_32Bit IST3EUD:2; /**< \brief [5:4] Input Select for T3EUD - IST3EUD (rw) */
Ifx_UReg_32Bit IST4IN:2; /**< \brief [7:6] Input Select for T4IN - IST4IN (rw) */
Ifx_UReg_32Bit IST4EUD:2; /**< \brief [9:8] Input Select for T4EUD - IST4EUD (rw) */
Ifx_UReg_32Bit IST5IN:1; /**< \brief [10:10] Input Select for T5IN - IST5IN (rw) */
Ifx_UReg_32Bit IST5EUD:1; /**< \brief [11:11] Input Select for T5EUD - IST5EUD (rw) */
Ifx_UReg_32Bit IST6IN:1; /**< \brief [12:12] Input Select for T6IN - IST6IN (rw) */
Ifx_UReg_32Bit IST6EUD:1; /**< \brief [13:13] Input Select for T6EUD - IST6EUD (rw) */
Ifx_UReg_32Bit ISCAPIN:2; /**< \brief [15:14] Input Select for CAPIN - ISCAPIN (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_PISEL_Bits;
/** \brief Timer T2 Register */
typedef struct _Ifx_GPT12_T2_Bits
{
Ifx_UReg_32Bit T2:16; /**< \brief [15:0] Timer T2 - T2 (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T2_Bits;
/** \brief Timer T2 Control Register */
typedef struct _Ifx_GPT12_T2CON_Bits
{
Ifx_UReg_32Bit T2I:3; /**< \brief [2:0] Timer T2 Input Parameter Selection - T2I (rw) */
Ifx_UReg_32Bit T2M:3; /**< \brief [5:3] Timer T2 Mode Control (Basic Operating Mode) - T2M (rw) */
Ifx_UReg_32Bit T2R:1; /**< \brief [6:6] Timer T2 Run Bit - T2R (rw) */
Ifx_UReg_32Bit T2UD:1; /**< \brief [7:7] Timer T2 Up/Down Control - T2UD (rw) */
Ifx_UReg_32Bit T2UDE:1; /**< \brief [8:8] Timer T2 External Up/Down Enable - T2UDE (rw) */
Ifx_UReg_32Bit T2RC:1; /**< \brief [9:9] Timer T2 Remote Control - T2RC (rw) */
Ifx_UReg_32Bit reserved_10:2; /**< \brief [11:10] \internal Reserved */
Ifx_UReg_32Bit T2IRDIS:1; /**< \brief [12:12] Timer T2 Interrupt Disable - T2IRDIS (rw) */
Ifx_UReg_32Bit T2EDGE:1; /**< \brief [13:13] Timer T2 Edge Detection - T2EDGE (rwh) */
Ifx_UReg_32Bit T2CHDIR:1; /**< \brief [14:14] Timer T2 Count Direction Change - T2CHDIR (rwh) */
Ifx_UReg_32Bit T2RDIR:1; /**< \brief [15:15] Timer T2 Rotation Direction - T2RDIR (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T2CON_Bits;
/** \brief Timer T3 Register */
typedef struct _Ifx_GPT12_T3_Bits
{
Ifx_UReg_32Bit T3:16; /**< \brief [15:0] Timer T3 - T3 (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T3_Bits;
/** \brief Timer T3 Control Register */
typedef struct _Ifx_GPT12_T3CON_Bits
{
Ifx_UReg_32Bit T3I:3; /**< \brief [2:0] Timer T3 Input Parameter Selection - T3I (rw) */
Ifx_UReg_32Bit T3M:3; /**< \brief [5:3] Timer T3 Mode Control - T3M (rw) */
Ifx_UReg_32Bit T3R:1; /**< \brief [6:6] Timer T3 Run Bit - T3R (rw) */
Ifx_UReg_32Bit T3UD:1; /**< \brief [7:7] Timer T3 Up/Down Control - T3UD (rw) */
Ifx_UReg_32Bit T3UDE:1; /**< \brief [8:8] Timer T3 External Up/Down Enable - T3UDE (rw) */
Ifx_UReg_32Bit T3OE:1; /**< \brief [9:9] Overflow/Underflow Output Enable - T3OE (rw) */
Ifx_UReg_32Bit T3OTL:1; /**< \brief [10:10] Timer T3 Overflow Toggle Latch - T3OTL (rwh) */
Ifx_UReg_32Bit BPS1:2; /**< \brief [12:11] GPT1 Block Prescaler Control - BPS1 (rw) */
Ifx_UReg_32Bit T3EDGE:1; /**< \brief [13:13] Timer T3 Edge Detection Flag - T3EDGE (rwh) */
Ifx_UReg_32Bit T3CHDIR:1; /**< \brief [14:14] Timer T3 Count Direction Change Flag - T3CHDIR (rwh) */
Ifx_UReg_32Bit T3RDIR:1; /**< \brief [15:15] Timer T3 Rotation Direction Flag - T3RDIR (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T3CON_Bits;
/** \brief Timer T4 Register */
typedef struct _Ifx_GPT12_T4_Bits
{
Ifx_UReg_32Bit T4:16; /**< \brief [15:0] Timer T4 - T4 (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T4_Bits;
/** \brief Timer T4 Control Register */
typedef struct _Ifx_GPT12_T4CON_Bits
{
Ifx_UReg_32Bit T4I:3; /**< \brief [2:0] Timer T4 Input Parameter Selection - T4I (rw) */
Ifx_UReg_32Bit T4M:3; /**< \brief [5:3] Timer T4 Mode Control (Basic Operating Mode) - T4M (rw) */
Ifx_UReg_32Bit T4R:1; /**< \brief [6:6] Timer T4 Run Bit - T4R (rw) */
Ifx_UReg_32Bit T4UD:1; /**< \brief [7:7] Timer T4 Up/Down Control - T4UD (rw) */
Ifx_UReg_32Bit T4UDE:1; /**< \brief [8:8] Timer T4 External Up/Down Enable - T4UDE (rw) */
Ifx_UReg_32Bit T4RC:1; /**< \brief [9:9] Timer T4 Remote Control - T4RC (rw) */
Ifx_UReg_32Bit CLRT2EN:1; /**< \brief [10:10] Clear Timer T2 Enable - CLRT2EN (rw) */
Ifx_UReg_32Bit CLRT3EN:1; /**< \brief [11:11] Clear Timer T3 Enable - CLRT3EN (rw) */
Ifx_UReg_32Bit T4IRDIS:1; /**< \brief [12:12] Timer T4 Interrupt Disable - T4IRDIS (rw) */
Ifx_UReg_32Bit T4EDGE:1; /**< \brief [13:13] Timer T4 Edge Detection - T4EDGE (rwh) */
Ifx_UReg_32Bit T4CHDIR:1; /**< \brief [14:14] Timer T4 Count Direction Change - T4CHDIR (rwh) */
Ifx_UReg_32Bit T4RDIR:1; /**< \brief [15:15] Timer T4 Rotation Direction - T4RDIR (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T4CON_Bits;
/** \brief Timer T5 Register */
typedef struct _Ifx_GPT12_T5_Bits
{
Ifx_UReg_32Bit T5:16; /**< \brief [15:0] Timer T5 - T5 (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T5_Bits;
/** \brief Timer T5 Control Register */
typedef struct _Ifx_GPT12_T5CON_Bits
{
Ifx_UReg_32Bit T5I:3; /**< \brief [2:0] Timer T5 Input Parameter Selection - T5I (rw) */
Ifx_UReg_32Bit T5M:3; /**< \brief [5:3] Timer T5 Mode Control (Basic Operating Mode) - T5M (rw) */
Ifx_UReg_32Bit T5R:1; /**< \brief [6:6] Timer T5 Run Bit - T5R (rw) */
Ifx_UReg_32Bit T5UD:1; /**< \brief [7:7] Timer T5 Up/Down Control - T5UD (rw) */
Ifx_UReg_32Bit T5UDE:1; /**< \brief [8:8] Timer T5 External Up/Down Enable - T5UDE (rw) */
Ifx_UReg_32Bit T5RC:1; /**< \brief [9:9] Timer T5 Remote Control - T5RC (rw) */
Ifx_UReg_32Bit CT3:1; /**< \brief [10:10] Timer T3 Capture Trigger Enable - CT3 (rw) */
Ifx_UReg_32Bit reserved_11:1; /**< \brief [11:11] \internal Reserved */
Ifx_UReg_32Bit CI:2; /**< \brief [13:12] Register CAPREL Capture Trigger Selection - CI (rw) */
Ifx_UReg_32Bit T5CLR:1; /**< \brief [14:14] Timer T5 Clear Enable Bit - T5CLR (rw) */
Ifx_UReg_32Bit T5SC:1; /**< \brief [15:15] Timer T5 Capture Mode Enable - T5SC (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T5CON_Bits;
/** \brief Timer T6 Register */
typedef struct _Ifx_GPT12_T6_Bits
{
Ifx_UReg_32Bit T6:16; /**< \brief [15:0] Timer T6 - T6 (rwh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T6_Bits;
/** \brief Timer T6 Control Register */
typedef struct _Ifx_GPT12_T6CON_Bits
{
Ifx_UReg_32Bit T6I:3; /**< \brief [2:0] Timer T6 Input Parameter Selection - T6I (rw) */
Ifx_UReg_32Bit T6M:3; /**< \brief [5:3] Timer T6 Mode Control (Basic Operating Mode) - T6M (rw) */
Ifx_UReg_32Bit T6R:1; /**< \brief [6:6] Timer T6 Run Bit - T6R (rw) */
Ifx_UReg_32Bit T6UD:1; /**< \brief [7:7] Timer T6 Up/Down Control - T6UD (rw) */
Ifx_UReg_32Bit T6UDE:1; /**< \brief [8:8] Timer T6 External Up/Down Enable - T6UDE (rw) */
Ifx_UReg_32Bit T6OE:1; /**< \brief [9:9] Overflow/Underflow Output Enable - T6OE (rw) */
Ifx_UReg_32Bit T6OTL:1; /**< \brief [10:10] Timer T6 Overflow Toggle Latch - T6OTL (rwh) */
Ifx_UReg_32Bit BPS2:2; /**< \brief [12:11] GPT2 Block Prescaler Control - BPS2 (rw) */
Ifx_UReg_32Bit reserved_13:1; /**< \brief [13:13] \internal Reserved */
Ifx_UReg_32Bit T6CLR:1; /**< \brief [14:14] Timer T6 Clear Enable Bit - T6CLR (rw) */
Ifx_UReg_32Bit T6SR:1; /**< \brief [15:15] Timer T6 Reload Mode Enable - T6SR (rw) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_GPT12_T6CON_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_gpt12_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_ACCEN0;
/** \brief Capture and Reload Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_CAPREL_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_CAPREL;
/** \brief Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_CLC;
/** \brief Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_ID_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_ID;
/** \brief Kernel Reset Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_KRST0_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_KRST0;
/** \brief Kernel Reset Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_KRST1_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_KRST1;
/** \brief Kernel Reset Status Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_KRSTCLR_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_KRSTCLR;
/** \brief OCDS Control and Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_OCS_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_OCS;
/** \brief Port Input Select Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_PISEL_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_PISEL;
/** \brief Timer T2 Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T2_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T2;
/** \brief Timer T2 Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T2CON_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T2CON;
/** \brief Timer T3 Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T3_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T3;
/** \brief Timer T3 Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T3CON_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T3CON;
/** \brief Timer T4 Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T4_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T4;
/** \brief Timer T4 Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T4CON_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T4CON;
/** \brief Timer T5 Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T5_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T5;
/** \brief Timer T5 Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T5CON_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T5CON;
/** \brief Timer T6 Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T6_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T6;
/** \brief Timer T6 Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_GPT12_T6CON_Bits B; /**< \brief Bitfield access */
} Ifx_GPT12_T6CON;
/** \} */
/******************************************************************************/
/** \addtogroup IfxSfr_Gpt12_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief GPT12 object */
typedef volatile struct _Ifx_GPT12
{
Ifx_GPT12_CLC CLC; /**< \brief 0, Clock Control Register*/
Ifx_GPT12_PISEL PISEL; /**< \brief 4, Port Input Select Register*/
Ifx_GPT12_ID ID; /**< \brief 8, Identification Register*/
Ifx_UReg_8Bit reserved_C[4]; /**< \brief C, \internal Reserved */
Ifx_GPT12_T2CON T2CON; /**< \brief 10, Timer T2 Control Register*/
Ifx_GPT12_T3CON T3CON; /**< \brief 14, Timer T3 Control Register*/
Ifx_GPT12_T4CON T4CON; /**< \brief 18, Timer T4 Control Register*/
Ifx_GPT12_T5CON T5CON; /**< \brief 1C, Timer T5 Control Register*/
Ifx_GPT12_T6CON T6CON; /**< \brief 20, Timer T6 Control Register*/
Ifx_UReg_8Bit reserved_24[12]; /**< \brief 24, \internal Reserved */
Ifx_GPT12_CAPREL CAPREL; /**< \brief 30, Capture and Reload Register*/
Ifx_GPT12_T2 T2; /**< \brief 34, Timer T2 Register*/
Ifx_GPT12_T3 T3; /**< \brief 38, Timer T3 Register*/
Ifx_GPT12_T4 T4; /**< \brief 3C, Timer T4 Register*/
Ifx_GPT12_T5 T5; /**< \brief 40, Timer T5 Register*/
Ifx_GPT12_T6 T6; /**< \brief 44, Timer T6 Register*/
Ifx_UReg_8Bit reserved_48[160]; /**< \brief 48, \internal Reserved */
Ifx_GPT12_OCS OCS; /**< \brief E8, OCDS Control and Status Register*/
Ifx_GPT12_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register*/
Ifx_GPT12_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1*/
Ifx_GPT12_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0*/
Ifx_UReg_8Bit reserved_F8[4]; /**< \brief F8, \internal Reserved */
Ifx_GPT12_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0*/
} Ifx_GPT12;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXGPT12_REGDEF_H */

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/**
* \file IfxHsct_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Hsct_Registers_Cfg Hsct address
* \ingroup IfxSfr_Hsct_Registers
*
* \defgroup IfxSfr_Hsct_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Hsct_Registers_Cfg
*
* \defgroup IfxSfr_Hsct_Registers_Cfg_Hsct0 2-HSCT0
* \ingroup IfxSfr_Hsct_Registers_Cfg
*
*
*/
#ifndef IFXHSCT_REG_H
#define IFXHSCT_REG_H 1
/******************************************************************************/
#include "IfxHsct_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hsct_Registers_Cfg_BaseAddress
* \{ */
/** \brief HSCT object */
#define MODULE_HSCT0 /*lint --e(923, 9078)*/ ((*(Ifx_HSCT*)0xF0090000u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hsct_Registers_Cfg_Hsct0
* \{ */
/** \brief 0, Clock Control Register */
#define HSCT0_CLC /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_CLC*)0xF0090000u)
/** \brief 8, Module Identification Register */
#define HSCT0_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_ID*)0xF0090008u)
/** \brief 10, Initialization Register */
#define HSCT0_INIT /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_INIT*)0xF0090010u)
/** \brief 14, Interface Control Register */
#define HSCT0_IFCTRL /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_IFCTRL*)0xF0090014u)
/** \brief 18, Sleep Control Register */
#define HSCT0_SLEEPCTRL /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_SLEEPCTRL*)0xF0090018u)
/** \brief 1C, Clear To Send Control Register */
#define HSCT0_CTSCTRL /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_CTSCTRL*)0xF009001Cu)
/** \brief 20, Transmission Disable Register */
#define HSCT0_DISABLE /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_DISABLE*)0xF0090020u)
/** \brief 24, Status Register */
#define HSCT0_STAT /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_STAT*)0xF0090024u)
/** \brief 28, Interface Status Register */
#define HSCT0_IFSTAT /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_IFSTAT*)0xF0090028u)
/** \brief 30, Configuration Physical Layer Register */
#define HSCT0_CONFIGPHY /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_CONFIGPHY*)0xF0090030u)
/** \brief 34, STATPHY */
#define HSCT0_STATPHY /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_STATPHY*)0xF0090034u)
/** \brief 40, Interrupt register */
#define HSCT0_IRQ /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_IRQ*)0xF0090040u)
/** \brief 44, Interrupt Enable Register */
#define HSCT0_IRQEN /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_IRQEN*)0xF0090044u)
/** \brief 48, Interrupt Clear Register */
#define HSCT0_IRQCLR /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_IRQCLR*)0xF0090048u)
/** \brief 50, Unsolicited Status Message Received */
#define HSCT0_USMR /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_USMR*)0xF0090050u)
/** \brief 54, Unsolicited Status Message Send */
#define HSCT0_USMS /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_USMS*)0xF0090054u)
/** \brief 60, Test Control Register */
#define HSCT0_TESTCTRL /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_TESTCTRL*)0xF0090060u)
/** \brief FFE8, OCDS Control and Status */
#define HSCT0_OCS /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_OCS*)0xF009FFE8u)
/** \brief FFEC, Reset Status Clear Register */
#define HSCT0_KRSTCLR /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_KRSTCLR*)0xF009FFECu)
/** \brief FFF0, Reset Register 1 */
#define HSCT0_KRST1 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_KRST1*)0xF009FFF0u)
/** \brief FFF4, Reset Register 0 */
#define HSCT0_KRST0 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_KRST0*)0xF009FFF4u)
/** \brief FFF8, Access Enable Register 1 */
#define HSCT0_ACCEN1 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_ACCEN1*)0xF009FFF8u)
/** \brief FFFC, Access Enable Register 0 */
#define HSCT0_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSCT_ACCEN0*)0xF009FFFCu)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXHSCT_REG_H */

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/**
* \file IfxHsct_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Hsct_Registers Hsct Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Hsct_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Hsct_Registers
*
* \defgroup IfxSfr_Hsct_Registers_union Register unions
* \ingroup IfxSfr_Hsct_Registers
*
* \defgroup IfxSfr_Hsct_Registers_struct Memory map
* \ingroup IfxSfr_Hsct_Registers
*/
#ifndef IFXHSCT_REGDEF_H
#define IFXHSCT_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hsct_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_HSCT_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_HSCT_ACCEN0_Bits;
/** \brief Access Enable Register 1 */
typedef struct _Ifx_HSCT_ACCEN1_Bits
{
Ifx_UReg_32Bit reserved_0:32; /**< \brief [31:0] \internal Reserved */
} Ifx_HSCT_ACCEN1_Bits;
/** \brief Clock Control Register */
typedef struct _Ifx_HSCT_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (r) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit EDIS:1; /**< \brief [3:3] Chip System Sleep Mode Control - EDIS (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_HSCT_CLC_Bits;
/** \brief Configuration Physical Layer Register */
typedef struct _Ifx_HSCT_CONFIGPHY_Bits
{
Ifx_UReg_32Bit PON:1; /**< \brief [0:0] Physical Layer Power On. - PON (rw) */
Ifx_UReg_32Bit reserved_1:15; /**< \brief [15:1] \internal Reserved */
Ifx_UReg_32Bit CORCEN:5; /**< \brief [20:16] Correlator phase enable - allows to enable/disable each of the 5 Phase outputs separately. - CORCEN (rw) */
Ifx_UReg_32Bit reserved_21:11; /**< \brief [31:21] \internal Reserved */
} Ifx_HSCT_CONFIGPHY_Bits;
/** \brief Clear To Send Control Register */
typedef struct _Ifx_HSCT_CTSCTRL_Bits
{
Ifx_UReg_32Bit CTS_FRAME:1; /**< \brief [0:0] Transmit CTS Frame Generation - CTS_FRAME (rw) */
Ifx_UReg_32Bit CTS_TXD:1; /**< \brief [1:1] Disable TX CTS signaling - CTS_TXD (rw) */
Ifx_UReg_32Bit CTS_RXD:1; /**< \brief [2:2] Disable RX CTS detection - CTS_RXD (rw) */
Ifx_UReg_32Bit HSSL_CTS_FBD:1; /**< \brief [3:3] Disable HSSL interface CTS Frame Blocking - HSSL_CTS_FBD (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_HSCT_CTSCTRL_Bits;
/** \brief Transmission Disable Register */
typedef struct _Ifx_HSCT_DISABLE_Bits
{
Ifx_UReg_32Bit TX_DIS:1; /**< \brief [0:0] Disable HSCT Transmit path in Master interface - TX_DIS (rw) */
Ifx_UReg_32Bit RX_DIS:1; /**< \brief [1:1] Disable HSCT Receive path in Master interface - RX_DIS (rw) */
Ifx_UReg_32Bit RX_HEPD:1; /**< \brief [2:2] Disable RX Header Error Discard Payload data. - RX_HEPD (rw) */
Ifx_UReg_32Bit reserved_3:29; /**< \brief [31:3] \internal Reserved */
} Ifx_HSCT_DISABLE_Bits;
/** \brief Module Identification Register */
typedef struct _Ifx_HSCT_ID_Bits
{
Ifx_UReg_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number - MOD_REV (r) */
Ifx_UReg_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Number Type - MOD_TYPE (r) */
Ifx_UReg_32Bit MOD_NUM:16; /**< \brief [31:16] Module Number for module identification - MOD_NUM (r) */
} Ifx_HSCT_ID_Bits;
/** \brief Interface Control Register */
typedef struct _Ifx_HSCT_IFCTRL_Bits
{
Ifx_UReg_32Bit IFCVS:8; /**< \brief [7:0] Master Mode - Trigger for Interface Control Value to be send to Slave interface - IFCVS (rw) */
Ifx_UReg_32Bit SIFCV:1; /**< \brief [8:8] Master Mode - Slave IF control frame trigger - SIFCV (w) */
Ifx_UReg_32Bit reserved_9:7; /**< \brief [15:9] \internal Reserved */
Ifx_UReg_32Bit MRXSPEED:2; /**< \brief [17:16] Master Mode RX speed - MRXSPEED (rw) */
Ifx_UReg_32Bit MTXSPEED:2; /**< \brief [19:18] Master Mode TX speed - MTXSPEED (rw) */
Ifx_UReg_32Bit IFTESTMD:1; /**< \brief [20:20] Interface TX Test Mode - IFTESTMD (rw) */
Ifx_UReg_32Bit reserved_21:11; /**< \brief [31:21] \internal Reserved */
} Ifx_HSCT_IFCTRL_Bits;
/** \brief Interface Status Register */
typedef struct _Ifx_HSCT_IFSTAT_Bits
{
Ifx_UReg_32Bit RX_STAT:3; /**< \brief [2:0] HSCT Slave interface Status for RX link - RX_STAT (rh) */
Ifx_UReg_32Bit TX_STAT:2; /**< \brief [4:3] HSCT Slave interface Status for TX link - TX_STAT (rh) */
Ifx_UReg_32Bit TX_EN:1; /**< \brief [5:5] HSCT LVDS Slave interface TX enable - TX_EN (rh) */
Ifx_UReg_32Bit reserved_6:26; /**< \brief [31:6] \internal Reserved */
} Ifx_HSCT_IFSTAT_Bits;
/** \brief Initialization Register */
typedef struct _Ifx_HSCT_INIT_Bits
{
Ifx_UReg_32Bit reserved_0:1; /**< \brief [0:0] \internal Reserved */
Ifx_UReg_32Bit SYS_CLK_EN:1; /**< \brief [1:1] Enable HSCT SysClk in Master interface - SYS_CLK_EN (rw) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit IFM:1; /**< \brief [3:3] Select Interface Mode - IFM (rw) */
Ifx_UReg_32Bit SRCF:2; /**< \brief [5:4] Select Reference Clock Frequency Divider - SRCF (rw) */
Ifx_UReg_32Bit SSCF:2; /**< \brief [7:6] Select SysClk Frequency Divider - SSCF (rw) */
Ifx_UReg_32Bit reserved_8:8; /**< \brief [15:8] \internal Reserved */
Ifx_UReg_32Bit TXHD:3; /**< \brief [18:16] Transmit High Speed Divider. - TXHD (rw) */
Ifx_UReg_32Bit RXHD:3; /**< \brief [21:19] Receive High Speed Divider. - RXHD (rw) */
Ifx_UReg_32Bit reserved_22:10; /**< \brief [31:22] \internal Reserved */
} Ifx_HSCT_INIT_Bits;
/** \brief Interrupt register */
typedef struct _Ifx_HSCT_IRQ_Bits
{
Ifx_UReg_32Bit reserved_0:1; /**< \brief [0:0] \internal Reserved */
Ifx_UReg_32Bit HER:1; /**< \brief [1:1] Header error detected - HER (rh) */
Ifx_UReg_32Bit PYER:1; /**< \brief [2:2] Payload error detected - PYER (rh) */
Ifx_UReg_32Bit CER:1; /**< \brief [3:3] HSCT command error - CER (rh) */
Ifx_UReg_32Bit IFCFS:1; /**< \brief [4:4] HSCT interface control frame send - IFCFS (rh) */
Ifx_UReg_32Bit SMER:1; /**< \brief [5:5] Speed Mode Switch Error (Master Mode only) - SMER (rh) */
Ifx_UReg_32Bit USMSF:1; /**< \brief [6:6] Unsolicited message frame send finished - USMSF (rh) */
Ifx_UReg_32Bit PLER:1; /**< \brief [7:7] PLL lost lock error - PLER (rh) */
Ifx_UReg_32Bit USM:1; /**< \brief [8:8] Unsolicited Message Received - USM (rh) */
Ifx_UReg_32Bit PAR:1; /**< \brief [9:9] PING Answer Received - PAR (rh) */
Ifx_UReg_32Bit TXTE:1; /**< \brief [10:10] TX transfer error occurred on a disabled TX channel. - TXTE (rh) */
Ifx_UReg_32Bit SFO:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) - SFO (rh) */
Ifx_UReg_32Bit SFU:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) - SFU (rh) */
Ifx_UReg_32Bit MSCE:1; /**< \brief [13:13] Multi Slave scenario Command Error - MSCE (rh) */
Ifx_UReg_32Bit reserved_14:18; /**< \brief [31:14] \internal Reserved */
} Ifx_HSCT_IRQ_Bits;
/** \brief Interrupt Clear Register */
typedef struct _Ifx_HSCT_IRQCLR_Bits
{
Ifx_UReg_32Bit reserved_0:1; /**< \brief [0:0] \internal Reserved */
Ifx_UReg_32Bit HERCLR:1; /**< \brief [1:1] Header error detected interrupt clear - HERCLR (w) */
Ifx_UReg_32Bit PYERCLR:1; /**< \brief [2:2] Payload error detected interrupt clear - PYERCLR (w) */
Ifx_UReg_32Bit CERCLR:1; /**< \brief [3:3] HSCT command error interrupt clear - CERCLR (w) */
Ifx_UReg_32Bit IFCFSCLR:1; /**< \brief [4:4] HSCT interface control command send interrupt clear - IFCFSCLR (w) */
Ifx_UReg_32Bit SMERCLR:1; /**< \brief [5:5] Speed Mode Switch Error interrupt clear - SMERCLR (w) */
Ifx_UReg_32Bit USMSFCLR:1; /**< \brief [6:6] Unsolicited message frame send finished interrupt clear - USMSFCLR (w) */
Ifx_UReg_32Bit PLERCLR:1; /**< \brief [7:7] PLL lost lock error interrupt clear - PLERCLR (w) */
Ifx_UReg_32Bit USMCLR:1; /**< \brief [8:8] Unsolicited Message received clear - USMCLR (w) */
Ifx_UReg_32Bit PARCLR:1; /**< \brief [9:9] PING Answer received clear - PARCLR (w) */
Ifx_UReg_32Bit TXTECLR:1; /**< \brief [10:10] TX disable error interrupt clear - TXTECLR (w) */
Ifx_UReg_32Bit SFOCLR:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) interrupt clear - SFOCLR (w) */
Ifx_UReg_32Bit SFUCLR:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) interrupt clear - SFUCLR (w) */
Ifx_UReg_32Bit MSCELR:1; /**< \brief [13:13] Multi Slave scenario Command Error interrupt clear - MSCELR (w) */
Ifx_UReg_32Bit reserved_14:18; /**< \brief [31:14] \internal Reserved */
} Ifx_HSCT_IRQCLR_Bits;
/** \brief Interrupt Enable Register */
typedef struct _Ifx_HSCT_IRQEN_Bits
{
Ifx_UReg_32Bit reserved_0:1; /**< \brief [0:0] \internal Reserved */
Ifx_UReg_32Bit HEREN:1; /**< \brief [1:1] Header error detected interrupt enable - HEREN (rw) */
Ifx_UReg_32Bit PYEREN:1; /**< \brief [2:2] Payload error detected interrupt enable - PYEREN (rw) */
Ifx_UReg_32Bit CEREN:1; /**< \brief [3:3] HSCT command error interrupt enable - CEREN (rw) */
Ifx_UReg_32Bit IFCFSEN:1; /**< \brief [4:4] HSCT interface control command send enable - IFCFSEN (rw) */
Ifx_UReg_32Bit SMEREN:1; /**< \brief [5:5] Speed Mode Switch Error interrupt enable - SMEREN (rw) */
Ifx_UReg_32Bit USMSFEN:1; /**< \brief [6:6] Unsolicited message frame send finished - USMSFEN (rw) */
Ifx_UReg_32Bit PLEREN:1; /**< \brief [7:7] PLL lost lock error interrupt enable - PLEREN (rw) */
Ifx_UReg_32Bit USMEN:1; /**< \brief [8:8] Unsolicited Message received enable - USMEN (rw) */
Ifx_UReg_32Bit PAREN:1; /**< \brief [9:9] PING Answer Received enable - PAREN (rw) */
Ifx_UReg_32Bit TXTEEN:1; /**< \brief [10:10] TX disable error interrupt enable - TXTEEN (rw) */
Ifx_UReg_32Bit SFOEN:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) interrupt enable - SFOEN (rw) */
Ifx_UReg_32Bit SFUEN:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) interrupt enable - SFUEN (rw) */
Ifx_UReg_32Bit MSCEEN:1; /**< \brief [13:13] Multi Slave scenario Command Error interrupt enable - MSCEEN (rw) */
Ifx_UReg_32Bit reserved_14:18; /**< \brief [31:14] \internal Reserved */
} Ifx_HSCT_IRQEN_Bits;
/** \brief Reset Register 0 */
typedef struct _Ifx_HSCT_KRST0_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status - RSTSTAT (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_HSCT_KRST0_Bits;
/** \brief Reset Register 1 */
typedef struct _Ifx_HSCT_KRST1_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_HSCT_KRST1_Bits;
/** \brief Reset Status Clear Register */
typedef struct _Ifx_HSCT_KRSTCLR_Bits
{
Ifx_UReg_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear - CLR (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_HSCT_KRSTCLR_Bits;
/** \brief OCDS Control and Status */
typedef struct _Ifx_HSCT_OCS_Bits
{
Ifx_UReg_32Bit TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 - TGS (rw) */
Ifx_UReg_32Bit TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select - TGB (rw) */
Ifx_UReg_32Bit TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection - TG_P (w) */
Ifx_UReg_32Bit reserved_4:20; /**< \brief [23:4] \internal Reserved */
Ifx_UReg_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control - SUS (rw) */
Ifx_UReg_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection - SUS_P (w) */
Ifx_UReg_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State - SUSSTA (rh) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_HSCT_OCS_Bits;
/** \brief Sleep Control Register */
typedef struct _Ifx_HSCT_SLEEPCTRL_Bits
{
Ifx_UReg_32Bit SLPEN:1; /**< \brief [0:0] Sleep mode enabled - SLPEN (rw) */
Ifx_UReg_32Bit SLPCLKG:1; /**< \brief [1:1] Clock Gating in Sleep Mode - SLPCLKG (rw) */
Ifx_UReg_32Bit reserved_2:14; /**< \brief [15:2] \internal Reserved */
Ifx_UReg_32Bit WKUPCNT:8; /**< \brief [23:16] Counter Value for Determining the Wake-up Time of the LVDS Line Driver - WKUPCNT (rw) */
Ifx_UReg_32Bit reserved_24:8; /**< \brief [31:24] \internal Reserved */
} Ifx_HSCT_SLEEPCTRL_Bits;
/** \brief Status Register */
typedef struct _Ifx_HSCT_STAT_Bits
{
Ifx_UReg_32Bit RX_PSIZE:3; /**< \brief [2:0] RX (Receiving) Payload Size - RX_PSIZE (rh) */
Ifx_UReg_32Bit RX_CHANNEL:4; /**< \brief [6:3] RX (Receiving) Logical Channel Type - RX_CHANNEL (rh) */
Ifx_UReg_32Bit RX_SLEEP:1; /**< \brief [7:7] RX (Receiving) Sleep Mode Status - RX_SLEEP (rh) */
Ifx_UReg_32Bit TX_SLEEP:1; /**< \brief [8:8] TX (Transmission) Sleep Mode Status - TX_SLEEP (rh) */
Ifx_UReg_32Bit reserved_9:3; /**< \brief [11:9] \internal Reserved */
Ifx_UReg_32Bit TX_PSIZE:3; /**< \brief [14:12] Transmission Payload Size - TX_PSIZE (rh) */
Ifx_UReg_32Bit reserved_15:1; /**< \brief [15:15] \internal Reserved */
Ifx_UReg_32Bit TX_CHANNEL_TYPE:4; /**< \brief [19:16] Transmission Logical Channel Type - TX_CHANNEL_TYPE (rh) */
Ifx_UReg_32Bit reserved_20:4; /**< \brief [23:20] \internal Reserved */
Ifx_UReg_32Bit LIFCCMDR:8; /**< \brief [31:24] Last Interface Control Command Received - LIFCCMDR (rh) */
} Ifx_HSCT_STAT_Bits;
/** \brief STATPHY */
typedef struct _Ifx_HSCT_STATPHY_Bits
{
Ifx_UReg_32Bit PLOCK:1; /**< \brief [0:0] PLL locked - PLOCK (rh) */
Ifx_UReg_32Bit reserved_1:1; /**< \brief [1:1] \internal Reserved */
Ifx_UReg_32Bit TXSA:2; /**< \brief [3:2] Transmitter speed - TXSA (rh) */
Ifx_UReg_32Bit RXSA:2; /**< \brief [5:4] Receiver speed - RXSA (rh) */
Ifx_UReg_32Bit reserved_6:26; /**< \brief [31:6] \internal Reserved */
} Ifx_HSCT_STATPHY_Bits;
/** \brief Test Control Register */
typedef struct _Ifx_HSCT_TESTCTRL_Bits
{
Ifx_UReg_32Bit TXENS:1; /**< \brief [0:0] Enable Slave TX path (Slave interface mode only) - TXENS (w) */
Ifx_UReg_32Bit TXDISS:1; /**< \brief [1:1] Disable Slave TX path (Slave Interface mode only) - TXDISS (w) */
Ifx_UReg_32Bit LLOPTXRX:1; /**< \brief [2:2] LVDS loop back TX to RX enable - LLOPTXRX (rw) */
Ifx_UReg_32Bit PRBSEN:1; /**< \brief [3:3] PRBS Pattern enable - PRBSEN (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_HSCT_TESTCTRL_Bits;
/** \brief Unsolicited Status Message Received */
typedef struct _Ifx_HSCT_USMR_Bits
{
Ifx_UReg_32Bit USMR:32; /**< \brief [31:0] Unsolicited status message received - USMR (rh) */
} Ifx_HSCT_USMR_Bits;
/** \brief Unsolicited Status Message Send */
typedef struct _Ifx_HSCT_USMS_Bits
{
Ifx_UReg_32Bit USMS:32; /**< \brief [31:0] Unsolicited status message send - USMS (rw) */
} Ifx_HSCT_USMS_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_hsct_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_ACCEN0;
/** \brief Access Enable Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_ACCEN1_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_ACCEN1;
/** \brief Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_CLC;
/** \brief Configuration Physical Layer Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_CONFIGPHY_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_CONFIGPHY;
/** \brief Clear To Send Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_CTSCTRL_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_CTSCTRL;
/** \brief Transmission Disable Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_DISABLE_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_DISABLE;
/** \brief Module Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_ID_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_ID;
/** \brief Interface Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_IFCTRL_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_IFCTRL;
/** \brief Interface Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_IFSTAT_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_IFSTAT;
/** \brief Initialization Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_INIT_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_INIT;
/** \brief Interrupt register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_IRQ_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_IRQ;
/** \brief Interrupt Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_IRQCLR_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_IRQCLR;
/** \brief Interrupt Enable Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_IRQEN_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_IRQEN;
/** \brief Reset Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_KRST0_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_KRST0;
/** \brief Reset Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_KRST1_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_KRST1;
/** \brief Reset Status Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_KRSTCLR_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_KRSTCLR;
/** \brief OCDS Control and Status */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_OCS_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_OCS;
/** \brief Sleep Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_SLEEPCTRL_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_SLEEPCTRL;
/** \brief Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_STAT_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_STAT;
/** \brief STATPHY */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_STATPHY_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_STATPHY;
/** \brief Test Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_TESTCTRL_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_TESTCTRL;
/** \brief Unsolicited Status Message Received */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_USMR_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_USMR;
/** \brief Unsolicited Status Message Send */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSCT_USMS_Bits B; /**< \brief Bitfield access */
} Ifx_HSCT_USMS;
/** \} */
/******************************************************************************/
/** \addtogroup IfxSfr_Hsct_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief HSCT object */
typedef volatile struct _Ifx_HSCT
{
Ifx_HSCT_CLC CLC; /**< \brief 0, Clock Control Register*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_HSCT_ID ID; /**< \brief 8, Module Identification Register*/
Ifx_UReg_8Bit reserved_C[4]; /**< \brief C, \internal Reserved */
Ifx_HSCT_INIT INIT; /**< \brief 10, Initialization Register*/
Ifx_HSCT_IFCTRL IFCTRL; /**< \brief 14, Interface Control Register*/
Ifx_HSCT_SLEEPCTRL SLEEPCTRL; /**< \brief 18, Sleep Control Register*/
Ifx_HSCT_CTSCTRL CTSCTRL; /**< \brief 1C, Clear To Send Control Register*/
Ifx_HSCT_DISABLE DISABLE; /**< \brief 20, Transmission Disable Register*/
Ifx_HSCT_STAT STAT; /**< \brief 24, Status Register*/
Ifx_HSCT_IFSTAT IFSTAT; /**< \brief 28, Interface Status Register*/
Ifx_UReg_8Bit reserved_2C[4]; /**< \brief 2C, \internal Reserved */
Ifx_HSCT_CONFIGPHY CONFIGPHY; /**< \brief 30, Configuration Physical Layer Register*/
Ifx_HSCT_STATPHY STATPHY; /**< \brief 34, STATPHY*/
Ifx_UReg_8Bit reserved_38[8]; /**< \brief 38, \internal Reserved */
Ifx_HSCT_IRQ IRQ; /**< \brief 40, Interrupt register*/
Ifx_HSCT_IRQEN IRQEN; /**< \brief 44, Interrupt Enable Register*/
Ifx_HSCT_IRQCLR IRQCLR; /**< \brief 48, Interrupt Clear Register*/
Ifx_UReg_8Bit reserved_4C[4]; /**< \brief 4C, \internal Reserved */
Ifx_HSCT_USMR USMR; /**< \brief 50, Unsolicited Status Message Received*/
Ifx_HSCT_USMS USMS; /**< \brief 54, Unsolicited Status Message Send*/
Ifx_UReg_8Bit reserved_58[8]; /**< \brief 58, \internal Reserved */
Ifx_HSCT_TESTCTRL TESTCTRL; /**< \brief 60, Test Control Register*/
Ifx_UReg_8Bit reserved_64[65412]; /**< \brief 64, \internal Reserved */
Ifx_HSCT_OCS OCS; /**< \brief FFE8, OCDS Control and Status*/
Ifx_HSCT_KRSTCLR KRSTCLR; /**< \brief FFEC, Reset Status Clear Register*/
Ifx_HSCT_KRST1 KRST1; /**< \brief FFF0, Reset Register 1*/
Ifx_HSCT_KRST0 KRST0; /**< \brief FFF4, Reset Register 0*/
Ifx_HSCT_ACCEN1 ACCEN1; /**< \brief FFF8, Access Enable Register 1*/
Ifx_HSCT_ACCEN0 ACCEN0; /**< \brief FFFC, Access Enable Register 0*/
} Ifx_HSCT;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXHSCT_REGDEF_H */

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/**
* \file IfxHssl_reg.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Hssl_Registers_Cfg Hssl address
* \ingroup IfxSfr_Hssl_Registers
*
* \defgroup IfxSfr_Hssl_Registers_Cfg_BaseAddress Base address
* \ingroup IfxSfr_Hssl_Registers_Cfg
*
* \defgroup IfxSfr_Hssl_Registers_Cfg_Hssl0 2-HSSL0
* \ingroup IfxSfr_Hssl_Registers_Cfg
*
*
*/
#ifndef IFXHSSL_REG_H
#define IFXHSSL_REG_H 1
/******************************************************************************/
#include "IfxHssl_regdef.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_Registers_Cfg_BaseAddress
* \{ */
/** \brief HSSL object */
#define MODULE_HSSL0 /*lint --e(923, 9078)*/ ((*(Ifx_HSSL*)0xF0080000u))
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_Registers_Cfg_Hssl0
* \{ */
/** \brief 0, Clock Control Register */
#define HSSL0_CLC /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_CLC*)0xF0080000u)
/** \brief 8, Module Identification Register */
#define HSSL0_ID /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_ID*)0xF0080008u)
/** \brief C, CRC Control Register */
#define HSSL0_CRC /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_CRC*)0xF008000Cu)
/** \brief 10, Configuration Register */
#define HSSL0_CFG /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_CFG*)0xF0080010u)
/** \brief 14, Request Flags Register */
#define HSSL0_QFLAGS /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_QFLAGS*)0xF0080014u)
/** \brief 18, Miscellaneous Flags Register */
#define HSSL0_MFLAGS /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_MFLAGS*)0xF0080018u)
/** \brief 1C, Miscellaneous Flags Set Register */
#define HSSL0_MFLAGSSET /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_MFLAGSSET*)0xF008001Cu)
/** \brief 20, Miscellaneous Flags Clear Register */
#define HSSL0_MFLAGSCL /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_MFLAGSCL*)0xF0080020u)
/** \brief 24, Flags Enable Register */
#define HSSL0_MFLAGSEN /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_MFLAGSEN*)0xF0080024u)
/** \brief 28, Stream FIFOs Status Flags Register */
#define HSSL0_SFSFLAGS /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_SFSFLAGS*)0xF0080028u)
/** \brief 30, Initiator Write Data Register 0 */
#define HSSL0_I0_IWD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080030u)
/** Alias (User Manual Name) for HSSL0_I0_IWD.
* To use register names with standard convension, please use HSSL0_I0_IWD.
*/
#define HSSL0_IWD0 (HSSL0_I0_IWD)
/** \brief 34, Initiator Control Data Register 0 */
#define HSSL0_I0_ICON /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080034u)
/** Alias (User Manual Name) for HSSL0_I0_ICON.
* To use register names with standard convension, please use HSSL0_I0_ICON.
*/
#define HSSL0_ICON0 (HSSL0_I0_ICON)
/** \brief 38, Initiator Read Write Address Register 0 */
#define HSSL0_I0_IRWA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080038u)
/** Alias (User Manual Name) for HSSL0_I0_IRWA.
* To use register names with standard convension, please use HSSL0_I0_IRWA.
*/
#define HSSL0_IRWA0 (HSSL0_I0_IRWA)
/** \brief 3C, Initiator Read Data Register 0 */
#define HSSL0_I0_IRD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008003Cu)
/** Alias (User Manual Name) for HSSL0_I0_IRD.
* To use register names with standard convension, please use HSSL0_I0_IRD.
*/
#define HSSL0_IRD0 (HSSL0_I0_IRD)
/** \brief 40, Initiator Write Data Register 1 */
#define HSSL0_I1_IWD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080040u)
/** Alias (User Manual Name) for HSSL0_I1_IWD.
* To use register names with standard convension, please use HSSL0_I1_IWD.
*/
#define HSSL0_IWD1 (HSSL0_I1_IWD)
/** \brief 44, Initiator Control Data Register 1 */
#define HSSL0_I1_ICON /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080044u)
/** Alias (User Manual Name) for HSSL0_I1_ICON.
* To use register names with standard convension, please use HSSL0_I1_ICON.
*/
#define HSSL0_ICON1 (HSSL0_I1_ICON)
/** \brief 48, Initiator Read Write Address Register 1 */
#define HSSL0_I1_IRWA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080048u)
/** Alias (User Manual Name) for HSSL0_I1_IRWA.
* To use register names with standard convension, please use HSSL0_I1_IRWA.
*/
#define HSSL0_IRWA1 (HSSL0_I1_IRWA)
/** \brief 4C, Initiator Read Data Register 1 */
#define HSSL0_I1_IRD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008004Cu)
/** Alias (User Manual Name) for HSSL0_I1_IRD.
* To use register names with standard convension, please use HSSL0_I1_IRD.
*/
#define HSSL0_IRD1 (HSSL0_I1_IRD)
/** \brief 50, Initiator Write Data Register 2 */
#define HSSL0_I2_IWD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080050u)
/** Alias (User Manual Name) for HSSL0_I2_IWD.
* To use register names with standard convension, please use HSSL0_I2_IWD.
*/
#define HSSL0_IWD2 (HSSL0_I2_IWD)
/** \brief 54, Initiator Control Data Register 2 */
#define HSSL0_I2_ICON /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080054u)
/** Alias (User Manual Name) for HSSL0_I2_ICON.
* To use register names with standard convension, please use HSSL0_I2_ICON.
*/
#define HSSL0_ICON2 (HSSL0_I2_ICON)
/** \brief 58, Initiator Read Write Address Register 2 */
#define HSSL0_I2_IRWA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080058u)
/** Alias (User Manual Name) for HSSL0_I2_IRWA.
* To use register names with standard convension, please use HSSL0_I2_IRWA.
*/
#define HSSL0_IRWA2 (HSSL0_I2_IRWA)
/** \brief 5C, Initiator Read Data Register 2 */
#define HSSL0_I2_IRD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008005Cu)
/** Alias (User Manual Name) for HSSL0_I2_IRD.
* To use register names with standard convension, please use HSSL0_I2_IRD.
*/
#define HSSL0_IRD2 (HSSL0_I2_IRD)
/** \brief 60, Initiator Write Data Register 3 */
#define HSSL0_I3_IWD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080060u)
/** Alias (User Manual Name) for HSSL0_I3_IWD.
* To use register names with standard convension, please use HSSL0_I3_IWD.
*/
#define HSSL0_IWD3 (HSSL0_I3_IWD)
/** \brief 64, Initiator Control Data Register 3 */
#define HSSL0_I3_ICON /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080064u)
/** Alias (User Manual Name) for HSSL0_I3_ICON.
* To use register names with standard convension, please use HSSL0_I3_ICON.
*/
#define HSSL0_ICON3 (HSSL0_I3_ICON)
/** \brief 68, Initiator Read Write Address Register 3 */
#define HSSL0_I3_IRWA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080068u)
/** Alias (User Manual Name) for HSSL0_I3_IRWA.
* To use register names with standard convension, please use HSSL0_I3_IRWA.
*/
#define HSSL0_IRWA3 (HSSL0_I3_IRWA)
/** \brief 6C, Initiator Read Data Register 3 */
#define HSSL0_I3_IRD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008006Cu)
/** Alias (User Manual Name) for HSSL0_I3_IRD.
* To use register names with standard convension, please use HSSL0_I3_IRD.
*/
#define HSSL0_IRD3 (HSSL0_I3_IRD)
/** \brief 70, Target Current Data Register 0 */
#define HSSL0_T0_TCD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080070u)
/** Alias (User Manual Name) for HSSL0_T0_TCD.
* To use register names with standard convension, please use HSSL0_T0_TCD.
*/
#define HSSL0_TCD0 (HSSL0_T0_TCD)
/** \brief 74, Target Current Address Register 0 */
#define HSSL0_T0_TCA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF0080074u)
/** Alias (User Manual Name) for HSSL0_T0_TCA.
* To use register names with standard convension, please use HSSL0_T0_TCA.
*/
#define HSSL0_TCA0 (HSSL0_T0_TCA)
/** \brief 78, Target Current Data Register 1 */
#define HSSL0_T1_TCD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080078u)
/** Alias (User Manual Name) for HSSL0_T1_TCD.
* To use register names with standard convension, please use HSSL0_T1_TCD.
*/
#define HSSL0_TCD1 (HSSL0_T1_TCD)
/** \brief 7C, Target Current Address Register 1 */
#define HSSL0_T1_TCA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF008007Cu)
/** Alias (User Manual Name) for HSSL0_T1_TCA.
* To use register names with standard convension, please use HSSL0_T1_TCA.
*/
#define HSSL0_TCA1 (HSSL0_T1_TCA)
/** \brief 80, Target Current Data Register 2 */
#define HSSL0_T2_TCD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080080u)
/** Alias (User Manual Name) for HSSL0_T2_TCD.
* To use register names with standard convension, please use HSSL0_T2_TCD.
*/
#define HSSL0_TCD2 (HSSL0_T2_TCD)
/** \brief 84, Target Current Address Register 2 */
#define HSSL0_T2_TCA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF0080084u)
/** Alias (User Manual Name) for HSSL0_T2_TCA.
* To use register names with standard convension, please use HSSL0_T2_TCA.
*/
#define HSSL0_TCA2 (HSSL0_T2_TCA)
/** \brief 88, Target Current Data Register 3 */
#define HSSL0_T3_TCD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080088u)
/** Alias (User Manual Name) for HSSL0_T3_TCD.
* To use register names with standard convension, please use HSSL0_T3_TCD.
*/
#define HSSL0_TCD3 (HSSL0_T3_TCD)
/** \brief 8C, Target Current Address Register 3 */
#define HSSL0_T3_TCA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF008008Cu)
/** Alias (User Manual Name) for HSSL0_T3_TCA.
* To use register names with standard convension, please use HSSL0_T3_TCA.
*/
#define HSSL0_TCA3 (HSSL0_T3_TCA)
/** \brief 90, Target Status Register */
#define HSSL0_TSTAT /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_TSTAT*)0xF0080090u)
/** \brief 94, Target ID Address Register */
#define HSSL0_TIDADD /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_TIDADD*)0xF0080094u)
/** \brief 98, Security Control Register */
#define HSSL0_SEC /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_SEC*)0xF0080098u)
/** \brief 9C, Multi Slave Control Register */
#define HSSL0_MSCR /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_MSCR*)0xF008009Cu)
/** \brief A0, Initiator Stream Start Address Register */
#define HSSL0_IS_SA0 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_IS_SA*)0xF00800A0u)
/** Alias (User Manual Name) for HSSL0_IS_SA0.
* To use register names with standard convension, please use HSSL0_IS_SA0.
*/
#define HSSL0_ISSA0 (HSSL0_IS_SA0)
/** \brief A4, Initiator Stream Start Address Register */
#define HSSL0_IS_SA1 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_IS_SA*)0xF00800A4u)
/** Alias (User Manual Name) for HSSL0_IS_SA1.
* To use register names with standard convension, please use HSSL0_IS_SA1.
*/
#define HSSL0_ISSA1 (HSSL0_IS_SA1)
/** \brief A8, Initiator Stream Current Address Register */
#define HSSL0_IS_CA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_IS_CA*)0xF00800A8u)
/** Alias (User Manual Name) for HSSL0_IS_CA.
* To use register names with standard convension, please use HSSL0_IS_CA.
*/
#define HSSL0_ISCA (HSSL0_IS_CA)
/** \brief AC, Initiator Stream Frame Count Register */
#define HSSL0_IS_FC /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_IS_FC*)0xF00800ACu)
/** Alias (User Manual Name) for HSSL0_IS_FC.
* To use register names with standard convension, please use HSSL0_IS_FC.
*/
#define HSSL0_ISFC (HSSL0_IS_FC)
/** \brief B0, Target Stream Start Address Register 0 */
#define HSSL0_TS_SA0 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_TS_SA*)0xF00800B0u)
/** Alias (User Manual Name) for HSSL0_TS_SA0.
* To use register names with standard convension, please use HSSL0_TS_SA0.
*/
#define HSSL0_TSSA0 (HSSL0_TS_SA0)
/** \brief B4, Target Stream Start Address Register 1 */
#define HSSL0_TS_SA1 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_TS_SA*)0xF00800B4u)
/** Alias (User Manual Name) for HSSL0_TS_SA1.
* To use register names with standard convension, please use HSSL0_TS_SA1.
*/
#define HSSL0_TSSA1 (HSSL0_TS_SA1)
/** \brief B8, Target Stream Current Address Register */
#define HSSL0_TS_CA /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_TS_CA*)0xF00800B8u)
/** Alias (User Manual Name) for HSSL0_TS_CA.
* To use register names with standard convension, please use HSSL0_TS_CA.
*/
#define HSSL0_TSCA (HSSL0_TS_CA)
/** \brief BC, Target Stream Frame Count Register */
#define HSSL0_TS_FC /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_TS_FC*)0xF00800BCu)
/** Alias (User Manual Name) for HSSL0_TS_FC.
* To use register names with standard convension, please use HSSL0_TS_FC.
*/
#define HSSL0_TSFC (HSSL0_TS_FC)
/** \brief C0, Access Window Start Register 0 */
#define HSSL0_AW0_AWSTART /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800C0u)
/** Alias (User Manual Name) for HSSL0_AW0_AWSTART.
* To use register names with standard convension, please use HSSL0_AW0_AWSTART.
*/
#define HSSL0_AWSTART0 (HSSL0_AW0_AWSTART)
/** \brief C4, Access Window End Register 0 */
#define HSSL0_AW0_AWEND /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800C4u)
/** Alias (User Manual Name) for HSSL0_AW0_AWEND.
* To use register names with standard convension, please use HSSL0_AW0_AWEND.
*/
#define HSSL0_AWEND0 (HSSL0_AW0_AWEND)
/** \brief C8, Access Window Start Register 1 */
#define HSSL0_AW1_AWSTART /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800C8u)
/** Alias (User Manual Name) for HSSL0_AW1_AWSTART.
* To use register names with standard convension, please use HSSL0_AW1_AWSTART.
*/
#define HSSL0_AWSTART1 (HSSL0_AW1_AWSTART)
/** \brief CC, Access Window End Register 1 */
#define HSSL0_AW1_AWEND /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800CCu)
/** Alias (User Manual Name) for HSSL0_AW1_AWEND.
* To use register names with standard convension, please use HSSL0_AW1_AWEND.
*/
#define HSSL0_AWEND1 (HSSL0_AW1_AWEND)
/** \brief D0, Access Window Start Register 2 */
#define HSSL0_AW2_AWSTART /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800D0u)
/** Alias (User Manual Name) for HSSL0_AW2_AWSTART.
* To use register names with standard convension, please use HSSL0_AW2_AWSTART.
*/
#define HSSL0_AWSTART2 (HSSL0_AW2_AWSTART)
/** \brief D4, Access Window End Register 2 */
#define HSSL0_AW2_AWEND /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800D4u)
/** Alias (User Manual Name) for HSSL0_AW2_AWEND.
* To use register names with standard convension, please use HSSL0_AW2_AWEND.
*/
#define HSSL0_AWEND2 (HSSL0_AW2_AWEND)
/** \brief D8, Access Window Start Register 3 */
#define HSSL0_AW3_AWSTART /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800D8u)
/** Alias (User Manual Name) for HSSL0_AW3_AWSTART.
* To use register names with standard convension, please use HSSL0_AW3_AWSTART.
*/
#define HSSL0_AWSTART3 (HSSL0_AW3_AWSTART)
/** \brief DC, Access Window End Register 3 */
#define HSSL0_AW3_AWEND /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800DCu)
/** Alias (User Manual Name) for HSSL0_AW3_AWEND.
* To use register names with standard convension, please use HSSL0_AW3_AWEND.
*/
#define HSSL0_AWEND3 (HSSL0_AW3_AWEND)
/** \brief E0, Access Rules Register */
#define HSSL0_AR /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_AR*)0xF00800E0u)
/** \brief E8, OCDS Control and Status */
#define HSSL0_OCS /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_OCS*)0xF00800E8u)
/** \brief EC, Kernel Reset Status Clear Register */
#define HSSL0_KRSTCLR /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_KRSTCLR*)0xF00800ECu)
/** \brief F0, Kernel Reset Register 1 */
#define HSSL0_KRST1 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_KRST1*)0xF00800F0u)
/** \brief F4, Kernel Reset Register 0 */
#define HSSL0_KRST0 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_KRST0*)0xF00800F4u)
/** \brief F8, Access Enable Register 1 */
#define HSSL0_ACCEN1 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_ACCEN1*)0xF00800F8u)
/** \brief FC, Access Enable Register 0 */
#define HSSL0_ACCEN0 /*lint --e(923, 9078)*/ (*(volatile Ifx_HSSL_ACCEN0*)0xF00800FCu)
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXHSSL_REG_H */

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/**
* \file IfxHssl_regdef.h
* \brief
* \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
*
*
* Version: TC37xPD_UM_V1.5.0
* Specification: TC3xx User Manual V1.5.0
* MAY BE CHANGED BY USER [yes/no]: No
*
* IMPORTANT NOTICE
*
* Use of this file is subject to the terms of use agreed between (i) you or
* the company in which ordinary course of business you are acting and (ii)
* Infineon Technologies AG or its licensees. If and as long as no such terms
* of use are agreed, use of this file is subject to following:
*
* Boost Software License - Version 1.0 - August 17th, 2003
*
* Permission is hereby granted, free of charge, to any person or organization
* obtaining a copy of the software and accompanying documentation covered by
* this license (the "Software") to use, reproduce, display, distribute,
* execute, and transmit the Software, and to prepare derivative works of the
* Software, and to permit third-parties to whom the Software is furnished to
* do so, all subject to the following:
*
* The copyright notices in the Software and this entire statement, including
* the above license grant, this restriction and the following disclaimer, must
* be included in all copies of the Software, in whole or in part, and all
* derivative works of the Software, unless such copies or derivative works are
* solely in the form of machine-executable object code generated by a source
* language processor.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* \defgroup IfxSfr_Hssl_Registers Hssl Registers
* \ingroup IfxSfr
*
* \defgroup IfxSfr_Hssl_Registers_Bitfields Bitfields
* \ingroup IfxSfr_Hssl_Registers
*
* \defgroup IfxSfr_Hssl_Registers_union Register unions
* \ingroup IfxSfr_Hssl_Registers
*
* \defgroup IfxSfr_Hssl_Registers_struct Memory map
* \ingroup IfxSfr_Hssl_Registers
*/
#ifndef IFXHSSL_REGDEF_H
#define IFXHSSL_REGDEF_H 1
/******************************************************************************/
#include "Ifx_TypesReg.h"
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_Registers_Bitfields
* \{ */
/** \brief Access Enable Register 0 */
typedef struct _Ifx_HSSL_ACCEN0_Bits
{
Ifx_UReg_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 - EN0 (rw) */
Ifx_UReg_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 - EN1 (rw) */
Ifx_UReg_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 - EN2 (rw) */
Ifx_UReg_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 - EN3 (rw) */
Ifx_UReg_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 - EN4 (rw) */
Ifx_UReg_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 - EN5 (rw) */
Ifx_UReg_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 - EN6 (rw) */
Ifx_UReg_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 - EN7 (rw) */
Ifx_UReg_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 - EN8 (rw) */
Ifx_UReg_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 - EN9 (rw) */
Ifx_UReg_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 - EN10 (rw) */
Ifx_UReg_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 - EN11 (rw) */
Ifx_UReg_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 - EN12 (rw) */
Ifx_UReg_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 - EN13 (rw) */
Ifx_UReg_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 - EN14 (rw) */
Ifx_UReg_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 - EN15 (rw) */
Ifx_UReg_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 - EN16 (rw) */
Ifx_UReg_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 - EN17 (rw) */
Ifx_UReg_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 - EN18 (rw) */
Ifx_UReg_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 - EN19 (rw) */
Ifx_UReg_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 - EN20 (rw) */
Ifx_UReg_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 - EN21 (rw) */
Ifx_UReg_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 - EN22 (rw) */
Ifx_UReg_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 - EN23 (rw) */
Ifx_UReg_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 - EN24 (rw) */
Ifx_UReg_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 - EN25 (rw) */
Ifx_UReg_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 - EN26 (rw) */
Ifx_UReg_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 - EN27 (rw) */
Ifx_UReg_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 - EN28 (rw) */
Ifx_UReg_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 - EN29 (rw) */
Ifx_UReg_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 - EN30 (rw) */
Ifx_UReg_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 - EN31 (rw) */
} Ifx_HSSL_ACCEN0_Bits;
/** \brief Access Enable Register 1 */
typedef struct _Ifx_HSSL_ACCEN1_Bits
{
Ifx_UReg_32Bit reserved_0:32; /**< \brief [31:0] \internal Reserved */
} Ifx_HSSL_ACCEN1_Bits;
/** \brief Access Rules Register */
typedef struct _Ifx_HSSL_AR_Bits
{
Ifx_UReg_32Bit ARW0:2; /**< \brief [1:0] Access Rule for Window 0 - ARW0 (rw) */
Ifx_UReg_32Bit ARW1:2; /**< \brief [3:2] Access Rule for Window 1 - ARW1 (rw) */
Ifx_UReg_32Bit ARW2:2; /**< \brief [5:4] Access Rule for Window 2 - ARW2 (rw) */
Ifx_UReg_32Bit ARW3:2; /**< \brief [7:6] Access Rule for Window 3 - ARW3 (rw) */
Ifx_UReg_32Bit reserved_8:8; /**< \brief [15:8] \internal Reserved */
Ifx_UReg_32Bit MAVCH:2; /**< \brief [17:16] Memory Access Violation Channel - MAVCH (rh) */
Ifx_UReg_32Bit reserved_18:14; /**< \brief [31:18] \internal Reserved */
} Ifx_HSSL_AR_Bits;
/** \brief Access Window End Register ${i} */
typedef struct _Ifx_HSSL_AW_AWEND_Bits
{
Ifx_UReg_32Bit reserved_0:8; /**< \brief [7:0] \internal Reserved */
Ifx_UReg_32Bit AWE:24; /**< \brief [31:8] Access Window End Address - AWE (rw) */
} Ifx_HSSL_AW_AWEND_Bits;
/** \brief Access Window Start Register ${i} */
typedef struct _Ifx_HSSL_AW_AWSTART_Bits
{
Ifx_UReg_32Bit reserved_0:8; /**< \brief [7:0] \internal Reserved */
Ifx_UReg_32Bit AWS:24; /**< \brief [31:8] Access Window Start Address - AWS (rw) */
} Ifx_HSSL_AW_AWSTART_Bits;
/** \brief Configuration Register */
typedef struct _Ifx_HSSL_CFG_Bits
{
Ifx_UReg_32Bit PREDIV:14; /**< \brief [13:0] Global Predivider - PREDIV (rw) */
Ifx_UReg_32Bit reserved_14:2; /**< \brief [15:14] \internal Reserved */
Ifx_UReg_32Bit SMT:1; /**< \brief [16:16] Streaming Mode Transmitter - SMT (rw) */
Ifx_UReg_32Bit SMR:1; /**< \brief [17:17] Streaming Mode Receiver - SMR (rw) */
Ifx_UReg_32Bit SCM:1; /**< \brief [18:18] Streaming Channel Mode - SCM (rw) */
Ifx_UReg_32Bit CCC:1; /**< \brief [19:19] Channel Code Control - CCC (rw) */
Ifx_UReg_32Bit reserved_20:12; /**< \brief [31:20] \internal Reserved */
} Ifx_HSSL_CFG_Bits;
/** \brief Clock Control Register */
typedef struct _Ifx_HSSL_CLC_Bits
{
Ifx_UReg_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit - DISR (rw) */
Ifx_UReg_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit - DISS (rh) */
Ifx_UReg_32Bit reserved_2:1; /**< \brief [2:2] \internal Reserved */
Ifx_UReg_32Bit EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control - EDIS (rw) */
Ifx_UReg_32Bit reserved_4:28; /**< \brief [31:4] \internal Reserved */
} Ifx_HSSL_CLC_Bits;
/** \brief CRC Control Register */
typedef struct _Ifx_HSSL_CRC_Bits
{
Ifx_UReg_32Bit XORMASK:16; /**< \brief [15:0] Value to be XORed with the Calculated CRC - XORMASK (rw) */
Ifx_UReg_32Bit XEN:1; /**< \brief [16:16] Enable the Error Injection via XORMASK - XEN (rw) */
Ifx_UReg_32Bit reserved_17:15; /**< \brief [31:17] \internal Reserved */
} Ifx_HSSL_CRC_Bits;
/** \brief Module Identification Register */
typedef struct _Ifx_HSSL_ID_Bits
{
Ifx_UReg_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number - MODREV (r) */
Ifx_UReg_32Bit MODTYPE:8; /**< \brief [15:8] Module Type - MODTYPE (r) */
Ifx_UReg_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value - MODNUMBER (r) */
} Ifx_HSSL_ID_Bits;
/** \brief Initiator Stream Current Address Register */
typedef struct _Ifx_HSSL_IS_CA_Bits
{
Ifx_UReg_32Bit reserved_0:5; /**< \brief [4:0] \internal Reserved */
Ifx_UReg_32Bit CURR:27; /**< \brief [31:5] Address of the Memory Location for the Current Transfer - CURR (rh) */
} Ifx_HSSL_IS_CA_Bits;
/** \brief Initiator Stream Frame Count Register */
typedef struct _Ifx_HSSL_IS_FC_Bits
{
Ifx_UReg_32Bit RELCOUNT:16; /**< \brief [15:0] Reload Count Number - RELCOUNT (rw) */
Ifx_UReg_32Bit CURCOUNT:16; /**< \brief [31:16] Current Count Number - CURCOUNT (rh) */
} Ifx_HSSL_IS_FC_Bits;
/** \brief Initiator Stream Start Address Register */
typedef struct _Ifx_HSSL_IS_SA_Bits
{
Ifx_UReg_32Bit reserved_0:5; /**< \brief [4:0] \internal Reserved */
Ifx_UReg_32Bit START:27; /**< \brief [31:5] Start Address for the Memory Range - START (rw) */
} Ifx_HSSL_IS_SA_Bits;
/** \brief Initiator Control Data Register ${x} */
typedef struct _Ifx_HSSL_I_ICON_Bits
{
Ifx_UReg_32Bit IDQ:1; /**< \brief [0:0] Read ID Request - IDQ (w) */
Ifx_UReg_32Bit TQ:1; /**< \brief [1:1] Trigger Request - TQ (w) */
Ifx_UReg_32Bit LETT:3; /**< \brief [4:2] Last Error Transaction Tag - LETT (rh) */
Ifx_UReg_32Bit CETT:3; /**< \brief [7:5] Currently Expected Transaction Tag - CETT (rh) */
Ifx_UReg_32Bit TOCV:8; /**< \brief [15:8] Time Out Current Value - TOCV (rh) */
Ifx_UReg_32Bit DATLEN:2; /**< \brief [17:16] Data Length - DATLEN (rw) */
Ifx_UReg_32Bit RWT:2; /**< \brief [19:18] Read Write Trigger Command Type - RWT (rw) */
Ifx_UReg_32Bit BSY:1; /**< \brief [20:20] Channel Busy - BSY (rh) */
Ifx_UReg_32Bit ITTAG:3; /**< \brief [23:21] Initiator Transaction Tag - ITTAG (rh) */
Ifx_UReg_32Bit TOREL:8; /**< \brief [31:24] Time Out Reload Value - TOREL (rw) */
} Ifx_HSSL_I_ICON_Bits;
/** \brief Initiator Read Data Register ${x} */
typedef struct _Ifx_HSSL_I_IRD_Bits
{
Ifx_UReg_32Bit DATA:32; /**< \brief [31:0] Data Delivered by a Read Response Frame - DATA (rh) */
} Ifx_HSSL_I_IRD_Bits;
/** \brief Initiator Read Write Address Register ${x} */
typedef struct _Ifx_HSSL_I_IRWA_Bits
{
Ifx_UReg_32Bit ADDRESS:32; /**< \brief [31:0] Address Part of the Payload of a Write Frame - ADDRESS (rw) */
} Ifx_HSSL_I_IRWA_Bits;
/** \brief Initiator Write Data Register ${x} */
typedef struct _Ifx_HSSL_I_IWD_Bits
{
Ifx_UReg_32Bit DATA:32; /**< \brief [31:0] Data Part of the Payload of a Write Frame - DATA (rw) */
} Ifx_HSSL_I_IWD_Bits;
/** \brief Kernel Reset Register 0 */
typedef struct _Ifx_HSSL_KRST0_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status - RSTSTAT (rh) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_HSSL_KRST0_Bits;
/** \brief Kernel Reset Register 1 */
typedef struct _Ifx_HSSL_KRST1_Bits
{
Ifx_UReg_32Bit RST:1; /**< \brief [0:0] Kernel Reset - RST (rwh) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_HSSL_KRST1_Bits;
/** \brief Kernel Reset Status Clear Register */
typedef struct _Ifx_HSSL_KRSTCLR_Bits
{
Ifx_UReg_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear - CLR (w) */
Ifx_UReg_32Bit reserved_1:31; /**< \brief [31:1] \internal Reserved */
} Ifx_HSSL_KRSTCLR_Bits;
/** \brief Miscellaneous Flags Register */
typedef struct _Ifx_HSSL_MFLAGS_Bits
{
Ifx_UReg_32Bit NACK:4; /**< \brief [3:0] Not Acknowledge Error - Target Error - NACK (rh) */
Ifx_UReg_32Bit TTE:4; /**< \brief [7:4] Transaction Tag Error - TTE (rh) */
Ifx_UReg_32Bit TIMEOUT:4; /**< \brief [11:8] Timeout Error - TIMEOUT (rh) */
Ifx_UReg_32Bit UNEXPECTED:4; /**< \brief [15:12] Unexpected Type of Frame Error - UNEXPECTED (rh) */
Ifx_UReg_32Bit reserved_16:2; /**< \brief [17:16] \internal Reserved */
Ifx_UReg_32Bit TMB:1; /**< \brief [18:18] Target Memory Block - TMB (rh) */
Ifx_UReg_32Bit IMB:1; /**< \brief [19:19] Initiator Memory Block - IMB (rh) */
Ifx_UReg_32Bit ISB:1; /**< \brief [20:20] Initiator Stream Block Request - ISB (rh) */
Ifx_UReg_32Bit MAV:1; /**< \brief [21:21] Memory Access Violation - MAV (rh) */
Ifx_UReg_32Bit SRIE:1; /**< \brief [22:22] SRI/SPB Bus Access Error - SRIE (rh) */
Ifx_UReg_32Bit PIE1:1; /**< \brief [23:23] PHY Inconsistency Error 1(Channel Number Code Error) - PIE1 (rh) */
Ifx_UReg_32Bit PIE2:1; /**< \brief [24:24] PHY Inconsistency Error 2(Data Length Error) - PIE2 (rh) */
Ifx_UReg_32Bit CRCE:1; /**< \brief [25:25] CRC Error - CRCE (rh) */
Ifx_UReg_32Bit reserved_26:2; /**< \brief [27:26] \internal Reserved */
Ifx_UReg_32Bit TSE:1; /**< \brief [28:28] Target Stream Enable - TSE (rh) */
Ifx_UReg_32Bit TEI:1; /**< \brief [29:29] Transmit Enable Input - TEI (rh) */
Ifx_UReg_32Bit TEO:1; /**< \brief [30:30] Transmit Enable Output - TEO (rh) */
Ifx_UReg_32Bit INI:1; /**< \brief [31:31] Initialize Mode - INI (rh) */
} Ifx_HSSL_MFLAGS_Bits;
/** \brief Miscellaneous Flags Clear Register */
typedef struct _Ifx_HSSL_MFLAGSCL_Bits
{
Ifx_UReg_32Bit NACKC:4; /**< \brief [3:0] NACK Flags Clear - NACKC (w) */
Ifx_UReg_32Bit TTEC:4; /**< \brief [7:4] Transaction Tag Error Flags Clear - TTEC (w) */
Ifx_UReg_32Bit TIMEOUTC:4; /**< \brief [11:8] Timeout Error Flags Clear - TIMEOUTC (w) */
Ifx_UReg_32Bit UNEXPECTEDC:4; /**< \brief [15:12] Unexpected Error Flags Clear - UNEXPECTEDC (w) */
Ifx_UReg_32Bit reserved_16:2; /**< \brief [17:16] \internal Reserved */
Ifx_UReg_32Bit TMBC:1; /**< \brief [18:18] Target Memory Block Flag Clear - TMBC (w) */
Ifx_UReg_32Bit IMBC:1; /**< \brief [19:19] Initiator Memory Block Flag Clear - IMBC (w) */
Ifx_UReg_32Bit ISBC:1; /**< \brief [20:20] Initiator Stream Block Request Clear - ISBC (w) */
Ifx_UReg_32Bit MAVC:1; /**< \brief [21:21] MAV Flag Clear - MAVC (w) */
Ifx_UReg_32Bit SRIEC:1; /**< \brief [22:22] SRI/SPB Bus Access Error Flag Clear - SRIEC (w) */
Ifx_UReg_32Bit PIE1C:1; /**< \brief [23:23] PIE1 Error Flag Clear - PIE1C (w) */
Ifx_UReg_32Bit PIE2C:1; /**< \brief [24:24] PIE2 Error Flag Clear - PIE2C (w) */
Ifx_UReg_32Bit CRCEC:1; /**< \brief [25:25] CRC Error Flag Clear - CRCEC (w) */
Ifx_UReg_32Bit reserved_26:2; /**< \brief [27:26] \internal Reserved */
Ifx_UReg_32Bit TSEC:1; /**< \brief [28:28] Target Stream Enable Flag Clear - TSEC (w) */
Ifx_UReg_32Bit reserved_29:1; /**< \brief [29:29] \internal Reserved */
Ifx_UReg_32Bit TEOC:1; /**< \brief [30:30] Transmit Enable Flag Clear - TEOC (w) */
Ifx_UReg_32Bit INIC:1; /**< \brief [31:31] Initialize Mode Flag Clear - INIC (w) */
} Ifx_HSSL_MFLAGSCL_Bits;
/** \brief Flags Enable Register */
typedef struct _Ifx_HSSL_MFLAGSEN_Bits
{
Ifx_UReg_32Bit NACKEN:4; /**< \brief [3:0] Not Acknowledge Error Enable Bits - NACKEN (rw) */
Ifx_UReg_32Bit TTEEN:4; /**< \brief [7:4] Transaction Tag Error Enable Bits - TTEEN (rw) */
Ifx_UReg_32Bit TIMEOUTEN:4; /**< \brief [11:8] Timeout Error Enable Bits - TIMEOUTEN (rw) */
Ifx_UReg_32Bit UNEXPECTEDEN:4; /**< \brief [15:12] Unexpected Error Enable Bits - UNEXPECTEDEN (rw) */
Ifx_UReg_32Bit reserved_16:5; /**< \brief [20:16] \internal Reserved */
Ifx_UReg_32Bit MAVEN:1; /**< \brief [21:21] MAV Enable Bit - MAVEN (rw) */
Ifx_UReg_32Bit SRIEEN:1; /**< \brief [22:22] SRI/SPB Bus Access Error Enable Bit - SRIEEN (rw) */
Ifx_UReg_32Bit PIE1EN:1; /**< \brief [23:23] PIE1 Error Enable Bit - PIE1EN (rw) */
Ifx_UReg_32Bit PIE2EN:1; /**< \brief [24:24] PIE2 Error Enable Bit - PIE2EN (rw) */
Ifx_UReg_32Bit CRCEEN:1; /**< \brief [25:25] CRC Error Enable Bit - CRCEEN (rw) */
Ifx_UReg_32Bit reserved_26:3; /**< \brief [28:26] \internal Reserved */
Ifx_UReg_32Bit TEIEN:1; /**< \brief [29:29] TEI Enable Bit - TEIEN (rw) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_HSSL_MFLAGSEN_Bits;
/** \brief Miscellaneous Flags Set Register */
typedef struct _Ifx_HSSL_MFLAGSSET_Bits
{
Ifx_UReg_32Bit NACKS:4; /**< \brief [3:0] NACK Flags Set - NACKS (w) */
Ifx_UReg_32Bit TTES:4; /**< \brief [7:4] Transaction Tag Error Flags Set - TTES (w) */
Ifx_UReg_32Bit TIMEOUTS:4; /**< \brief [11:8] Timeout Error Flags Set - TIMEOUTS (w) */
Ifx_UReg_32Bit UNEXPECTEDS:4; /**< \brief [15:12] Unexpected Error Flags Set - UNEXPECTEDS (w) */
Ifx_UReg_32Bit reserved_16:2; /**< \brief [17:16] \internal Reserved */
Ifx_UReg_32Bit TMBS:1; /**< \brief [18:18] Target Memory Block Flag Set - TMBS (w) */
Ifx_UReg_32Bit IMBS:1; /**< \brief [19:19] Initiator Memory Block Flag Set - IMBS (w) */
Ifx_UReg_32Bit ISBS:1; /**< \brief [20:20] Initiator Stream Block Request Set - ISBS (w) */
Ifx_UReg_32Bit MAVS:1; /**< \brief [21:21] MAV Flag Set - MAVS (w) */
Ifx_UReg_32Bit SRIES:1; /**< \brief [22:22] SRI/SPB Bus Access Error Flag Set - SRIES (w) */
Ifx_UReg_32Bit PIE1S:1; /**< \brief [23:23] PIE1 Error Flag Set - PIE1S (w) */
Ifx_UReg_32Bit PIE2S:1; /**< \brief [24:24] PIE2 Error Flag Set - PIE2S (w) */
Ifx_UReg_32Bit CRCES:1; /**< \brief [25:25] CRC Error Flag Set - CRCES (w) */
Ifx_UReg_32Bit reserved_26:2; /**< \brief [27:26] \internal Reserved */
Ifx_UReg_32Bit TSES:1; /**< \brief [28:28] Target Stream Enable Flag Set - TSES (w) */
Ifx_UReg_32Bit reserved_29:1; /**< \brief [29:29] \internal Reserved */
Ifx_UReg_32Bit TEOS:1; /**< \brief [30:30] Transmit Enable Flag Set - TEOS (w) */
Ifx_UReg_32Bit INIS:1; /**< \brief [31:31] Initialize Mode Flag Set - INIS (w) */
} Ifx_HSSL_MFLAGSSET_Bits;
/** \brief Multi Slave Control Register */
typedef struct _Ifx_HSSL_MSCR_Bits
{
Ifx_UReg_32Bit EN:1; /**< \brief [0:0] Multi Slave Mode Enable - EN (rw) */
Ifx_UReg_32Bit SLAVETAG:2; /**< \brief [2:1] Slave Tag - SLAVETAG (rw) */
Ifx_UReg_32Bit reserved_3:13; /**< \brief [15:3] \internal Reserved */
Ifx_UReg_32Bit ITXSTOP:1; /**< \brief [16:16] Initiator Transmission Stop - ITXSTOP (rw) */
Ifx_UReg_32Bit reserved_17:15; /**< \brief [31:17] \internal Reserved */
} Ifx_HSSL_MSCR_Bits;
/** \brief OCDS Control and Status */
typedef struct _Ifx_HSSL_OCS_Bits
{
Ifx_UReg_32Bit TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 - TGS (rw) */
Ifx_UReg_32Bit TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select - TGB (rw) */
Ifx_UReg_32Bit TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection - TG_P (w) */
Ifx_UReg_32Bit reserved_4:20; /**< \brief [23:4] \internal Reserved */
Ifx_UReg_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control - SUS (rw) */
Ifx_UReg_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection - SUS_P (w) */
Ifx_UReg_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State - SUSSTA (rh) */
Ifx_UReg_32Bit reserved_30:2; /**< \brief [31:30] \internal Reserved */
} Ifx_HSSL_OCS_Bits;
/** \brief Request Flags Register */
typedef struct _Ifx_HSSL_QFLAGS_Bits
{
Ifx_UReg_32Bit I:4; /**< \brief [3:0] Request Flags for Initiated Commands - I (rh) */
Ifx_UReg_32Bit T:4; /**< \brief [7:4] Request Flags for Commands Arrived at Target - T (rh) */
Ifx_UReg_32Bit R:4; /**< \brief [11:8] Request Flags for Response Frames at the Target - R (rh) */
Ifx_UReg_32Bit reserved_12:4; /**< \brief [15:12] \internal Reserved */
Ifx_UReg_32Bit E0:2; /**< \brief [17:16] Expect Flags for Activated Timeout Timer 0 - E0 (rh) */
Ifx_UReg_32Bit E1:2; /**< \brief [19:18] Expect Flags for Activated Timeout Timer 1 - E1 (rh) */
Ifx_UReg_32Bit E2:2; /**< \brief [21:20] Expect Flags for Activated Timeout Timer 2 - E2 (rh) */
Ifx_UReg_32Bit E3:2; /**< \brief [23:22] Expect Flags for Activated Timeout Timer 3 - E3 (rh) */
Ifx_UReg_32Bit reserved_24:4; /**< \brief [27:24] \internal Reserved */
Ifx_UReg_32Bit IS:1; /**< \brief [28:28] I Flag for Stream Frames - IS (rh) */
Ifx_UReg_32Bit RS:1; /**< \brief [29:29] R Flag for Stream Frames - RS (rh) */
Ifx_UReg_32Bit TS:1; /**< \brief [30:30] T Flag for Stream Frames - TS (rh) */
Ifx_UReg_32Bit ES:1; /**< \brief [31:31] E Flag for Stream Frames - ES (rh) */
} Ifx_HSSL_QFLAGS_Bits;
/** \brief Security Control Register */
typedef struct _Ifx_HSSL_SEC_Bits
{
Ifx_UReg_32Bit LCK:1; /**< \brief [0:0] Lock the HSSL Module - LCK (rw) */
Ifx_UReg_32Bit LAW:1; /**< \brief [1:1] Lock the Address Windows Registers - LAW (rw) */
Ifx_UReg_32Bit reserved_2:30; /**< \brief [31:2] \internal Reserved */
} Ifx_HSSL_SEC_Bits;
/** \brief Stream FIFOs Status Flags Register */
typedef struct _Ifx_HSSL_SFSFLAGS_Bits
{
Ifx_UReg_32Bit RXFL:2; /**< \brief [1:0] Stream RxFIFO Filling Level - RXFL (rh) */
Ifx_UReg_32Bit TXFL:2; /**< \brief [3:2] Stream TxFIFO Filling Level - TXFL (rh) */
Ifx_UReg_32Bit EXFL:2; /**< \brief [5:4] Stream Expect FIFO Filling Level - EXFL (rh) */
Ifx_UReg_32Bit reserved_6:9; /**< \brief [14:6] \internal Reserved */
Ifx_UReg_32Bit ISF:1; /**< \brief [15:15] Initiator Stream Frame Request - ISF (rh) */
Ifx_UReg_32Bit reserved_16:16; /**< \brief [31:16] \internal Reserved */
} Ifx_HSSL_SFSFLAGS_Bits;
/** \brief Target ID Address Register */
typedef struct _Ifx_HSSL_TIDADD_Bits
{
Ifx_UReg_32Bit A:32; /**< \brief [31:0] Address Pointer - A (rw) */
} Ifx_HSSL_TIDADD_Bits;
/** \brief Target Status Register */
typedef struct _Ifx_HSSL_TSTAT_Bits
{
Ifx_UReg_32Bit LASTCC0:5; /**< \brief [4:0] Last Command Code - LASTCC0 (rh) */
Ifx_UReg_32Bit LASTTT0:3; /**< \brief [7:5] Last Transaction Tag - LASTTT0 (rh) */
Ifx_UReg_32Bit LASTCC1:5; /**< \brief [12:8] Last Command Code - LASTCC1 (rh) */
Ifx_UReg_32Bit LASTTT1:3; /**< \brief [15:13] Last Transaction Tag - LASTTT1 (rh) */
Ifx_UReg_32Bit LASTCC2:5; /**< \brief [20:16] Last Command Code - LASTCC2 (rh) */
Ifx_UReg_32Bit LASTTT2:3; /**< \brief [23:21] Last Transaction Tag - LASTTT2 (rh) */
Ifx_UReg_32Bit LASTCC3:5; /**< \brief [28:24] Last Command Code - LASTCC3 (rh) */
Ifx_UReg_32Bit LASTTT3:3; /**< \brief [31:29] Last Transaction Tag - LASTTT3 (rh) */
} Ifx_HSSL_TSTAT_Bits;
/** \brief Target Stream Current Address Register */
typedef struct _Ifx_HSSL_TS_CA_Bits
{
Ifx_UReg_32Bit reserved_0:5; /**< \brief [4:0] \internal Reserved */
Ifx_UReg_32Bit CURR:27; /**< \brief [31:5] Address of the Memory Location for the Current Transfer - CURR (rh) */
} Ifx_HSSL_TS_CA_Bits;
/** \brief Target Stream Frame Count Register */
typedef struct _Ifx_HSSL_TS_FC_Bits
{
Ifx_UReg_32Bit RELCOUNT:16; /**< \brief [15:0] Reload Count Number - RELCOUNT (rw) */
Ifx_UReg_32Bit CURCOUNT:16; /**< \brief [31:16] Current Count Number - CURCOUNT (rh) */
} Ifx_HSSL_TS_FC_Bits;
/** \brief Target Stream Start Address Register ${x} */
typedef struct _Ifx_HSSL_TS_SA_Bits
{
Ifx_UReg_32Bit reserved_0:5; /**< \brief [4:0] \internal Reserved */
Ifx_UReg_32Bit ADDR:27; /**< \brief [31:5] Start Address for the Memory Range - ADDR (rw) */
} Ifx_HSSL_TS_SA_Bits;
/** \brief Target Current Address Register ${i} */
typedef struct _Ifx_HSSL_T_TCA_Bits
{
Ifx_UReg_32Bit A:32; /**< \brief [31:0] Address Part of the Payload of a Write Command Frame or a Read Command Frame or ID Frame - A (rh) */
} Ifx_HSSL_T_TCA_Bits;
/** \brief Target Current Data Register ${i} */
typedef struct _Ifx_HSSL_T_TCD_Bits
{
Ifx_UReg_32Bit D:32; /**< \brief [31:0] Data Part of the Payload of a Write Command Frame or Read Data of a Read Command Frame - D (rh) */
} Ifx_HSSL_T_TCD_Bits;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_hssl_Registers_union
* \{ */
/** \brief Access Enable Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_ACCEN0_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_ACCEN0;
/** \brief Access Enable Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_ACCEN1_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_ACCEN1;
/** \brief Access Rules Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_AR_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_AR;
/** \brief Access Window End Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_AW_AWEND_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_AW_AWEND;
/** \brief Access Window Start Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_AW_AWSTART_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_AW_AWSTART;
/** \brief Configuration Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_CFG_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_CFG;
/** \brief Clock Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_CLC_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_CLC;
/** \brief CRC Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_CRC_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_CRC;
/** \brief Module Identification Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_ID_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_ID;
/** \brief Initiator Stream Current Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_IS_CA_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_IS_CA;
/** \brief Initiator Stream Frame Count Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_IS_FC_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_IS_FC;
/** \brief Initiator Stream Start Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_IS_SA_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_IS_SA;
/** \brief Initiator Control Data Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_I_ICON_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_I_ICON;
/** \brief Initiator Read Data Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_I_IRD_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_I_IRD;
/** \brief Initiator Read Write Address Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_I_IRWA_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_I_IRWA;
/** \brief Initiator Write Data Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_I_IWD_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_I_IWD;
/** \brief Kernel Reset Register 0 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_KRST0_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_KRST0;
/** \brief Kernel Reset Register 1 */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_KRST1_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_KRST1;
/** \brief Kernel Reset Status Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_KRSTCLR_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_KRSTCLR;
/** \brief Miscellaneous Flags Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_MFLAGS_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_MFLAGS;
/** \brief Miscellaneous Flags Clear Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_MFLAGSCL_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_MFLAGSCL;
/** \brief Flags Enable Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_MFLAGSEN_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_MFLAGSEN;
/** \brief Miscellaneous Flags Set Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_MFLAGSSET_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_MFLAGSSET;
/** \brief Multi Slave Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_MSCR_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_MSCR;
/** \brief OCDS Control and Status */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_OCS_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_OCS;
/** \brief Request Flags Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_QFLAGS_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_QFLAGS;
/** \brief Security Control Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_SEC_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_SEC;
/** \brief Stream FIFOs Status Flags Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_SFSFLAGS_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_SFSFLAGS;
/** \brief Target ID Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_TIDADD_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_TIDADD;
/** \brief Target Status Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_TSTAT_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_TSTAT;
/** \brief Target Stream Current Address Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_TS_CA_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_TS_CA;
/** \brief Target Stream Frame Count Register */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_TS_FC_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_TS_FC;
/** \brief Target Stream Start Address Register ${x} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_TS_SA_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_TS_SA;
/** \brief Target Current Address Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_T_TCA_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_T_TCA;
/** \brief Target Current Data Register ${i} */
typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_HSSL_T_TCD_Bits B; /**< \brief Bitfield access */
} Ifx_HSSL_T_TCD;
/** \} */
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_I_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief I object */
typedef volatile struct _Ifx_HSSL_I
{
Ifx_HSSL_I_IWD IWD; /**< \brief 0, Initiator Write Data Register ${x}*/
Ifx_HSSL_I_ICON ICON; /**< \brief 4, Initiator Control Data Register ${x}*/
Ifx_HSSL_I_IRWA IRWA; /**< \brief 8, Initiator Read Write Address Register ${x}*/
Ifx_HSSL_I_IRD IRD; /**< \brief C, Initiator Read Data Register ${x}*/
} Ifx_HSSL_I;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_T_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief T object */
typedef volatile struct _Ifx_HSSL_T
{
Ifx_HSSL_T_TCD TCD; /**< \brief 0, Target Current Data Register ${i}*/
Ifx_HSSL_T_TCA TCA; /**< \brief 4, Target Current Address Register ${i}*/
} Ifx_HSSL_T;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_IS_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief IS object */
typedef volatile struct _Ifx_HSSL_IS
{
Ifx_HSSL_IS_SA SA[2]; /**< \brief 0, Initiator Stream Start Address Register*/
Ifx_HSSL_IS_CA CA; /**< \brief 8, Initiator Stream Current Address Register*/
Ifx_HSSL_IS_FC FC; /**< \brief C, Initiator Stream Frame Count Register*/
} Ifx_HSSL_IS;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_TS_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief TS object */
typedef volatile struct _Ifx_HSSL_TS
{
Ifx_HSSL_TS_SA SA[2]; /**< \brief 0, Target Stream Start Address Register ${x}*/
Ifx_HSSL_TS_CA CA; /**< \brief 8, Target Stream Current Address Register*/
Ifx_HSSL_TS_FC FC; /**< \brief C, Target Stream Frame Count Register*/
} Ifx_HSSL_TS;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_AW_struct
* \{ */
/******************************************************************************/
/** \name Object L1
* \{ */
/** \brief AW object */
typedef volatile struct _Ifx_HSSL_AW
{
Ifx_HSSL_AW_AWSTART AWSTART; /**< \brief 0, Access Window Start Register ${i}*/
Ifx_HSSL_AW_AWEND AWEND; /**< \brief 4, Access Window End Register ${i}*/
} Ifx_HSSL_AW;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxSfr_Hssl_Registers_struct
* \{ */
/******************************************************************************/
/** \name Object L0
* \{ */
/** \brief HSSL object */
typedef volatile struct _Ifx_HSSL
{
Ifx_HSSL_CLC CLC; /**< \brief 0, Clock Control Register*/
Ifx_UReg_8Bit reserved_4[4]; /**< \brief 4, \internal Reserved */
Ifx_HSSL_ID ID; /**< \brief 8, Module Identification Register*/
Ifx_HSSL_CRC CRC; /**< \brief C, CRC Control Register*/
Ifx_HSSL_CFG CFG; /**< \brief 10, Configuration Register*/
Ifx_HSSL_QFLAGS QFLAGS; /**< \brief 14, Request Flags Register*/
Ifx_HSSL_MFLAGS MFLAGS; /**< \brief 18, Miscellaneous Flags Register*/
Ifx_HSSL_MFLAGSSET MFLAGSSET; /**< \brief 1C, Miscellaneous Flags Set Register*/
Ifx_HSSL_MFLAGSCL MFLAGSCL; /**< \brief 20, Miscellaneous Flags Clear Register*/
Ifx_HSSL_MFLAGSEN MFLAGSEN; /**< \brief 24, Flags Enable Register*/
Ifx_HSSL_SFSFLAGS SFSFLAGS; /**< \brief 28, Stream FIFOs Status Flags Register*/
Ifx_UReg_8Bit reserved_2C[4]; /**< \brief 2C, \internal Reserved */
Ifx_HSSL_I I[4]; /**< \brief 30, Initiator Read Data Register ${x}*/
Ifx_HSSL_T T[4]; /**< \brief 70, Target Current Address Register ${i}*/
Ifx_HSSL_TSTAT TSTAT; /**< \brief 90, Target Status Register*/
Ifx_HSSL_TIDADD TIDADD; /**< \brief 94, Target ID Address Register*/
Ifx_HSSL_SEC SEC; /**< \brief 98, Security Control Register*/
Ifx_HSSL_MSCR MSCR; /**< \brief 9C, Multi Slave Control Register*/
Ifx_HSSL_IS IS; /**< \brief A0, Initiator Stream Frame Count Register*/
Ifx_HSSL_TS TS; /**< \brief B0, Target Stream Frame Count Register*/
Ifx_HSSL_AW AW[4]; /**< \brief C0, Access Window End Register ${i}*/
Ifx_HSSL_AR AR; /**< \brief E0, Access Rules Register*/
Ifx_UReg_8Bit reserved_E4[4]; /**< \brief E4, \internal Reserved */
Ifx_HSSL_OCS OCS; /**< \brief E8, OCDS Control and Status*/
Ifx_HSSL_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register*/
Ifx_HSSL_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1*/
Ifx_HSSL_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0*/
Ifx_HSSL_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1*/
Ifx_HSSL_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0*/
Ifx_UReg_8Bit reserved_100[767]; /**< \brief 100, \internal Reserved */
} Ifx_HSSL;
/** \} */
/******************************************************************************/
/** \} */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXHSSL_REGDEF_H */

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Target/Demo/TRICORE_TC3_TC375_Lite_Kit_ADS/Boot/Libraries/Infra/Sfr/TC37A/_Reg/IfxI2c_bf.h Normal file
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