- Added support for firmware updates from a FATFS mounted file system

- Supported firmware updates from SD-card for EK-LM3S6965 demo
- Added CpuUserProgramStartHook() hook function
- Improved timer module so it can be used by all other modules, not just the backdoor


git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@42 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2013-05-22 13:37:47 +00:00
parent 4c72a2b0f9
commit f6830b5864
473 changed files with 242635 additions and 30970 deletions

View File

@ -1,5 +1,5 @@
[sci]
port=3
port=6
baudrate=8
[xcp]
seedkey=

View File

@ -50,6 +50,8 @@ Discarded input sections
.text 0x00000000 0x0 ARM Flash Debug/../../obj/com.o
.data 0x00000000 0x0 ARM Flash Debug/../../obj/com.o
.bss 0x00000000 0x0 ARM Flash Debug/../../obj/com.o
.text.ComSetDisconnectEntryState
0x00000000 0x14 ARM Flash Debug/../../obj/com.o
.text.ComIsConnectEntryState
0x00000000 0x10 ARM Flash Debug/../../obj/com.o
.text 0x00000000 0x0 ARM Flash Debug/../../obj/cop.o
@ -180,7 +182,7 @@ Linker script and memory map
0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .init is too large to fit in FLASH memory segment)
0x00000370 __text_load_start__ = ALIGN (__init_end__, 0x4)
.text 0x00000370 0x110c
.text 0x00000370 0x1130
0x00000370 __text_start__ = .
*(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
.glue_7 0x00000000 0x0 linker stubs
@ -206,115 +208,114 @@ Linker script and memory map
.text.FlashErase
0x00000788 0x130 ARM Flash Debug/../../obj/flash.o
0x00000788 FlashErase
.text.FlashVerifyChecksum
0x000008b8 0x48 ARM Flash Debug/../../obj/flash.o
0x000008b8 FlashVerifyChecksum
.text.FlashWriteChecksum
0x00000900 0x74 ARM Flash Debug/../../obj/flash.o
0x00000900 FlashWriteChecksum
0x000008b8 0x80 ARM Flash Debug/../../obj/flash.o
0x000008b8 FlashWriteChecksum
.text.FlashVerifyChecksum
0x00000938 0x48 ARM Flash Debug/../../obj/flash.o
0x00000938 FlashVerifyChecksum
.text.FlashDone
0x00000974 0x5c ARM Flash Debug/../../obj/flash.o
0x00000974 FlashDone
0x00000980 0x5c ARM Flash Debug/../../obj/flash.o
0x00000980 FlashDone
.text.CpuMemCopy
0x000009d0 0x44 ARM Flash Debug/../../obj/cpu.o
0x000009d0 CpuMemCopy
0x000009dc 0x44 ARM Flash Debug/../../obj/cpu.o
0x000009dc CpuMemCopy
.text.CpuStartUserProgram
0x00000a14 0x44 ARM Flash Debug/../../obj/cpu.o
0x00000a14 CpuStartUserProgram
0x00000a20 0x4c ARM Flash Debug/../../obj/cpu.o
0x00000a20 CpuStartUserProgram
.text.CpuReset
0x00000a58 0x10 ARM Flash Debug/../../obj/cpu.o
0x00000a58 CpuReset
.text.NvmInit 0x00000a68 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000a68 NvmInit
0x00000a6c 0x10 ARM Flash Debug/../../obj/cpu.o
0x00000a6c CpuReset
.text.NvmInit 0x00000a7c 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000a7c NvmInit
.text.NvmWrite
0x00000a78 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000a78 NvmWrite
0x00000a8c 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000a8c NvmWrite
.text.NvmErase
0x00000a88 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000a88 NvmErase
0x00000a9c 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000a9c NvmErase
.text.NvmVerifyChecksum
0x00000a98 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000a98 NvmVerifyChecksum
.text.NvmDone 0x00000aa8 0x1c ARM Flash Debug/../../obj/nvm.o
0x00000aa8 NvmDone
.text.TimerReset
0x00000ac4 0x20 ARM Flash Debug/../../obj/timer.o
0x00000ac4 TimerReset
.text.TimerUpdate
0x00000ae4 0x38 ARM Flash Debug/../../obj/timer.o
0x00000ae4 TimerUpdate
.text.TimerSet
0x00000b1c 0x10 ARM Flash Debug/../../obj/timer.o
0x00000b1c TimerSet
0x00000aac 0x10 ARM Flash Debug/../../obj/nvm.o
0x00000aac NvmVerifyChecksum
.text.NvmDone 0x00000abc 0x1c ARM Flash Debug/../../obj/nvm.o
0x00000abc NvmDone
.text.TimerInit
0x00000b2c 0x48 ARM Flash Debug/../../obj/timer.o
0x00000b2c TimerInit
0x00000ad8 0x48 ARM Flash Debug/../../obj/timer.o
0x00000ad8 TimerInit
.text.TimerReset
0x00000b20 0x20 ARM Flash Debug/../../obj/timer.o
0x00000b20 TimerReset
.text.TimerUpdate
0x00000b40 0x38 ARM Flash Debug/../../obj/timer.o
0x00000b40 TimerUpdate
.text.TimerGet
0x00000b74 0x1c ARM Flash Debug/../../obj/timer.o
0x00000b74 TimerGet
0x00000b78 0x1c ARM Flash Debug/../../obj/timer.o
0x00000b78 TimerGet
.text.UartReceiveByte
0x00000b90 0x28 ARM Flash Debug/../../obj/uart.o
0x00000b94 0x28 ARM Flash Debug/../../obj/uart.o
.text.UartTransmitByte
0x00000bb8 0x54 ARM Flash Debug/../../obj/uart.o
0x00000bbc 0x54 ARM Flash Debug/../../obj/uart.o
.text.UartInit
0x00000c0c 0x40 ARM Flash Debug/../../obj/uart.o
0x00000c0c UartInit
0x00000c10 0x40 ARM Flash Debug/../../obj/uart.o
0x00000c10 UartInit
.text.UartTransmitPacket
0x00000c4c 0x84 ARM Flash Debug/../../obj/uart.o
0x00000c4c UartTransmitPacket
0x00000c50 0x84 ARM Flash Debug/../../obj/uart.o
0x00000c50 UartTransmitPacket
.text.UartReceivePacket
0x00000cd0 0xc0 ARM Flash Debug/../../obj/uart.o
0x00000cd0 UartReceivePacket
0x00000cd4 0xc0 ARM Flash Debug/../../obj/uart.o
0x00000cd4 UartReceivePacket
.text.AssertFailure
0x00000d90 0x24 ARM Flash Debug/../../obj/assert.o
0x00000d90 AssertFailure
0x00000d94 0x24 ARM Flash Debug/../../obj/assert.o
0x00000d94 AssertFailure
.text.BackDoorCheck
0x00000db4 0x4c ARM Flash Debug/../../obj/backdoor.o
0x00000db4 BackDoorCheck
0x00000db8 0x54 ARM Flash Debug/../../obj/backdoor.o
0x00000db8 BackDoorCheck
.text.BackDoorInit
0x00000e00 0x24 ARM Flash Debug/../../obj/backdoor.o
0x00000e00 BackDoorInit
0x00000e0c 0x30 ARM Flash Debug/../../obj/backdoor.o
0x00000e0c BackDoorInit
.text.BootInit
0x00000e24 0x1c ARM Flash Debug/../../obj/boot.o
0x00000e24 BootInit
0x00000e3c 0x20 ARM Flash Debug/../../obj/boot.o
0x00000e3c BootInit
.text.BootTask
0x00000e40 0x18 ARM Flash Debug/../../obj/boot.o
0x00000e40 BootTask
.text.ComInit 0x00000e58 0x44 ARM Flash Debug/../../obj/com.o
0x00000e58 ComInit
.text.ComTask 0x00000e9c 0x24 ARM Flash Debug/../../obj/com.o
0x00000e9c ComTask
0x00000e5c 0x1c ARM Flash Debug/../../obj/boot.o
0x00000e5c BootTask
.text.ComInit 0x00000e78 0x44 ARM Flash Debug/../../obj/com.o
0x00000e78 ComInit
.text.ComTask 0x00000ebc 0x24 ARM Flash Debug/../../obj/com.o
0x00000ebc ComTask
.text.ComFree 0x00000ee0 0x4 ARM Flash Debug/../../obj/com.o
0x00000ee0 ComFree
.text.ComTransmitPacket
0x00000ec0 0x18 ARM Flash Debug/../../obj/com.o
0x00000ec0 ComTransmitPacket
0x00000ee4 0x18 ARM Flash Debug/../../obj/com.o
0x00000ee4 ComTransmitPacket
.text.ComSetConnectEntryState
0x00000ed8 0x14 ARM Flash Debug/../../obj/com.o
0x00000ed8 ComSetConnectEntryState
0x00000efc 0x14 ARM Flash Debug/../../obj/com.o
0x00000efc ComSetConnectEntryState
.text.ComIsConnected
0x00000eec 0x10 ARM Flash Debug/../../obj/com.o
0x00000eec ComIsConnected
.text.CopInit 0x00000efc 0x4 ARM Flash Debug/../../obj/cop.o
0x00000efc CopInit
0x00000f10 0x10 ARM Flash Debug/../../obj/com.o
0x00000f10 ComIsConnected
.text.CopInit 0x00000f20 0x4 ARM Flash Debug/../../obj/cop.o
0x00000f20 CopInit
.text.CopService
0x00000f00 0x4 ARM Flash Debug/../../obj/cop.o
0x00000f00 CopService
0x00000f24 0x4 ARM Flash Debug/../../obj/cop.o
0x00000f24 CopService
.text.XcpProtectResources
0x00000f04 0x14 ARM Flash Debug/../../obj/xcp.o
0x00000f28 0x14 ARM Flash Debug/../../obj/xcp.o
.text.XcpSetCtoError
0x00000f18 0x20 ARM Flash Debug/../../obj/xcp.o
.text.XcpInit 0x00000f38 0x28 ARM Flash Debug/../../obj/xcp.o
0x00000f38 XcpInit
0x00000f3c 0x20 ARM Flash Debug/../../obj/xcp.o
.text.XcpInit 0x00000f5c 0x28 ARM Flash Debug/../../obj/xcp.o
0x00000f5c XcpInit
.text.XcpIsConnected
0x00000f60 0x18 ARM Flash Debug/../../obj/xcp.o
0x00000f60 XcpIsConnected
0x00000f84 0x18 ARM Flash Debug/../../obj/xcp.o
0x00000f84 XcpIsConnected
.text.XcpPacketTransmitted
0x00000f78 0x14 ARM Flash Debug/../../obj/xcp.o
0x00000f78 XcpPacketTransmitted
0x00000f9c 0x14 ARM Flash Debug/../../obj/xcp.o
0x00000f9c XcpPacketTransmitted
.text.XcpPacketReceived
0x00000f8c 0x4f0 ARM Flash Debug/../../obj/xcp.o
0x00000f8c XcpPacketReceived
0x0000147c __text_end__ = (__text_start__ + SIZEOF (.text))
0x0000147c __text_load_end__ = __text_end__
0x00000fb0 0x4f0 ARM Flash Debug/../../obj/xcp.o
0x00000fb0 XcpPacketReceived
0x000014a0 __text_end__ = (__text_start__ + SIZEOF (.text))
0x000014a0 __text_load_end__ = __text_end__
.vfp11_veneer 0x00000000 0x0
.vfp11_veneer 0x00000000 0x0 linker stubs
@ -322,45 +323,45 @@ Linker script and memory map
.v4_bx 0x00000000 0x0
.v4_bx 0x00000000 0x0 linker stubs
0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .text is too large to fit in FLASH memory segment)
0x0000147c __dtors_load_start__ = ALIGN (__text_end__, 0x4)
0x000014a0 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
.dtors 0x0000147c 0x0
0x0000147c __dtors_start__ = .
.dtors 0x000014a0 0x0
0x000014a0 __dtors_start__ = .
*(SORT(.dtors.*))
*(.dtors)
0x0000147c __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
0x0000147c __dtors_load_end__ = __dtors_end__
0x000014a0 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
0x000014a0 __dtors_load_end__ = __dtors_end__
0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .dtors is too large to fit in FLASH memory segment)
0x0000147c __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
0x000014a0 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
.ctors 0x0000147c 0x0
0x0000147c __ctors_start__ = .
.ctors 0x000014a0 0x0
0x000014a0 __ctors_start__ = .
*(SORT(.ctors.*))
*(.ctors)
0x0000147c __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
0x0000147c __ctors_load_end__ = __ctors_end__
0x000014a0 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
0x000014a0 __ctors_load_end__ = __ctors_end__
0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .ctors is too large to fit in FLASH memory segment)
0x0000147c __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
0x000014a0 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
.rodata 0x0000147c 0x14c
0x0000147c __rodata_start__ = .
.rodata 0x000014a0 0x148
0x000014a0 __rodata_start__ = .
*(.rodata .rodata.* .gnu.linkonce.r.*)
.rodata.flashLayout
0x0000147c 0xc0 ARM Flash Debug/../../obj/flash.o
0x000014a0 0xc0 ARM Flash Debug/../../obj/flash.o
.rodata.str1.4
0x0000153c 0x84 ARM Flash Debug/../../obj/uart.o
0x00001560 0x80 ARM Flash Debug/../../obj/uart.o
.rodata.xcpStationId
0x000015c0 0x8 ARM Flash Debug/../../obj/xcp.o
0x000015c8 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
0x000015c8 __rodata_load_end__ = __rodata_end__
0x000015e0 0x8 ARM Flash Debug/../../obj/xcp.o
0x000015e8 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
0x000015e8 __rodata_load_end__ = __rodata_end__
0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .rodata is too large to fit in FLASH memory segment)
0x000015c8 __data_load_start__ = ALIGN (__rodata_end__, 0x4)
0x000015e8 __data_load_start__ = ALIGN (__rodata_end__, 0x4)
.data 0x4000023c 0x0 load address 0x000015c8
.data 0x4000023c 0x0 load address 0x000015e8
0x4000023c __data_start__ = .
*(.data .data.* .gnu.linkonce.d.*)
0x4000023c __data_end__ = (__data_start__ + SIZEOF (.data))
0x000015c8 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
0x000015e8 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x40000))), error: .data is too large to fit in FLASH memory segment)
.data_run 0x4000023c 0x0
@ -371,7 +372,7 @@ Linker script and memory map
0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .data_run is too large to fit in SRAM memory segment)
0x4000023c __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
.bss 0x4000023c 0x4f4
.bss 0x4000023c 0x4fc
0x4000023c __bss_start__ = .
*(.bss .bss.* .gnu.linkonce.b.*)
.bss.bootBlockInfo
@ -382,12 +383,12 @@ Linker script and memory map
0x40000644 0x4 ARM Flash Debug/../../obj/timer.o
.bss.free_running_counter_last
0x40000648 0x4 ARM Flash Debug/../../obj/timer.o
.bss.xcpCtoRxLength.866
.bss.xcpCtoRxLength.900
0x4000064c 0x1 ARM Flash Debug/../../obj/uart.o
*fill* 0x4000064d 0x3 00
.bss.xcpCtoReqPacket.865
.bss.xcpCtoReqPacket.899
0x40000650 0x44 ARM Flash Debug/../../obj/uart.o
.bss.xcpCtoRxInProgress.867
.bss.xcpCtoRxInProgress.901
0x40000694 0x1 ARM Flash Debug/../../obj/uart.o
*fill* 0x40000695 0x3 00
.bss.assert_failure_file
@ -396,107 +397,110 @@ Linker script and memory map
0x4000069c 0x4 ARM Flash Debug/../../obj/assert.o
.bss.backdoorOpen
0x400006a0 0x1 ARM Flash Debug/../../obj/backdoor.o
*fill* 0x400006a1 0x3 00
.bss.backdoorOpenTime
0x400006a4 0x4 ARM Flash Debug/../../obj/backdoor.o
.bss.comEntryStateConnect
0x400006a1 0x1 ARM Flash Debug/../../obj/com.o
*fill* 0x400006a2 0x2 00
.bss.xcpCtoReqPacket.855
0x400006a4 0x40 ARM Flash Debug/../../obj/com.o
.bss.xcpInfo 0x400006e4 0x4c ARM Flash Debug/../../obj/xcp.o
0x400006a8 0x1 ARM Flash Debug/../../obj/com.o
*fill* 0x400006a9 0x3 00
.bss.xcpCtoReqPacket.889
0x400006ac 0x40 ARM Flash Debug/../../obj/com.o
.bss.xcpInfo 0x400006ec 0x4c ARM Flash Debug/../../obj/xcp.o
*(COMMON)
0x40000730 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
0x40000730 __bss_load_end__ = __bss_end__
0x40000738 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
0x40000738 __bss_load_end__ = __bss_end__
0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .bss is too large to fit in SRAM memory segment)
0x40000730 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
0x40000738 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
.non_init 0x40000730 0x0
0x40000730 __non_init_start__ = .
.non_init 0x40000738 0x0
0x40000738 __non_init_start__ = .
*(.non_init .non_init.*)
0x40000730 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
0x40000730 __non_init_load_end__ = __non_init_end__
0x40000738 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
0x40000738 __non_init_load_end__ = __non_init_end__
0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .non_init is too large to fit in SRAM memory segment)
0x40000730 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
0x40000738 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
.heap 0x40000730 0x400
0x40000730 __heap_start__ = .
.heap 0x40000738 0x400
0x40000738 __heap_start__ = .
*(.heap .heap.*)
0x40000b30 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
*fill* 0x40000730 0x400 00
0x40000b30 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
0x40000b30 __heap_load_end__ = __heap_end__
0x40000b38 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
*fill* 0x40000738 0x400 00
0x40000b38 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
0x40000b38 __heap_load_end__ = __heap_end__
0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .heap is too large to fit in SRAM memory segment)
0x40000b30 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
0x40000b38 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
.stack 0x40000b30 0x400
0x40000b30 __stack_start__ = .
.stack 0x40000b38 0x400
0x40000b38 __stack_start__ = .
*(.stack .stack.*)
0x40000f30 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
*fill* 0x40000b30 0x400 00
0x40000f30 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
0x40000f30 __stack_load_end__ = __stack_end__
0x40000f38 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
*fill* 0x40000b38 0x400 00
0x40000f38 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
0x40000f38 __stack_load_end__ = __stack_end__
0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack is too large to fit in SRAM memory segment)
0x40000f30 __stack_irq_load_start__ = ALIGN (__stack_end__, 0x4)
0x40000f38 __stack_irq_load_start__ = ALIGN (__stack_end__, 0x4)
.stack_irq 0x40000f30 0x100
0x40000f30 __stack_irq_start__ = .
.stack_irq 0x40000f38 0x100
0x40000f38 __stack_irq_start__ = .
*(.stack_irq .stack_irq.*)
0x40001030 . = ALIGN (MAX ((__stack_irq_start__ + __STACKSIZE_IRQ__), .), 0x4)
*fill* 0x40000f30 0x100 00
0x40001030 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq))
0x40001030 __stack_irq_load_end__ = __stack_irq_end__
0x40001038 . = ALIGN (MAX ((__stack_irq_start__ + __STACKSIZE_IRQ__), .), 0x4)
*fill* 0x40000f38 0x100 00
0x40001038 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq))
0x40001038 __stack_irq_load_end__ = __stack_irq_end__
0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_irq is too large to fit in SRAM memory segment)
0x40001030 __stack_fiq_load_start__ = ALIGN (__stack_irq_end__, 0x4)
0x40001038 __stack_fiq_load_start__ = ALIGN (__stack_irq_end__, 0x4)
.stack_fiq 0x40001030 0x100
0x40001030 __stack_fiq_start__ = .
.stack_fiq 0x40001038 0x100
0x40001038 __stack_fiq_start__ = .
*(.stack_fiq .stack_fiq.*)
0x40001130 . = ALIGN (MAX ((__stack_fiq_start__ + __STACKSIZE_FIQ__), .), 0x4)
*fill* 0x40001030 0x100 00
0x40001130 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq))
0x40001130 __stack_fiq_load_end__ = __stack_fiq_end__
0x40001138 . = ALIGN (MAX ((__stack_fiq_start__ + __STACKSIZE_FIQ__), .), 0x4)
*fill* 0x40001038 0x100 00
0x40001138 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq))
0x40001138 __stack_fiq_load_end__ = __stack_fiq_end__
0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_fiq is too large to fit in SRAM memory segment)
0x40001130 __stack_svc_load_start__ = ALIGN (__stack_fiq_end__, 0x4)
0x40001138 __stack_svc_load_start__ = ALIGN (__stack_fiq_end__, 0x4)
.stack_svc 0x40001130 0x0
0x40001130 __stack_svc_start__ = .
.stack_svc 0x40001138 0x0
0x40001138 __stack_svc_start__ = .
*(.stack_svc .stack_svc.*)
0x40001130 . = ALIGN (MAX ((__stack_svc_start__ + __STACKSIZE_SVC__), .), 0x4)
0x40001130 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc))
0x40001130 __stack_svc_load_end__ = __stack_svc_end__
0x40001138 . = ALIGN (MAX ((__stack_svc_start__ + __STACKSIZE_SVC__), .), 0x4)
0x40001138 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc))
0x40001138 __stack_svc_load_end__ = __stack_svc_end__
0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_svc is too large to fit in SRAM memory segment)
0x40001130 __stack_abt_load_start__ = ALIGN (__stack_svc_end__, 0x4)
0x40001138 __stack_abt_load_start__ = ALIGN (__stack_svc_end__, 0x4)
.stack_abt 0x40001130 0x0
0x40001130 __stack_abt_start__ = .
.stack_abt 0x40001138 0x0
0x40001138 __stack_abt_start__ = .
*(.stack_abt .stack_abt.*)
0x40001130 . = ALIGN (MAX ((__stack_abt_start__ + __STACKSIZE_ABT__), .), 0x4)
0x40001130 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt))
0x40001130 __stack_abt_load_end__ = __stack_abt_end__
0x40001138 . = ALIGN (MAX ((__stack_abt_start__ + __STACKSIZE_ABT__), .), 0x4)
0x40001138 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt))
0x40001138 __stack_abt_load_end__ = __stack_abt_end__
0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_abt is too large to fit in SRAM memory segment)
0x40001130 __stack_und_load_start__ = ALIGN (__stack_abt_end__, 0x4)
0x40001138 __stack_und_load_start__ = ALIGN (__stack_abt_end__, 0x4)
.stack_und 0x40001130 0x0
0x40001130 __stack_und_start__ = .
.stack_und 0x40001138 0x0
0x40001138 __stack_und_start__ = .
*(.stack_und .stack_und.*)
0x40001130 . = ALIGN (MAX ((__stack_und_start__ + __STACKSIZE_UND__), .), 0x4)
0x40001130 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und))
0x40001130 __stack_und_load_end__ = __stack_und_end__
0x40001138 . = ALIGN (MAX ((__stack_und_start__ + __STACKSIZE_UND__), .), 0x4)
0x40001138 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und))
0x40001138 __stack_und_load_end__ = __stack_und_end__
0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_und is too large to fit in SRAM memory segment)
0x000015c8 __fast_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
0x000015e8 __fast_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
.fast 0x40001130 0x0 load address 0x000015c8
0x40001130 __fast_start__ = .
.fast 0x40001138 0x0 load address 0x000015e8
0x40001138 __fast_start__ = .
*(.fast .fast.*)
0x40001130 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
0x000015c8 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
0x000015c8 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.fast))
0x40001138 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
0x000015e8 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
0x000015e8 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.fast))
0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x40000))), error: .fast is too large to fit in FLASH memory segment)
.fast_run 0x40001130 0x0
0x40001130 __fast_run_start__ = .
0x40001130 . = MAX ((__fast_run_start__ + SIZEOF (.fast)), .)
0x40001130 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
0x40001130 __fast_run_load_end__ = __fast_run_end__
0x40001130 __SRAM_segment_used_end__ = (ALIGN (__stack_und_end__, 0x4) + SIZEOF (.fast_run))
.fast_run 0x40001138 0x0
0x40001138 __fast_run_start__ = .
0x40001138 . = MAX ((__fast_run_start__ + SIZEOF (.fast)), .)
0x40001138 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
0x40001138 __fast_run_load_end__ = __fast_run_end__
0x40001138 __SRAM_segment_used_end__ = (ALIGN (__stack_und_end__, 0x4) + SIZEOF (.fast_run))
0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .fast_run is too large to fit in SRAM memory segment)
START GROUP
LOAD ARM Flash Debug/../../obj/hooks.o
@ -516,35 +520,35 @@ LOAD ARM Flash Debug/../../obj/com.o
LOAD ARM Flash Debug/../../obj/cop.o
LOAD ARM Flash Debug/../../obj/xcp.o
LOAD C:/Users/voorburg/AppData/Local/Rowley Associates Limited/CrossWorks for ARM/packages/lib/liblpc2000_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libm_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libcpp_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_targetio_impl_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libarm_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcpp_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_targetio_impl_v4t_a_le.a
LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v4t_a_le.a
END GROUP
OUTPUT(D:/usr/feaser/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/../bin/openbtl_olimex_lpc_l2294_20mhz.elf elf32-littlearm)
OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/../bin/openbtl_olimex_lpc_l2294_20mhz.elf elf32-littlearm)
.debug_info 0x00000000 0x1809
.debug_info 0x00000000 0x181c
.debug_info 0x00000000 0x5a ARM Flash Debug/../../obj/hooks.o
.debug_info 0x0000005a 0x116 ARM Flash Debug/../../obj/main.o
.debug_info 0x00000170 0x5a ARM Flash Debug/../../obj/extflash.o
.debug_info 0x000001ca 0x110 ARM Flash Debug/../../obj/cstart.o
.debug_info 0x000002da 0x539 ARM Flash Debug/../../obj/flash.o
.debug_info 0x00000813 0x5a ARM Flash Debug/../../obj/can.o
.debug_info 0x0000086d 0x13a ARM Flash Debug/../../obj/cpu.o
.debug_info 0x000009a7 0x15e ARM Flash Debug/../../obj/nvm.o
.debug_info 0x00000b05 0x119 ARM Flash Debug/../../obj/timer.o
.debug_info 0x00000c1e 0x1bf ARM Flash Debug/../../obj/uart.o
.debug_info 0x00000ddd 0xe4 ARM Flash Debug/../../obj/assert.o
.debug_info 0x00000ec1 0xa4 ARM Flash Debug/../../obj/backdoor.o
.debug_info 0x00000f65 0x88 ARM Flash Debug/../../obj/boot.o
.debug_info 0x00000fed 0x18b ARM Flash Debug/../../obj/com.o
.debug_info 0x00001178 0x86 ARM Flash Debug/../../obj/cop.o
.debug_info 0x000011fe 0x60b ARM Flash Debug/../../obj/xcp.o
.debug_info 0x000001ca 0x106 ARM Flash Debug/../../obj/cstart.o
.debug_info 0x000002d0 0x538 ARM Flash Debug/../../obj/flash.o
.debug_info 0x00000808 0x5a ARM Flash Debug/../../obj/can.o
.debug_info 0x00000862 0x13a ARM Flash Debug/../../obj/cpu.o
.debug_info 0x0000099c 0x15e ARM Flash Debug/../../obj/nvm.o
.debug_info 0x00000afa 0xf2 ARM Flash Debug/../../obj/timer.o
.debug_info 0x00000bec 0x1bf ARM Flash Debug/../../obj/uart.o
.debug_info 0x00000dab 0xe4 ARM Flash Debug/../../obj/assert.o
.debug_info 0x00000e8f 0xc0 ARM Flash Debug/../../obj/backdoor.o
.debug_info 0x00000f4f 0x88 ARM Flash Debug/../../obj/boot.o
.debug_info 0x00000fd7 0x1b4 ARM Flash Debug/../../obj/com.o
.debug_info 0x0000118b 0x86 ARM Flash Debug/../../obj/cop.o
.debug_info 0x00001211 0x60b ARM Flash Debug/../../obj/xcp.o
.debug_abbrev 0x00000000 0xa6c
.debug_abbrev 0x00000000 0xa48
.debug_abbrev 0x00000000 0x28 ARM Flash Debug/../../obj/hooks.o
.debug_abbrev 0x00000028 0xc5 ARM Flash Debug/../../obj/main.o
.debug_abbrev 0x000000ed 0x28 ARM Flash Debug/../../obj/extflash.o
@ -553,82 +557,82 @@ OUTPUT(D:/usr/feaser/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_
.debug_abbrev 0x00000346 0x28 ARM Flash Debug/../../obj/can.o
.debug_abbrev 0x0000036e 0xaf ARM Flash Debug/../../obj/cpu.o
.debug_abbrev 0x0000041d 0xa3 ARM Flash Debug/../../obj/nvm.o
.debug_abbrev 0x000004c0 0xad ARM Flash Debug/../../obj/timer.o
.debug_abbrev 0x0000056d 0x110 ARM Flash Debug/../../obj/uart.o
.debug_abbrev 0x0000067d 0x7c ARM Flash Debug/../../obj/assert.o
.debug_abbrev 0x000006f9 0x5b ARM Flash Debug/../../obj/backdoor.o
.debug_abbrev 0x00000754 0x3f ARM Flash Debug/../../obj/boot.o
.debug_abbrev 0x00000793 0xe0 ARM Flash Debug/../../obj/com.o
.debug_abbrev 0x00000873 0x3f ARM Flash Debug/../../obj/cop.o
.debug_abbrev 0x000008b2 0x1ba ARM Flash Debug/../../obj/xcp.o
.debug_abbrev 0x000004c0 0x89 ARM Flash Debug/../../obj/timer.o
.debug_abbrev 0x00000549 0x110 ARM Flash Debug/../../obj/uart.o
.debug_abbrev 0x00000659 0x7c ARM Flash Debug/../../obj/assert.o
.debug_abbrev 0x000006d5 0x5b ARM Flash Debug/../../obj/backdoor.o
.debug_abbrev 0x00000730 0x3f ARM Flash Debug/../../obj/boot.o
.debug_abbrev 0x0000076f 0xe0 ARM Flash Debug/../../obj/com.o
.debug_abbrev 0x0000084f 0x3f ARM Flash Debug/../../obj/cop.o
.debug_abbrev 0x0000088e 0x1ba ARM Flash Debug/../../obj/xcp.o
.debug_line 0x00000000 0x1245
.debug_line 0x00000000 0x11ef
.debug_line 0x00000000 0x1d ARM Flash Debug/../../obj/hooks.o
.debug_line 0x0000001d 0x13a ARM Flash Debug/../../obj/main.o
.debug_line 0x00000157 0x1d ARM Flash Debug/../../obj/extflash.o
.debug_line 0x00000174 0x19e ARM Flash Debug/../../obj/cstart.o
.debug_line 0x00000312 0x2db ARM Flash Debug/../../obj/flash.o
.debug_line 0x000005ed 0x1d ARM Flash Debug/../../obj/can.o
.debug_line 0x0000060a 0xf6 ARM Flash Debug/../../obj/cpu.o
.debug_line 0x00000700 0x112 ARM Flash Debug/../../obj/nvm.o
.debug_line 0x00000812 0x113 ARM Flash Debug/../../obj/timer.o
.debug_line 0x00000925 0x15e ARM Flash Debug/../../obj/uart.o
.debug_line 0x00000a83 0x137 ARM Flash Debug/../../obj/assert.o
.debug_line 0x00000bba 0x150 ARM Flash Debug/../../obj/backdoor.o
.debug_line 0x00000d0a 0xbf ARM Flash Debug/../../obj/boot.o
.debug_line 0x00000dc9 0x192 ARM Flash Debug/../../obj/com.o
.debug_line 0x00000f5b 0xb7 ARM Flash Debug/../../obj/cop.o
.debug_line 0x00001012 0x233 ARM Flash Debug/../../obj/xcp.o
.debug_line 0x0000001d 0x12e ARM Flash Debug/../../obj/main.o
.debug_line 0x0000014b 0x1d ARM Flash Debug/../../obj/extflash.o
.debug_line 0x00000168 0x198 ARM Flash Debug/../../obj/cstart.o
.debug_line 0x00000300 0x2d1 ARM Flash Debug/../../obj/flash.o
.debug_line 0x000005d1 0x1d ARM Flash Debug/../../obj/can.o
.debug_line 0x000005ee 0xf4 ARM Flash Debug/../../obj/cpu.o
.debug_line 0x000006e2 0x10c ARM Flash Debug/../../obj/nvm.o
.debug_line 0x000007ee 0xfb ARM Flash Debug/../../obj/timer.o
.debug_line 0x000008e9 0x158 ARM Flash Debug/../../obj/uart.o
.debug_line 0x00000a41 0x12b ARM Flash Debug/../../obj/assert.o
.debug_line 0x00000b6c 0x145 ARM Flash Debug/../../obj/backdoor.o
.debug_line 0x00000cb1 0xbb ARM Flash Debug/../../obj/boot.o
.debug_line 0x00000d6c 0x1ab ARM Flash Debug/../../obj/com.o
.debug_line 0x00000f17 0xb1 ARM Flash Debug/../../obj/cop.o
.debug_line 0x00000fc8 0x227 ARM Flash Debug/../../obj/xcp.o
.debug_str 0x00000000 0xe15
.debug_str 0x00000000 0xb1 ARM Flash Debug/../../obj/hooks.o
0xcf (size before relaxing)
.debug_str 0x000000b1 0xa4 ARM Flash Debug/../../obj/main.o
0x110 (size before relaxing)
.debug_str 0x00000155 0x6b ARM Flash Debug/../../obj/extflash.o
0xd2 (size before relaxing)
.debug_str 0x000001c0 0x24d ARM Flash Debug/../../obj/flash.o
0x2d8 (size before relaxing)
.debug_str 0x0000040d 0x83 ARM Flash Debug/../../obj/can.o
0xea (size before relaxing)
.debug_str 0x00000490 0xc7 ARM Flash Debug/../../obj/cpu.o
0x157 (size before relaxing)
.debug_str 0x00000557 0xb7 ARM Flash Debug/../../obj/nvm.o
0x14f (size before relaxing)
.debug_str 0x0000060e 0x10b ARM Flash Debug/../../obj/timer.o
0x17d (size before relaxing)
.debug_str 0x00000719 0x11f ARM Flash Debug/../../obj/uart.o
0x1b4 (size before relaxing)
.debug_str 0x00000838 0xb8 ARM Flash Debug/../../obj/assert.o
0x134 (size before relaxing)
.debug_str 0x000008f0 0xa3 ARM Flash Debug/../../obj/backdoor.o
0x113 (size before relaxing)
.debug_str 0x00000993 0x89 ARM Flash Debug/../../obj/boot.o
0xf0 (size before relaxing)
.debug_str 0x00000a1c 0x102 ARM Flash Debug/../../obj/com.o
0x19c (size before relaxing)
.debug_str 0x00000b1e 0x89 ARM Flash Debug/../../obj/cop.o
0xf0 (size before relaxing)
.debug_str 0x00000ba7 0x26e ARM Flash Debug/../../obj/xcp.o
0x312 (size before relaxing)
.debug_str 0x00000000 0xe17
.debug_str 0x00000000 0xe8 ARM Flash Debug/../../obj/hooks.o
0x106 (size before relaxing)
.debug_str 0x000000e8 0x9e ARM Flash Debug/../../obj/main.o
0x147 (size before relaxing)
.debug_str 0x00000186 0x65 ARM Flash Debug/../../obj/extflash.o
0x109 (size before relaxing)
.debug_str 0x000001eb 0x247 ARM Flash Debug/../../obj/flash.o
0x30f (size before relaxing)
.debug_str 0x00000432 0x7d ARM Flash Debug/../../obj/can.o
0x121 (size before relaxing)
.debug_str 0x000004af 0xc1 ARM Flash Debug/../../obj/cpu.o
0x18e (size before relaxing)
.debug_str 0x00000570 0xb1 ARM Flash Debug/../../obj/nvm.o
0x186 (size before relaxing)
.debug_str 0x00000621 0xf0 ARM Flash Debug/../../obj/timer.o
0x19f (size before relaxing)
.debug_str 0x00000711 0x119 ARM Flash Debug/../../obj/uart.o
0x1eb (size before relaxing)
.debug_str 0x0000082a 0xb2 ARM Flash Debug/../../obj/assert.o
0x16b (size before relaxing)
.debug_str 0x000008dc 0xae ARM Flash Debug/../../obj/backdoor.o
0x166 (size before relaxing)
.debug_str 0x0000098a 0x83 ARM Flash Debug/../../obj/boot.o
0x127 (size before relaxing)
.debug_str 0x00000a0d 0x11f ARM Flash Debug/../../obj/com.o
0x1f6 (size before relaxing)
.debug_str 0x00000b2c 0x83 ARM Flash Debug/../../obj/cop.o
0x127 (size before relaxing)
.debug_str 0x00000baf 0x268 ARM Flash Debug/../../obj/xcp.o
0x349 (size before relaxing)
.comment 0x00000000 0x11
.comment 0x00000000 0x11 ARM Flash Debug/../../obj/hooks.o
0x12 (size before relaxing)
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/main.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/extflash.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/flash.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/can.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/cpu.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/nvm.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/timer.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/uart.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/assert.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/backdoor.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/boot.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/com.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/cop.o
.comment 0x00000000 0x12 ARM Flash Debug/../../obj/xcp.o
.comment 0x00000000 0x4e
.comment 0x00000000 0x4e ARM Flash Debug/../../obj/hooks.o
0x4f (size before relaxing)
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/main.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/extflash.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/flash.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/can.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/cpu.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/nvm.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/timer.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/uart.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/assert.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/backdoor.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/boot.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/com.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/cop.o
.comment 0x00000000 0x4f ARM Flash Debug/../../obj/xcp.o
.ARM.attributes
0x00000000 0x10
@ -667,32 +671,32 @@ OUTPUT(D:/usr/feaser/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_
.debug_frame 0x00000000 0x5a8
.debug_frame 0x00000000 0x2c ARM Flash Debug/../../obj/main.o
.debug_frame 0x0000002c 0x160 ARM Flash Debug/../../obj/flash.o
.debug_frame 0x0000018c 0x68 ARM Flash Debug/../../obj/cpu.o
.debug_frame 0x000001f4 0x9c ARM Flash Debug/../../obj/nvm.o
.debug_frame 0x00000290 0x78 ARM Flash Debug/../../obj/timer.o
.debug_frame 0x00000308 0x90 ARM Flash Debug/../../obj/uart.o
.debug_frame 0x00000398 0x2c ARM Flash Debug/../../obj/assert.o
.debug_frame 0x000003c4 0x48 ARM Flash Debug/../../obj/backdoor.o
.debug_frame 0x0000040c 0x48 ARM Flash Debug/../../obj/boot.o
.debug_frame 0x00000454 0xa4 ARM Flash Debug/../../obj/com.o
.debug_frame 0x0000002c 0x15c ARM Flash Debug/../../obj/flash.o
.debug_frame 0x00000188 0x68 ARM Flash Debug/../../obj/cpu.o
.debug_frame 0x000001f0 0x9c ARM Flash Debug/../../obj/nvm.o
.debug_frame 0x0000028c 0x5c ARM Flash Debug/../../obj/timer.o
.debug_frame 0x000002e8 0x90 ARM Flash Debug/../../obj/uart.o
.debug_frame 0x00000378 0x2c ARM Flash Debug/../../obj/assert.o
.debug_frame 0x000003a4 0x48 ARM Flash Debug/../../obj/backdoor.o
.debug_frame 0x000003ec 0x48 ARM Flash Debug/../../obj/boot.o
.debug_frame 0x00000434 0xc4 ARM Flash Debug/../../obj/com.o
.debug_frame 0x000004f8 0x30 ARM Flash Debug/../../obj/cop.o
.debug_frame 0x00000528 0x80 ARM Flash Debug/../../obj/xcp.o
.debug_loc 0x00000000 0xb16
.debug_loc 0x00000000 0xae3
.debug_loc 0x00000000 0x20 ARM Flash Debug/../../obj/main.o
.debug_loc 0x00000020 0x4a6 ARM Flash Debug/../../obj/flash.o
.debug_loc 0x000004c6 0x109 ARM Flash Debug/../../obj/cpu.o
.debug_loc 0x000005cf 0xff ARM Flash Debug/../../obj/nvm.o
.debug_loc 0x000006ce 0x40 ARM Flash Debug/../../obj/timer.o
.debug_loc 0x0000070e 0xe9 ARM Flash Debug/../../obj/uart.o
.debug_loc 0x000007f7 0x46 ARM Flash Debug/../../obj/assert.o
.debug_loc 0x0000083d 0x40 ARM Flash Debug/../../obj/backdoor.o
.debug_loc 0x0000087d 0x40 ARM Flash Debug/../../obj/boot.o
.debug_loc 0x000008bd 0xb2 ARM Flash Debug/../../obj/com.o
.debug_loc 0x0000096f 0x1a7 ARM Flash Debug/../../obj/xcp.o
.debug_loc 0x00000020 0x493 ARM Flash Debug/../../obj/flash.o
.debug_loc 0x000004b3 0x109 ARM Flash Debug/../../obj/cpu.o
.debug_loc 0x000005bc 0xff ARM Flash Debug/../../obj/nvm.o
.debug_loc 0x000006bb 0x20 ARM Flash Debug/../../obj/timer.o
.debug_loc 0x000006db 0xe9 ARM Flash Debug/../../obj/uart.o
.debug_loc 0x000007c4 0x46 ARM Flash Debug/../../obj/assert.o
.debug_loc 0x0000080a 0x40 ARM Flash Debug/../../obj/backdoor.o
.debug_loc 0x0000084a 0x40 ARM Flash Debug/../../obj/boot.o
.debug_loc 0x0000088a 0xb2 ARM Flash Debug/../../obj/com.o
.debug_loc 0x0000093c 0x1a7 ARM Flash Debug/../../obj/xcp.o
.debug_aranges 0x00000000 0x2d0
.debug_aranges 0x00000000 0x2d8
.debug_aranges
0x00000000 0x20 ARM Flash Debug/../../obj/main.o
.debug_aranges
@ -704,33 +708,33 @@ OUTPUT(D:/usr/feaser/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_
.debug_aranges
0x000000e8 0x40 ARM Flash Debug/../../obj/nvm.o
.debug_aranges
0x00000128 0x40 ARM Flash Debug/../../obj/timer.o
0x00000128 0x38 ARM Flash Debug/../../obj/timer.o
.debug_aranges
0x00000168 0x40 ARM Flash Debug/../../obj/uart.o
0x00000160 0x40 ARM Flash Debug/../../obj/uart.o
.debug_aranges
0x000001a8 0x20 ARM Flash Debug/../../obj/assert.o
0x000001a0 0x20 ARM Flash Debug/../../obj/assert.o
.debug_aranges
0x000001c8 0x28 ARM Flash Debug/../../obj/backdoor.o
0x000001c0 0x28 ARM Flash Debug/../../obj/backdoor.o
.debug_aranges
0x000001f0 0x28 ARM Flash Debug/../../obj/boot.o
0x000001e8 0x28 ARM Flash Debug/../../obj/boot.o
.debug_aranges
0x00000218 0x48 ARM Flash Debug/../../obj/com.o
0x00000210 0x58 ARM Flash Debug/../../obj/com.o
.debug_aranges
0x00000260 0x28 ARM Flash Debug/../../obj/cop.o
0x00000268 0x28 ARM Flash Debug/../../obj/cop.o
.debug_aranges
0x00000288 0x48 ARM Flash Debug/../../obj/xcp.o
0x00000290 0x48 ARM Flash Debug/../../obj/xcp.o
.debug_ranges 0x00000000 0x208
.debug_ranges 0x00000000 0x210
.debug_ranges 0x00000000 0x10 ARM Flash Debug/../../obj/main.o
.debug_ranges 0x00000010 0x20 ARM Flash Debug/../../obj/cstart.o
.debug_ranges 0x00000030 0x60 ARM Flash Debug/../../obj/flash.o
.debug_ranges 0x00000090 0x20 ARM Flash Debug/../../obj/cpu.o
.debug_ranges 0x000000b0 0x30 ARM Flash Debug/../../obj/nvm.o
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S9030050AC

View File

@ -41,10 +41,15 @@
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
* big endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
#define BOOT_CPU_XTAL_SPEED_KHZ (20000)
#define BOOT_CPU_SYSTEM_SPEED_KHZ (60000)
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
/****************************************************************************************

View File

@ -75,6 +75,30 @@ blt_bool BackDoorEntryHook(void)
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/****************************************************************************************
** NAME: CpuUserProgramStartHook
** PARAMETER: none
** RETURN VALUE: BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
** DESCRIPTION: Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/

View File

@ -2,23 +2,18 @@
<session>
<Bookmarks/>
<Breakpoints/>
<ETMWindow>
<ETMRegister number="0" value="800" />
<ETMRegister number="8" value="6f" />
<ETMRegister number="9" value="1000000" />
</ETMWindow>
<ExecutionCountWindow/>
<ExecutionProfileWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0x80000200" numColumns="8" sizeText="32" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0x80000200" numColumns="8" sizeText="32" dataSize="1" radix="16" name="" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="lpc2294_crossworks" name="unnamed" />
@ -28,16 +23,16 @@
<ProjectSessionItem path="lpc2294_crossworks;openbtl_olimex_lpc_l2294_20mhz;Source Files;Demo;Boot" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -56,8 +51,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\main.c" y="53" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\main.c" left="0" selected="0" name="unnamed" top="47" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="12" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\config.h" y="76" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\config.h" left="0" selected="1" name="unnamed" top="72" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\main.c" y="0" path="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot\main.c" left="0" selected="1" name="unnamed" top="0" />
</Files>
<ARMCrossStudioWindow activeProject="openbtl_olimex_lpc_l2294_20mhz" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Boot" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388479" debugSearchPath="" buildConfiguration="ARM Flash Debug" />
</session>

View File

@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

View File

@ -1,4 +1,4 @@
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@ -30,11 +30,11 @@ S11321A8FBFFFF1A0EF0A0E10130D0E40130C1E4D6
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S10B22480000A0E10000A0E188
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@ -133,7 +133,7 @@ S11328100020C3E55C309FE50120A0E30020C3E570
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@ -174,10 +174,10 @@ S1132AA0F9FFFFEA040040E27000BDE80120D0E431
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View File

@ -2,23 +2,18 @@
<session>
<Bookmarks/>
<Breakpoints/>
<ETMWindow>
<ETMRegister number="0" value="800" />
<ETMRegister number="8" value="6f" />
<ETMRegister number="9" value="1000000" />
</ETMWindow>
<ExecutionCountWindow/>
<ExecutionProfileWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="lpc2294_crossworks" name="unnamed" />
@ -28,16 +23,16 @@
<ProjectSessionItem path="lpc2294_crossworks;demoprog_olimex_lpc_l2294_20mhz;Source Files;Demo;Prog" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -56,8 +51,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\main.c" y="50" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\main.c" left="0" selected="1" name="unnamed" top="50" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.c" y="0" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\boot.c" left="0" selected="0" name="unnamed" top="0" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\main.c" y="36" path="C:\Work\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog\main.c" left="0" selected="1" name="unnamed" top="18" />
</Files>
<ARMCrossStudioWindow activeProject="demoprog_olimex_lpc_l2294_20mhz" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARM7_LPC2000_Olimex_LPC_L2294_Crossworks\Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388479" debugSearchPath="" buildConfiguration="ARM Flash Debug" />
</session>

View File

@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

View File

@ -1,7 +1,7 @@
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View File

@ -1,59 +1,57 @@
bin/openbtl_olimex_lpc_l2294_20mhz.elf: file format elf32-littlearm
bin/openbtl_olimex_lpc_l2294_20mhz.elf
architecture: arm, flags 0x00000112:
architecture: armv4t, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00000000
Program Header:
LOAD off 0x00008000 vaddr 0x00000000 paddr 0x00000000 align 2**15
filesz 0x000013d8 memsz 0x000013d8 flags r-x
LOAD off 0x00010200 vaddr 0x40000200 paddr 0x000013d8 align 2**15
filesz 0x00000000 memsz 0x000004f4 flags rw-
filesz 0x000013e8 memsz 0x000013e8 flags r-x
LOAD off 0x00010200 vaddr 0x40000200 paddr 0x000013e8 align 2**15
filesz 0x00000000 memsz 0x000004f8 flags rw-
private flags = 5000000: [Version5 EABI]
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 000013d8 00000000 00000000 00008000 2**2
0 .text 000013e8 00000000 00000000 00008000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .bss 000004f4 40000200 000013d8 00010200 2**2
1 .bss 000004f8 40000200 000013e8 00010200 2**2
ALLOC
2 .ARM.attributes 00000030 00000000 00000000 000093d8 2**0
2 .ARM.attributes 0000002e 00000000 00000000 000093e8 2**0
CONTENTS, READONLY
3 .comment 0000002a 00000000 00000000 00009408 2**0
3 .comment 00000030 00000000 00000000 00009416 2**0
CONTENTS, READONLY
4 .debug_abbrev 00000aa1 00000000 00000000 00009432 2**0
4 .debug_info 000021c1 00000000 00000000 00009446 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_info 000017a7 00000000 00000000 00009ed3 2**0
5 .debug_abbrev 00000e22 00000000 00000000 0000b607 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_line 0000088b 00000000 00000000 0000b67a 2**0
6 .debug_aranges 000001e8 00000000 00000000 0000c429 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_pubtypes 00000324 00000000 00000000 0000bf05 2**0
7 .debug_line 00000a21 00000000 00000000 0000c611 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_str 00000905 00000000 00000000 0000c229 2**0
8 .debug_str 00000935 00000000 00000000 0000d032 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_loc 00000bed 00000000 00000000 0000cb2e 2**0
9 .debug_loc 00000f2d 00000000 00000000 0000d967 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_pubnames 000003af 00000000 00000000 0000d71b 2**0
10 .debug_frame 00000630 00000000 00000000 0000e894 2**2
CONTENTS, READONLY, DEBUGGING
11 .debug_aranges 000001a0 00000000 00000000 0000daca 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_frame 0000062c 00000000 00000000 0000dc6c 2**2
11 .debug_ranges 00000048 00000000 00000000 0000eec4 2**0
CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00000000 l d .text 00000000 .text
40000200 l d .bss 00000000 .bss
00000000 l d .ARM.attributes 00000000 .ARM.attributes
00000000 l d .comment 00000000 .comment
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_pubtypes 00000000 .debug_pubtypes
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l d .debug_pubnames 00000000 .debug_pubnames
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l df *ABS* 00000000 ./obj/cstart.o
00000004 l *ABS* 00000000 UND_STACK_SIZE
00000004 l *ABS* 00000000 ABT_STACK_SIZE
00000004 l *ABS* 00000000 FIQ_STACK_SIZE
@ -80,98 +78,100 @@ e01fc040 l *ABS* 00000000 MEMMAP
000000a0 l .text 00000000 Reset_Handler_SWI
00000000 l df *ABS* 00000000 hooks.c
00000000 l df *ABS* 00000000 main.c
000012b4 l O .text 00000004 pll_dividers.1366
00000000 l df *ABS* 00000000 extflash.c
00000000 l df *ABS* 00000000 boot.c
00000000 l df *ABS* 00000000 com.c
40000200 l O .bss 00000001 comEntryStateConnect
40000204 l O .bss 00000040 xcpCtoReqPacket.1371
40000204 l O .bss 00000040 xcpCtoReqPacket.4167
00000000 l df *ABS* 00000000 xcp.c
0000032c l F .text 00000014 XcpProtectResources
00000340 l F .text 00000020 XcpSetCtoError
000012b8 l O .text 00000008 xcpStationId
000002e8 l F .text 00000014 XcpProtectResources
000002fc l F .text 00000020 XcpSetCtoError
000012d0 l O .text 00000008 xcpStationId
40000244 l O .bss 0000004c xcpInfo
00000000 l df *ABS* 00000000 backdoor.c
40000290 l O .bss 00000001 backdoorOpen
40000294 l O .bss 00000004 backdoorOpenTime
00000000 l df *ABS* 00000000 cop.c
00000000 l df *ABS* 00000000 assert.c
40000294 l O .bss 00000004 assert_failure_file
40000298 l O .bss 00000004 assert_failure_line
40000298 l O .bss 00000004 assert_failure_file
4000029c l O .bss 00000004 assert_failure_line
00000000 l df *ABS* 00000000 cpu.c
00000000 l df *ABS* 00000000 can.c
00000000 l df *ABS* 00000000 uart.c
000009a8 l F .text 00000028 UartReceiveByte
000009d0 l F .text 00000054 UartTransmitByte
4000029c l O .bss 00000001 xcpCtoRxInProgress.1383
400002a0 l O .bss 00000041 xcpCtoReqPacket.1381
400002e1 l O .bss 00000001 xcpCtoRxLength.1382
00000988 l F .text 00000028 UartReceiveByte
000009b0 l F .text 00000058 UartTransmitByte
400002a0 l O .bss 00000001 xcpCtoRxInProgress.4179
400002a4 l O .bss 00000041 xcpCtoReqPacket.4177
400002e5 l O .bss 00000001 xcpCtoRxLength.4178
00000000 l df *ABS* 00000000 nvm.c
00000000 l df *ABS* 00000000 timer.c
400002e4 l O .bss 00000004 millisecond_counter
400002e8 l O .bss 00000004 free_running_counter_last
400002ec l O .bss 00000004 millisecond_counter
00000000 l df *ABS* 00000000 flash.c
00000cb4 l F .text 0000006c FlashGetSector
00000d20 l F .text 00000110 FlashWriteBlock
00000e30 l F .text 00000038 FlashInitBlock
00000e68 l F .text 00000068 FlashSwitchBlock
00000ed0 l F .text 000000dc FlashAddToBlock
000012c0 l O .text 000000c0 flashLayout
400002ec l O .bss 00000204 blockInfo
400004f0 l O .bss 00000204 bootBlockInfo
00000c90 l F .text 0000006c FlashGetSector
00000cfc l F .text 00000114 FlashWriteBlock
00000e10 l F .text 0000003c FlashInitBlock
00000e4c l F .text 0000006c FlashSwitchBlock
00000eb8 l F .text 000000e0 FlashAddToBlock
000012d8 l O .text 000000c0 flashLayout
400002f0 l O .bss 00000204 blockInfo
400004f4 l O .bss 00000204 bootBlockInfo
00000000 l df *ABS* 00000000 vectors.c
00000278 g F .text 00000044 ComInit
00000fc4 g F .text 0000006c FlashWrite
00000900 g F .text 0000001c AssertFailure
00001280 g F .text 0000001c IRQ_ISR
00000c14 g F .text 0000002c TimerUpdate
000003a0 g F .text 00000014 XcpPacketTransmitted
000002bc g F .text 00000024 ComTask
000002f8 g F .text 00000014 ComSetConnectEntryState
00000244 g F .text 0000001c BootInit
000008d4 g F .text 00000024 BackDoorInit
000008fc g F .text 00000004 CopService
000013d8 g .text 00000000 _etext
00000bf4 g F .text 00000020 TimerReset
00000260 g F .text 00000018 BootTask
00001190 g F .text 00000078 FlashWriteChecksum
00000000 l df *ABS* 00000000
0000021c g F .text 00000044 ComInit
00000fb0 g F .text 00000070 FlashWrite
000008cc g F .text 0000001c AssertFailure
0000129c g F .text 0000001c IRQ_ISR
00000c44 g F .text 00000030 TimerUpdate
0000035c g F .text 00000014 XcpPacketTransmitted
00000260 g F .text 00000024 ComTask
000002a0 g F .text 00000014 ComSetConnectEntryState
000001e0 g F .text 00000020 BootInit
0000089c g F .text 00000028 BackDoorInit
000008c8 g F .text 00000004 CopService
000013e8 g .text 00000000 _etext
00000c24 g F .text 00000020 TimerReset
00000200 g F .text 0000001c BootTask
00001154 g F .text 00000084 FlashWriteChecksum
40000200 g .bss 00000000 _bss_start
000002e0 g F .text 00000018 ComTransmitPacket
00000288 g F .text 00000018 ComTransmitPacket
00000000 g .text 00000000 _startup
00000388 g F .text 00000018 XcpIsConnected
00000b98 g F .text 00000010 NvmInit
00000fac g F .text 00000018 FlashInit
400006f4 g *ABS* 00000000 _bss_end
00000344 g F .text 00000018 XcpIsConnected
00000b80 g F .text 00000010 NvmInit
00000f98 g F .text 00000018 FlashInit
400006f8 g .bss 00000000 _bss_end
00000050 g .text 00000000 Reset_Handler
00000a24 g F .text 00000040 UartInit
00000bb8 g F .text 00000010 NvmErase
000003b4 g F .text 000004d4 XcpPacketReceived
00001208 g F .text 0000005c FlashDone
00000284 g F .text 00000004 ComFree
00000a08 g F .text 00000040 UartInit
00000ba0 g F .text 00000010 NvmErase
00000370 g F .text 000004dc XcpPacketReceived
00001220 g F .text 00000060 FlashDone
000002b4 g F .text 00000014 ComSetDisconnectEntryState
00000040 g .text 00000000 EntryFromProg
0000030c g F .text 00000010 ComIsConnectEntryState
00000360 g F .text 00000028 XcpInit
00001030 g F .text 00000118 FlashErase
00000148 g F .text 000000fc main
00000bd8 g F .text 0000001c NvmDone
00000a64 g F .text 00000084 UartTransmitPacket
00000bc8 g F .text 00000010 NvmVerifyChecksum
0000091c g F .text 00000038 CpuMemCopy
000002c8 g F .text 00000010 ComIsConnectEntryState
0000031c g F .text 00000028 XcpInit
00001020 g F .text 00000134 FlashErase
00000148 g F .text 00000098 main
00000bc0 g F .text 00000024 NvmDone
00000a48 g F .text 00000084 UartTransmitPacket
00000bb0 g F .text 00000010 NvmVerifyChecksum
000008e8 g F .text 00000044 CpuMemCopy
40001edc g *ABS* 00000000 _stack_end
00000c40 g F .text 00000010 TimerSet
00001264 g F .text 0000001c FIQ_ISR
00000ae8 g F .text 000000b0 UartReceivePacket
00001280 g F .text 0000001c FIQ_ISR
00000acc g F .text 000000b4 UartReceivePacket
40000200 g .text 00000000 _data
000008f8 g F .text 00000004 CopInit
00000998 g F .text 00000010 CpuReset
000008c4 g F .text 00000004 CopInit
00000978 g F .text 00000010 CpuReset
000000f4 g .text 00000000 SetupRAM
00000ba8 g F .text 00000010 NvmWrite
00000954 g F .text 00000044 CpuStartUserProgram
00001148 g F .text 00000048 FlashVerifyChecksum
00000b90 g F .text 00000010 NvmWrite
0000092c g F .text 0000004c CpuStartUserProgram
000011d8 g F .text 00000048 FlashVerifyChecksum
40000200 g .text 00000000 _edata
400006f4 g *ABS* 00000000 _end
0000129c g F .text 00000018 UNDEF_ISR
0000031c g F .text 00000010 ComIsConnected
00000888 g F .text 0000004c BackDoorCheck
00000c98 g F .text 0000001c TimerGet
00000c50 g F .text 00000048 TimerInit
400006f8 g .bss 00000000 _end
000012b8 g F .text 00000018 UNDEF_ISR
000002d8 g F .text 00000010 ComIsConnected
0000084c g F .text 00000050 BackDoorCheck
00000c74 g F .text 0000001c TimerGet
00000be4 g F .text 00000040 TimerInit

View File

@ -41,10 +41,15 @@
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
* big endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
#define BOOT_CPU_XTAL_SPEED_KHZ (20000)
#define BOOT_CPU_SYSTEM_SPEED_KHZ (60000)
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
/****************************************************************************************

View File

@ -75,6 +75,30 @@ blt_bool BackDoorEntryHook(void)
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/****************************************************************************************
** NAME: CpuUserProgramStartHook
** PARAMETER: none
** RETURN VALUE: BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
** DESCRIPTION: Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/

View File

@ -1,56 +1,54 @@
bin/demoprog_olimex_lpc_l2294_20mhz.elf: file format elf32-littlearm
bin/demoprog_olimex_lpc_l2294_20mhz.elf
architecture: arm, flags 0x00000112:
architecture: armv4t, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00002000
Program Header:
LOAD off 0x00000000 vaddr 0x00000000 paddr 0x00000000 align 2**15
filesz 0x000028e8 memsz 0x000028e8 flags r-x
LOAD off 0x00008200 vaddr 0x40000200 paddr 0x000028e8 align 2**15
filesz 0x00002b18 memsz 0x00002b18 flags r-x
LOAD off 0x00008200 vaddr 0x40000200 paddr 0x00002b18 align 2**15
filesz 0x00000000 memsz 0x0000005c flags rw-
private flags = 5000002: [Version5 EABI] [has entry point]
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 000008e8 00002000 00002000 00002000 2**2
0 .text 00000b18 00002000 00002000 00002000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .bss 0000005c 40000200 000028e8 00008200 2**2
1 .bss 0000005c 40000200 00002b18 00008200 2**2
ALLOC
2 .ARM.attributes 00000030 00000000 00000000 000028e8 2**0
2 .ARM.attributes 0000002e 00000000 00000000 00002b18 2**0
CONTENTS, READONLY
3 .comment 0000002a 00000000 00000000 00002918 2**0
3 .comment 00000030 00000000 00000000 00002b46 2**0
CONTENTS, READONLY
4 .debug_abbrev 0000029c 00000000 00000000 00002942 2**0
4 .debug_info 000004ce 00000000 00000000 00002b76 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_info 000004b9 00000000 00000000 00002bde 2**0
5 .debug_abbrev 00000310 00000000 00000000 00003044 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_line 00000222 00000000 00000000 00003097 2**0
6 .debug_loc 00000390 00000000 00000000 00003354 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_loc 00000390 00000000 00000000 000032b9 2**0
7 .debug_aranges 000000c0 00000000 00000000 000036e4 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_pubnames 00000175 00000000 00000000 00003649 2**0
8 .debug_line 00000224 00000000 00000000 000037a4 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_aranges 000000c0 00000000 00000000 000037be 2**0
9 .debug_str 000002ab 00000000 00000000 000039c8 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_str 000002a8 00000000 00000000 0000387e 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_frame 000002e0 00000000 00000000 00003b28 2**2
10 .debug_frame 00000310 00000000 00000000 00003c74 2**2
CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00002000 l d .text 00000000 .text
40000200 l d .bss 00000000 .bss
00000000 l d .ARM.attributes 00000000 .ARM.attributes
00000000 l d .comment 00000000 .comment
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l d .debug_pubnames 00000000 .debug_pubnames
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l df *ABS* 00000000 ./obj/cstart.o
00000100 l *ABS* 00000000 UND_STACK_SIZE
00000100 l *ABS* 00000000 ABT_STACK_SIZE
00000100 l *ABS* 00000000 FIQ_STACK_SIZE
@ -75,48 +73,50 @@ SYMBOL TABLE:
00002038 l .text 00000000 IRQ_Addr
00000000 l df *ABS* 00000000 vectors.c
00000000 l df *ABS* 00000000 main.c
0000217c l F .text 000001f0 Init
000028e4 l O .text 00000004 C.0.2054
0000217c l F .text 00000218 Init
00000000 l df *ABS* 00000000 boot.c
0000236c l F .text 0000002c BootActivate
00002538 l F .text 00000064 UartReceiveByte
40000200 l .bss 00000000 xcpCtoRxInProgress.1301
40000204 l .bss 00000000 xcpCtoReqPacket.1299
40000245 l .bss 00000000 xcpCtoRxLength.1300
00002394 l F .text 0000002c BootActivate
00002560 l F .text 00000060 UartReceiveByte
40000200 l .bss 00000000 xcpCtoRxInProgress.4095
40000204 l .bss 00000000 xcpCtoReqPacket.4093
40000245 l .bss 00000000 xcpCtoRxLength.4094
00000000 l df *ABS* 00000000 irq.c
40000248 l .bss 00000000 oldInterruptStatus
4000024c l .bss 00000000 interruptNesting
0000259c l F .text 00000028 IrqGetCPSR
000025c4 l F .text 00000024 IrqSetCPSR
000025c0 l F .text 00000028 IrqGetCPSR
000025e8 l F .text 00000024 IrqSetCPSR
00000000 l df *ABS* 00000000 led.c
40000250 l .bss 00000000 timer_counter_last.1292
40000254 l .bss 00000000 led_toggle_state.1291
40000250 l .bss 00000000 timer_counter_last.4086
40000254 l .bss 00000000 led_toggle_state.4085
00000000 l df *ABS* 00000000 timer.c
40000258 l .bss 00000000 millisecond_counter
00002868 g F .text 0000002c TimerUpdate
000025e8 g F .text 00000030 IrqInterruptEnable
00000000 l df *ABS* 00000000 memcpy.c
00000000 l df *ABS* 00000000
0000288c g F .text 0000002c TimerUpdate
0000260c g F .text 00000030 IrqInterruptEnable
000020d8 g F .text 00000044 TIMER0_ISR
000028e8 g .text 00000000 _etext
00002b18 g .text 00000000 _etext
00002908 g F .text 0000020c memcpy
40000200 g .bss 00000000 _bss_start
00002000 g .text 00000000 _startup
4000025c g *ABS* 00000000 _bss_end
4000025c g .bss 00000000 _bss_end
00002040 g .text 00000000 Reset_Handler
000026f4 g F .text 0000003c LedInit
00002684 g F .text 00000070 IrqInterruptRestore
00002718 g F .text 0000003c LedInit
000026a8 g F .text 00000070 IrqInterruptRestore
0000213c g F .text 00000040 main
40003edc g *ABS* 00000000 _stack_end
00002894 g F .text 0000002c TimerSet
00002398 g F .text 000000b8 BootComInit
000028b8 g F .text 0000002c TimerSet
000023c0 g F .text 000000b8 BootComInit
00002128 g F .text 00000008 FIQ_ISR
40000200 g .text 00000000 _data
00002730 g F .text 000000b4 LedToggle
00002754 g F .text 000000b4 LedToggle
40000200 g .text 00000000 _edata
4000025c g *ABS* 00000000 _end
4000025c g .bss 00000000 _end
00002130 g F .text 0000000c UNDEF_ISR
0000211c g F .text 0000000c SWI_ISR
00002618 g F .text 0000006c IrqInterruptDisable
00002450 g F .text 000000e8 BootComCheckActivationRequest
000028c0 g F .text 00000024 TimerGet
000027e4 g F .text 00000084 TimerInit
0000263c g F .text 0000006c IrqInterruptDisable
00002478 g F .text 000000e8 BootComCheckActivationRequest
000028e4 g F .text 00000024 TimerGet
00002808 g F .text 00000084 TimerInit

View File

@ -11,135 +11,170 @@ S1132080DFF021E300D0A0E134109FE534209FE588
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View File

@ -41,10 +41,15 @@
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
* big endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
#define BOOT_CPU_XTAL_SPEED_KHZ (32000)
#define BOOT_CPU_SYSTEM_SPEED_KHZ (14000)
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
/****************************************************************************************

View File

@ -67,6 +67,30 @@ blt_bool BackDoorEntryHook(void)
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/****************************************************************************************
** NAME: CpuUserProgramStartHook
** PARAMETER: none
** RETURN VALUE: BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
** DESCRIPTION: Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/

View File

@ -2,23 +2,18 @@
<session>
<Bookmarks/>
<Breakpoints/>
<ETMWindow>
<ETMRegister number="0" value="800" />
<ETMRegister number="8" value="6f" />
<ETMRegister number="9" value="1000000" />
</ETMWindow>
<ExecutionCountWindow/>
<ExecutionProfileWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0x4000" numColumns="8" sizeText="128" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="0x4000" numColumns="8" sizeText="128" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_olimex_efm32g880" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="EFM32G880_crossworks" name="unnamed" />
@ -26,22 +21,18 @@
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Demo" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Demo;Boot" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Source" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Source;ARMCM3_EFM32" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;Source Files;Source;ARMCM3_EFM32;Crossworks" name="unnamed" />
<ProjectSessionItem path="EFM32G880_crossworks;openbtl_olimex_efm32g880;System Files" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_efm32g880" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_efm32g880" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_efm32g880" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_olimex_efm32g880" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -60,9 +51,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="8" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Boot\main.c" y="37" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Boot\main.c" left="0" selected="1" name="unnamed" top="36" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_EFM32\cpu.c" y="43" path="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_EFM32\cpu.c" left="0" selected="0" name="unnamed" top="37" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_EFM32\flash.c" y="101" path="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_EFM32\flash.c" left="0" selected="0" name="unnamed" top="74" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Boot\main.c" y="85" path="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Boot\main.c" left="18" selected="1" name="unnamed" top="63" />
</Files>
<ARMCrossStudioWindow activeProject="openbtl_olimex_efm32g880" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_EFM32\Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
<ARMCrossStudioWindow activeProject="openbtl_olimex_efm32g880" autoConnectTarget="SEGGER J-Link" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_EFM32\Crossworks" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
</session>

View File

@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

View File

@ -2,23 +2,18 @@
<session>
<Bookmarks/>
<Breakpoints/>
<ETMWindow>
<ETMRegister number="0" value="800" />
<ETMRegister number="8" value="6f" />
<ETMRegister number="9" value="1000000" />
</ETMWindow>
<ExecutionCountWindow/>
<ExecutionProfileWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="EFM32G880_crossworks" name="unnamed" />
@ -28,16 +23,16 @@
<ProjectSessionItem path="EFM32G880_crossworks;demoprog_olimex_efm32g880;Source Files;Demo;Prog" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -56,7 +51,7 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="40" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Prog\main.c" y="102" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Prog\main.c" left="0" selected="1" name="unnamed" top="76" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Prog\main.c" y="21" path="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Prog\main.c" left="0" selected="1" name="unnamed" top="21" />
</Files>
<ARMCrossStudioWindow activeProject="demoprog_olimex_efm32g880" autoConnectTarget="Olimex ARM-USB-TINY" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_Crossworks\Prog" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
</session>

View File

@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

View File

@ -1,7 +1,6 @@
MEMORY
{
UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000
RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 0x00020000 - 0x2000
}
@ -9,10 +8,8 @@ MEMORY
SECTIONS
{
__CM3_System_Control_Space_segment_start__ = 0xe000e000;
__CM3_System_Control_Space_segment_end__ = 0xe000f000;
__RAM_segment_start__ = 0x20000000;
__RAM_segment_end__ = 0x20004000;
__SRAM_segment_start__ = 0x20000000;
__SRAM_segment_end__ = 0x20004000;
__FLASH_segment_start__ = 0x00002000;
__FLASH_segment_end__ = 0x00020000;
@ -25,8 +22,8 @@ SECTIONS
__STACKSIZE_UND__ = 0;
__HEAPSIZE__ = 128;
__vectors_ram_load_start__ = ALIGN(__RAM_segment_start__ , 256);
.vectors_ram ALIGN(__RAM_segment_start__ , 256) (NOLOAD) : AT(ALIGN(__RAM_segment_start__ , 256))
__vectors_ram_load_start__ = ALIGN(__SRAM_segment_start__ , 256);
.vectors_ram ALIGN(__SRAM_segment_start__ , 256) (NOLOAD) : AT(ALIGN(__SRAM_segment_start__ , 256))
{
__vectors_ram_start__ = .;
*(.vectors_ram .vectors_ram.*)
@ -35,7 +32,7 @@ SECTIONS
__vectors_ram_load_end__ = __vectors_ram_end__;
. = ASSERT(__vectors_ram_end__ >= __RAM_segment_start__ && __vectors_ram_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .vectors_ram is too large to fit in RAM memory segment");
. = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= __SRAM_segment_end__ , "error: .vectors_ram is too large to fit in SRAM memory segment");
__vectors_load_start__ = ALIGN(__FLASH_segment_start__ , 256);
.vectors ALIGN(__FLASH_segment_start__ , 256) : AT(ALIGN(__FLASH_segment_start__ , 256))
@ -47,7 +44,7 @@ SECTIONS
__vectors_load_end__ = __vectors_end__;
. = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .vectors is too large to fit in FLASH memory segment");
. = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= __FLASH_segment_end__ , "error: .vectors is too large to fit in FLASH memory segment");
__init_load_start__ = ALIGN(__vectors_end__ , 4);
.init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
@ -59,7 +56,7 @@ SECTIONS
__init_load_end__ = __init_end__;
. = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .init is too large to fit in FLASH memory segment");
. = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= __FLASH_segment_end__ , "error: .init is too large to fit in FLASH memory segment");
__text_load_start__ = ALIGN(__init_end__ , 4);
.text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
@ -71,7 +68,7 @@ SECTIONS
__text_load_end__ = __text_end__;
. = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .text is too large to fit in FLASH memory segment");
. = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= __FLASH_segment_end__ , "error: .text is too large to fit in FLASH memory segment");
__dtors_load_start__ = ALIGN(__text_end__ , 4);
.dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
@ -83,7 +80,7 @@ SECTIONS
__dtors_load_end__ = __dtors_end__;
. = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .dtors is too large to fit in FLASH memory segment");
. = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= __FLASH_segment_end__ , "error: .dtors is too large to fit in FLASH memory segment");
__ctors_load_start__ = ALIGN(__dtors_end__ , 4);
.ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
@ -95,7 +92,7 @@ SECTIONS
__ctors_load_end__ = __ctors_end__;
. = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .ctors is too large to fit in FLASH memory segment");
. = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= __FLASH_segment_end__ , "error: .ctors is too large to fit in FLASH memory segment");
__rodata_load_start__ = ALIGN(__ctors_end__ , 4);
.rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
@ -107,7 +104,7 @@ SECTIONS
__rodata_load_end__ = __rodata_end__;
. = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .rodata is too large to fit in FLASH memory segment");
. = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= __FLASH_segment_end__ , "error: .rodata is too large to fit in FLASH memory segment");
__ARM.exidx_load_start__ = ALIGN(__rodata_end__ , 4);
.ARM.exidx ALIGN(__rodata_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
@ -121,7 +118,7 @@ SECTIONS
__exidx_end = __ARM.exidx_end__;
__ARM.exidx_load_end__ = __ARM.exidx_end__;
. = ASSERT(__ARM.exidx_end__ >= __FLASH_segment_start__ && __ARM.exidx_end__ <= (__FLASH_segment_start__ + 0x00020000) , "error: .ARM.exidx is too large to fit in FLASH memory segment");
. = ASSERT(__ARM.exidx_end__ >= __FLASH_segment_start__ && __ARM.exidx_end__ <= __FLASH_segment_end__ , "error: .ARM.exidx is too large to fit in FLASH memory segment");
__fast_load_start__ = ALIGN(__ARM.exidx_end__ , 4);
.fast ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__ARM.exidx_end__ , 4))
@ -133,7 +130,7 @@ SECTIONS
__fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
. = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .fast is too large to fit in FLASH memory segment");
. = ASSERT(__fast_load_end__ >= __FLASH_segment_start__ && __fast_load_end__ <= __FLASH_segment_end__ , "error: .fast is too large to fit in FLASH memory segment");
.fast_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
{
@ -144,7 +141,7 @@ SECTIONS
__fast_run_load_end__ = __fast_run_end__;
. = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .fast_run is too large to fit in RAM memory segment");
. = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= __SRAM_segment_end__ , "error: .fast_run is too large to fit in SRAM memory segment");
__data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
.data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
@ -156,7 +153,7 @@ SECTIONS
__data_load_end__ = __data_load_start__ + SIZEOF(.data);
. = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .data is too large to fit in FLASH memory segment");
. = ASSERT(__data_load_end__ >= __FLASH_segment_start__ && __data_load_end__ <= __FLASH_segment_end__ , "error: .data is too large to fit in FLASH memory segment");
.data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
{
@ -167,7 +164,7 @@ SECTIONS
__data_run_load_end__ = __data_run_end__;
. = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .data_run is too large to fit in RAM memory segment");
. = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= __SRAM_segment_end__ , "error: .data_run is too large to fit in SRAM memory segment");
__bss_load_start__ = ALIGN(__data_run_end__ , 4);
.bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
@ -179,7 +176,7 @@ SECTIONS
__bss_load_end__ = __bss_end__;
. = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .bss is too large to fit in RAM memory segment");
. = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= __SRAM_segment_end__ , "error: .bss is too large to fit in SRAM memory segment");
__non_init_load_start__ = ALIGN(__bss_end__ , 4);
.non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
@ -191,7 +188,7 @@ SECTIONS
__non_init_load_end__ = __non_init_end__;
. = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .non_init is too large to fit in RAM memory segment");
. = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= __SRAM_segment_end__ , "error: .non_init is too large to fit in SRAM memory segment");
__heap_load_start__ = ALIGN(__non_init_end__ , 4);
.heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
@ -204,7 +201,7 @@ SECTIONS
__heap_load_end__ = __heap_end__;
. = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .heap is too large to fit in RAM memory segment");
. = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= __SRAM_segment_end__ , "error: .heap is too large to fit in SRAM memory segment");
__stack_load_start__ = ALIGN(__heap_end__ , 4);
.stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
@ -217,7 +214,7 @@ SECTIONS
__stack_load_end__ = __stack_end__;
. = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .stack is too large to fit in RAM memory segment");
. = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= __SRAM_segment_end__ , "error: .stack is too large to fit in SRAM memory segment");
__stack_process_load_start__ = ALIGN(__stack_end__ , 4);
.stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
@ -230,7 +227,7 @@ SECTIONS
__stack_process_load_end__ = __stack_process_end__;
. = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .stack_process is too large to fit in RAM memory segment");
. = ASSERT(__stack_process_end__ >= __SRAM_segment_start__ && __stack_process_end__ <= __SRAM_segment_end__ , "error: .stack_process is too large to fit in SRAM memory segment");
__tbss_load_start__ = ALIGN(__stack_process_end__ , 4);
.tbss ALIGN(__stack_process_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_process_end__ , 4))
@ -242,7 +239,7 @@ SECTIONS
__tbss_load_end__ = __tbss_end__;
. = ASSERT(__tbss_end__ >= __RAM_segment_start__ && __tbss_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .tbss is too large to fit in RAM memory segment");
. = ASSERT(__tbss_end__ >= __SRAM_segment_start__ && __tbss_end__ <= __SRAM_segment_end__ , "error: .tbss is too large to fit in SRAM memory segment");
__tdata_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
.tdata ALIGN(__tbss_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
@ -256,7 +253,7 @@ SECTIONS
__FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.tdata);
. = ASSERT((__tdata_load_start__ + SIZEOF(.tdata)) >= __FLASH_segment_start__ && (__tdata_load_start__ + SIZEOF(.tdata)) <= (__FLASH_segment_start__ + 0x00020000) , "error: .tdata is too large to fit in FLASH memory segment");
. = ASSERT(__tdata_load_end__ >= __FLASH_segment_start__ && __tdata_load_end__ <= __FLASH_segment_end__ , "error: .tdata is too large to fit in FLASH memory segment");
.tdata_run ALIGN(__tbss_end__ , 4) (NOLOAD) :
{
@ -267,9 +264,9 @@ SECTIONS
__tdata_run_load_end__ = __tdata_run_end__;
__RAM_segment_used_end__ = ALIGN(__tbss_end__ , 4) + SIZEOF(.tdata_run);
__SRAM_segment_used_end__ = ALIGN(__tbss_end__ , 4) + SIZEOF(.tdata_run);
. = ASSERT(__tdata_run_end__ >= __RAM_segment_start__ && __tdata_run_end__ <= (__RAM_segment_start__ + 0x00004000) , "error: .tdata_run is too large to fit in RAM memory segment");
. = ASSERT(__tdata_run_end__ >= __SRAM_segment_start__ && __tdata_run_end__ <= __SRAM_segment_end__ , "error: .tdata_run is too large to fit in SRAM memory segment");
}

View File

@ -7,223 +7,185 @@ start address 0x00000000
Program Header:
LOAD off 0x00008000 vaddr 0x00000000 paddr 0x00000000 align 2**15
filesz 0x000015d3 memsz 0x000015d3 flags r-x
LOAD off 0x00010000 vaddr 0x20000000 paddr 0x000015d3 align 2**15
filesz 0x00000138 memsz 0x00000728 flags rwx
filesz 0x0000152f memsz 0x0000152f flags r-x
LOAD off 0x00010000 vaddr 0x20000000 paddr 0x0000152f align 2**15
filesz 0x00000150 memsz 0x00000150 flags rwx
LOAD off 0x00010150 vaddr 0x20000150 paddr 0x00001680 align 2**15
filesz 0x00000000 memsz 0x000005f8 flags rw-
private flags = 5000000: [Version5 EABI]
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 000015d3 00000000 00000000 00008000 2**3
0 .text 0000152f 00000000 00000000 00008000 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .data 00000138 20000000 000015d3 00010000 2**2
1 .data 00000150 20000000 0000152f 00010000 2**2
CONTENTS, ALLOC, LOAD, CODE
2 .bss 000005f0 20000138 0000170b 00010138 2**2
2 .bss 000005f8 20000150 00001680 00010150 2**2
ALLOC
3 .debug_abbrev 00003f13 00000000 00000000 00010138 2**0
3 .debug_info 000068b0 00000000 00000000 00010150 2**0
CONTENTS, READONLY, DEBUGGING
4 .debug_info 0000d7e9 00000000 00000000 0001404b 2**0
4 .debug_abbrev 000021f7 00000000 00000000 00016a00 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_line 00005915 00000000 00000000 00021834 2**0
5 .debug_loc 000030be 00000000 00000000 00018bf7 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_pubtypes 00001800 00000000 00000000 00027149 2**0
6 .debug_aranges 000005b8 00000000 00000000 0001bcb5 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_str 000055da 00000000 00000000 00028949 2**0
7 .debug_ranges 00000980 00000000 00000000 0001c26d 2**0
CONTENTS, READONLY, DEBUGGING
8 .comment 0000002a 00000000 00000000 0002df23 2**0
8 .debug_line 000023f2 00000000 00000000 0001cbed 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_str 00001c9b 00000000 00000000 0001efdf 2**0
CONTENTS, READONLY, DEBUGGING
10 .comment 00000030 00000000 00000000 00020c7a 2**0
CONTENTS, READONLY
9 .ARM.attributes 00000031 00000000 00000000 0002df4d 2**0
11 .ARM.attributes 00000033 00000000 00000000 00020caa 2**0
CONTENTS, READONLY
10 .debug_loc 00006519 00000000 00000000 0002df7e 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_pubnames 00001513 00000000 00000000 00034497 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_aranges 00000c70 00000000 00000000 000359aa 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_ranges 00000af8 00000000 00000000 0003661a 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_frame 00001bdc 00000000 00000000 00037114 2**2
12 .debug_frame 00000bdc 00000000 00000000 00020ce0 2**2
CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00000000 l d .text 00000000 .text
20000000 l d .data 00000000 .data
20000138 l d .bss 00000000 .bss
00000000 l d .debug_abbrev 00000000 .debug_abbrev
20000150 l d .bss 00000000 .bss
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_pubtypes 00000000 .debug_pubtypes
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .comment 00000000 .comment
00000000 l d .ARM.attributes 00000000 .ARM.attributes
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l d .debug_pubnames 00000000 .debug_pubnames
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l df *ABS* 00000000 vectors.c
00000000 l df *ABS* 00000000 cstart.c
000000e2 l F .text 00000000 zero_loop2
0000146e l F .text 00000000 zero_loop
000000e4 l F .text 00000000 zero_loop2
000013c6 l F .text 00000000 zero_loop
00000000 l df *ABS* 00000000 main.c
00000000 l df *ABS* 00000000 system_efm32.c
20000000 l O .data 00000004 SystemLFXOClock
20000004 l O .data 00000004 SystemHFXOClock
00000000 l df *ABS* 00000000 efm32_cmu.c
000003c0 l F .text 0000000e BITBAND_Peripheral
000003d0 l F .text 00000030 CMU_FlashWaitStateMax
00000400 l F .text 0000000c CMU_DivToLog2
0000040c l F .text 00000054 CMU_FlashWaitStateControl
00000460 l F .text 00000018 CMU_Sync
00000478 l F .text 0000003c CMU_LFClkGet
000014b0 l O .text 00000003 CSWTCH.5
000014b3 l O .text 00000003 CSWTCH.8
000003c0 l F .text 00000030 CMU_FlashWaitStateMax
000003f0 l F .text 00000054 CMU_FlashWaitStateControl
00000444 l F .text 00000014 CMU_Sync
00000458 l F .text 0000003c CMU_LFClkGet
00001410 l O .text 00000003 CSWTCH.19
00000000 l df *ABS* 00000000 efm32_emu.c
20000138 l O .bss 00000002 cmuStatus
20000150 l O .bss 00000002 cmuStatus
00000000 l df *ABS* 00000000 efm32_gpio.c
00000000 l df *ABS* 00000000 efm32_leuart.c
000009bc l F .text 00000010 LEUART_Sync
00000968 l F .text 0000000e LEUART_Sync
00000000 l df *ABS* 00000000 efm32_msc.c
00000000 l df *ABS* 00000000 efm32_system.c
00000000 l df *ABS* 00000000 boot.c
00000000 l df *ABS* 00000000 com.c
2000013a l O .bss 00000001 comEntryStateConnect
2000013b l O .bss 00000040 xcpCtoReqPacket.1375
20000152 l O .bss 00000001 comEntryStateConnect
20000153 l O .bss 00000040 xcpCtoReqPacket.4167
00000000 l df *ABS* 00000000 xcp.c
00000ba4 l F .text 0000000c XcpProtectResources
00000bb0 l F .text 00000014 XcpSetCtoError
000014b6 l O .text 00000008 xcpStationId
2000017c l O .bss 0000004c xcpInfo
00000b30 l F .text 00000014 XcpSetCtoError
00001413 l O .text 00000008 xcpStationId
20000194 l O .bss 0000004c xcpInfo
00000000 l df *ABS* 00000000 backdoor.c
200001c8 l O .bss 00000001 backdoorOpen
200001e0 l O .bss 00000001 backdoorOpen
200001e4 l O .bss 00000004 backdoorOpenTime
00000000 l df *ABS* 00000000 cop.c
00000000 l df *ABS* 00000000 assert.c
200001cc l O .bss 00000004 assert_failure_file
200001d0 l O .bss 00000004 assert_failure_line
200001e8 l O .bss 00000004 assert_failure_file
200001ec l O .bss 00000004 assert_failure_line
00000000 l df *ABS* 00000000 cpu.c
00000000 l df *ABS* 00000000 uart.c
00000e94 l F .text 00000020 UartReceiveByte
00000eb4 l F .text 00000030 UartTransmitByte
200001d4 l O .bss 00000041 xcpCtoReqPacket.2673
20000215 l O .bss 00000001 xcpCtoRxLength.2674
20000216 l O .bss 00000001 xcpCtoRxInProgress.2675
000014e4 l O .text 00000010 C.4.3618
200001f0 l O .bss 00000001 xcpCtoRxLength.5470
200001f1 l O .bss 00000041 xcpCtoReqPacket.5469
20000232 l O .bss 00000001 xcpCtoRxInProgress.5471
00000000 l df *ABS* 00000000 nvm.c
00000000 l df *ABS* 00000000 timer.c
20000218 l O .bss 00000002 millisecond_counter
20000234 l O .bss 00000002 millisecond_counter
00000000 l df *ABS* 00000000 flash.c
000010b8 l F .text 00000038 FlashGetSector
000010f0 l F .text 00000030 FlashGetSectorBaseAddr
00001120 l F .text 0000004e FlashWriteBlock
0000116e l F .text 00000026 FlashInitBlock
00001194 l F .text 00000040 FlashSwitchBlock
000011d4 l F .text 00000080 FlashAddToBlock
000014f4 l O .text 000000b4 flashLayout
2000021c l O .bss 00000204 bootBlockInfo
20000420 l O .bss 00000204 blockInfo
00000000 l df *ABS* 00000000 hooks.c
00000000 l df *ABS* 00000000 core_cm3.c
00000000 l df *ABS* 00000000 efm32_acmp.c
00000000 l df *ABS* 00000000 efm32_adc.c
00000000 l df *ABS* 00000000 efm32_aes.c
00000000 l df *ABS* 00000000 efm32_assert.c
00000000 l df *ABS* 00000000 efm32_dac.c
00000000 l df *ABS* 00000000 efm32_dbg.c
00000000 l df *ABS* 00000000 efm32_dma.c
00000000 l df *ABS* 00000000 efm32_ebi.c
00000000 l df *ABS* 00000000 efm32_i2c.c
00000000 l df *ABS* 00000000 efm32_int.c
00000000 l df *ABS* 00000000 efm32_lcd.c
00000000 l df *ABS* 00000000 efm32_lesense.c
00000000 l df *ABS* 00000000 efm32_letimer.c
00000000 l df *ABS* 00000000 efm32_mpu.c
00000000 l df *ABS* 00000000 efm32_opamp.c
00000000 l df *ABS* 00000000 efm32_pcnt.c
00000000 l df *ABS* 00000000 efm32_prs.c
00000000 l df *ABS* 00000000 efm32_rmu.c
00000000 l df *ABS* 00000000 efm32_rtc.c
00000000 l df *ABS* 00000000 efm32_timer.c
00000000 l df *ABS* 00000000 efm32_usart.c
00000000 l df *ABS* 00000000 efm32_vcmp.c
00000000 l df *ABS* 00000000 efm32_wdog.c
00001490 l F .text 00000010 __MSC_ErasePage_veneer
000014a0 l F .text 00000010 __MSC_WriteWord_veneer
00000b38 g F .text 0000002c ComInit
00001270 g F .text 00000048 FlashWrite
00000900 g F .text 00000018 GPIO_DriveModeSet
00000e34 g F .text 00000018 AssertFailure
000008ec g F .text 00000014 EMU_UpdateOscConfig
00001450 g F .text 00000038 reset_handler
000006b8 g F .text 00000128 CMU_ClockFreqGet
0000105c g F .text 0000001c TimerUpdate
00000bf0 g F .text 00000010 XcpPacketTransmitted
00000a14 g F .text 00000018 LEUART_Enable
00000a2c g F .text 00000012 LEUART_FreezeEnable
00000b64 g F .text 0000001c ComTask
00000b94 g F .text 0000000c ComSetConnectEntryState
00000b10 g F .text 00000016 BootInit
00000e18 g F .text 00000018 BackDoorInit
000007e0 g F .text 00000054 CMU_OscillatorEnable
00000e32 g F .text 00000002 CopService
000015d3 g .text 00000000 _etext
0000063c g F .text 0000007c CMU_ClockSelectGet
00001050 g F .text 0000000c TimerReset
20000624 g O .bss 00000004 SystemCoreClock
00000b26 g F .text 00000012 BootTask
00001384 g F .text 00000044 FlashWriteChecksum
00000b82 g F .text 00000010 ComTransmitPacket
00001024 l F .text 0000003c FlashGetSector
00001060 l F .text 00000044 FlashWriteBlock
000010a4 l F .text 0000004c FlashSwitchBlock
000010f0 l F .text 00000084 FlashAddToBlock
00001450 l O .text 000000b4 flashLayout
20000238 l O .bss 00000204 bootBlockInfo
2000043c l O .bss 00000204 blockInfo
00000000 l df *ABS* 00000000
00000100 l *ABS* 00000000 __STACKSIZE__
000013f0 l F .text 00000010 __MSC_ErasePage_veneer
00001400 l F .text 00000010 __MSC_WriteWord_veneer
00000ac4 g F .text 0000002c ComInit
00001190 g F .text 00000048 FlashWrite
000008c0 g F .text 00000018 GPIO_DriveModeSet
00000dc4 g F .text 00000018 AssertFailure
000008ac g F .text 00000014 EMU_UpdateOscConfig
000013a4 g F .text 00000044 reset_handler
00000684 g F .text 00000120 CMU_ClockFreqGet
00000ff8 g F .text 0000001c TimerUpdate
00000b70 g F .text 00000010 XcpPacketTransmitted
000009bc g F .text 00000018 LEUART_Enable
00000af0 g F .text 0000001c ComTask
00000b20 g F .text 0000000c ComSetConnectEntryState
00000a94 g F .text 0000001a BootInit
00000da0 g F .text 00000020 BackDoorInit
000007a4 g F .text 00000050 CMU_OscillatorEnable
00000dc2 g F .text 00000002 CopService
0000152f g .text 00000000 _etext
0000061c g F .text 00000068 CMU_ClockSelectGet
00000fec g F .text 0000000c TimerReset
20000640 g O .bss 00000004 SystemCoreClock
00000aae g F .text 00000016 BootTask
000012d4 g F .text 00000040 FlashWriteChecksum
00000b0e g F .text 00000010 ComTransmitPacket
000003b4 g F .text 0000000c SystemLFXOClockGet
000005c8 g F .text 00000074 CMU_ClockEnable
00000a86 g F .text 0000000e LEUART_Rx
00000be0 g F .text 00000010 XcpIsConnected
0000102c g F .text 00000004 NvmInit
00001254 g F .text 0000001c FlashInit
20000628 g .bss 00000000 _ebss
00000100 g *ABS* 00000000 __STACKSIZE__
00001444 g F .text 0000000c UnusedISR
00000b80 g F .text 00000002 ComFree
00000a3e g F .text 00000048 LEUART_Init
20000080 g F .data 000000b4 MSC_WriteWord
00000ee4 g F .text 00000094 UartInit
00000ad0 g F .text 0000001c MSC_Deinit
00000834 g F .text 000000b8 CMU_ClockSelectSet
00001034 g F .text 00000004 NvmErase
20000138 g .bss 00000000 _bss
000005b0 g F .text 0000006c CMU_ClockEnable
00000a14 g F .text 0000000c LEUART_Rx
00000b60 g F .text 00000010 XcpIsConnected
00000fa8 g F .text 00000004 NvmInit
00001174 g F .text 0000001c FlashInit
20000648 g .bss 00000000 _ebss
00001398 g F .text 0000000c UnusedISR
00000b0c g F .text 00000002 ComFree
000009d4 g F .text 00000040 LEUART_Init
2000007c g F .data 000000d0 MSC_WriteWord
00000e28 g F .text 00000094 UartInit
00000a58 g F .text 0000001c MSC_Deinit
000007f4 g F .text 000000b8 CMU_ClockSelectSet
00000fb0 g F .text 00000004 NvmErase
20000150 g .bss 00000000 _bss
000002f4 g F .text 00000098 SystemHFClockGet
00000c00 g F .text 000001e8 XcpPacketReceived
20000008 g F .data 00000078 MSC_ErasePage
00001410 g F .text 00000034 FlashDone
000000b8 g F .text 0000004c EntryFromProg
00000bc4 g F .text 0000001c XcpInit
000012b8 g F .text 000000cc FlashErase
00000118 g F .text 000001dc main
0000103c g F .text 00000012 NvmDone
00000f78 g F .text 00000050 UartTransmitPacket
00001038 g F .text 00000004 NvmVerifyChecksum
00000e70 g F .text 00000020 CpuMemCopy
00001078 g F .text 0000000c TimerSet
00000918 g F .text 000000a4 GPIO_PinModeSet
00000b80 g F .text 000001e8 XcpPacketReceived
20000008 g F .data 00000074 MSC_ErasePage
0000135c g F .text 0000003c FlashDone
000000b8 g F .text 00000050 EntryFromProg
00000b44 g F .text 0000001c XcpInit
000011d8 g F .text 000000fc FlashErase
0000011c g F .text 000001d8 main
00000fb8 g F .text 00000012 NvmDone
00000ebc g F .text 00000080 UartTransmitPacket
00000fb4 g F .text 00000004 NvmVerifyChecksum
00000e04 g F .text 0000001e CpuMemCopy
000008d8 g F .text 00000090 GPIO_PinModeSet
000003ac g F .text 00000002 SystemInit
00000a94 g F .text 0000001a LEUART_Tx
000004b4 g F .text 00000114 CMU_ClockDivSet
00000fc8 g F .text 00000064 UartReceivePacket
00000a20 g F .text 00000018 LEUART_Tx
00000494 g F .text 0000011c CMU_ClockDivSet
00000f3c g F .text 0000006c UartReceivePacket
20000000 g .data 00000000 _data
00000e30 g F .text 00000002 CopInit
00000dc0 g F .text 00000002 CopInit
000003ae g F .text 00000006 SystemLFRCOClockGet
00000e90 g F .text 00000004 CpuReset
000009cc g F .text 00000048 LEUART_BaudrateSet
00000aec g F .text 00000024 SYSTEM_ChipRevisionGet
00000e22 g F .text 00000004 CpuReset
00000978 g F .text 00000044 LEUART_BaudrateSet
00000a74 g F .text 00000020 SYSTEM_ChipRevisionGet
0000038c g F .text 00000020 SystemCoreClockGet
00001030 g F .text 00000004 NvmWrite
00000e4c g F .text 00000024 CpuStartUserProgram
20000728 g .bss 00000000 _estack
000013c8 g F .text 00000046 FlashVerifyChecksum
20000138 g .data 00000000 _edata
00000fac g F .text 00000004 NvmWrite
00000ddc g F .text 00000028 CpuStartUserProgram
20000748 g .bss 00000000 _estack
00001314 g F .text 00000048 FlashVerifyChecksum
20000150 g .data 00000000 _edata
00000000 g O .text 000000b8 _vectab
00000ba0 g F .text 00000004 ComIsConnected
00000de8 g F .text 00000030 BackDoorCheck
20000628 g .bss 00000000 _stack
000010a8 g F .text 00000010 TimerGet
00001084 g F .text 00000024 TimerInit
00000ab0 g F .text 00000020 MSC_Init
00000b2c g F .text 00000004 ComIsConnected
00000d68 g F .text 00000038 BackDoorCheck
20000648 g .bss 00000000 _stack
00001014 g F .text 00000010 TimerGet
00000fcc g F .text 00000020 TimerInit
00000a38 g F .text 00000020 MSC_Init

View File

@ -41,10 +41,15 @@
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
* big endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
#define BOOT_CPU_XTAL_SPEED_KHZ (32000)
#define BOOT_CPU_SYSTEM_SPEED_KHZ (14000)
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
/****************************************************************************************

View File

@ -67,6 +67,30 @@ blt_bool BackDoorEntryHook(void)
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/****************************************************************************************
** NAME: CpuUserProgramStartHook
** PARAMETER: none
** RETURN VALUE: BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
** DESCRIPTION: Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/

View File

@ -172,7 +172,7 @@ LIB_PATH = -L../../../Source/ARMCM3_EFM32/GCC/
#|---------------------------------------------------------------------------------------|
CFLAGS = -g -D inline= -mthumb -mcpu=cortex-m3 -Os -T memory.x
CFLAGS += -D PACK_STRUCT_END=__attribute\(\(packed\)\) -Wno-main
CFLAGS += -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\)
CFLAGS += -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) -Wno-attributes
CFLAGS += -ffunction-sections -fdata-sections $(INC_PATH) -D EFM32G880F128
CFLAGS += -Wa,-adhlns="$(OBJ_PATH)/$(subst .o,.lst,$@)"
LFLAGS = -nostartfiles -Xlinker -M -Xlinker -Map=$(BIN_PATH)/$(PROJ_NAME).map

View File

@ -7,72 +7,65 @@ start address 0x00002000
Program Header:
LOAD off 0x00000000 vaddr 0x00000000 paddr 0x00000000 align 2**15
filesz 0x0000344c memsz 0x0000344c flags r-x
LOAD off 0x00008000 vaddr 0x20000000 paddr 0x0000344c align 2**15
filesz 0x0000315c memsz 0x0000315c flags r-x
LOAD off 0x00008000 vaddr 0x20000000 paddr 0x0000315c align 2**15
filesz 0x00000008 memsz 0x00000168 flags rw-
private flags = 5000002: [Version5 EABI] [has entry point]
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 0000144c 00002000 00002000 00002000 2**2
0 .text 0000115c 00002000 00002000 00002000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .data 00000008 20000000 0000344c 00008000 2**2
1 .data 00000008 20000000 0000315c 00008000 2**2
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000160 20000008 00003454 00008008 2**2
2 .bss 00000160 20000008 00003164 00008008 2**2
ALLOC
3 .debug_abbrev 000039ba 00000000 00000000 00008008 2**0
3 .debug_info 00005a0f 00000000 00000000 00008008 2**0
CONTENTS, READONLY, DEBUGGING
4 .debug_info 0000db0e 00000000 00000000 0000b9c2 2**0
4 .debug_abbrev 00001851 00000000 00000000 0000da17 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_line 0000554b 00000000 00000000 000194d0 2**0
5 .debug_loc 00002ba8 00000000 00000000 0000f268 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_loc 000065d3 00000000 00000000 0001ea1b 2**0
6 .debug_aranges 00000488 00000000 00000000 00011e10 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_pubnames 0000138d 00000000 00000000 00024fee 2**0
7 .debug_ranges 000003a8 00000000 00000000 00012298 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_pubtypes 00001700 00000000 00000000 0002637b 2**0
8 .debug_line 00001e4a 00000000 00000000 00012640 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_aranges 00000b10 00000000 00000000 00027a7b 2**0
9 .debug_str 00001a6b 00000000 00000000 0001448a 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_ranges 000008f0 00000000 00000000 0002858b 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_str 000051e2 00000000 00000000 00028e7b 2**0
CONTENTS, READONLY, DEBUGGING
12 .comment 0000002a 00000000 00000000 0002e05d 2**0
10 .comment 00000030 00000000 00000000 00015ef5 2**0
CONTENTS, READONLY
13 .ARM.attributes 00000031 00000000 00000000 0002e087 2**0
11 .ARM.attributes 00000033 00000000 00000000 00015f25 2**0
CONTENTS, READONLY
14 .debug_frame 000017ac 00000000 00000000 0002e0b8 2**2
12 .debug_frame 00000904 00000000 00000000 00015f58 2**2
CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00002000 l d .text 00000000 .text
20000000 l d .data 00000000 .data
20000008 l d .bss 00000000 .bss
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_info 00000000 .debug_info
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_abbrev 00000000 .debug_abbrev
00000000 l d .debug_loc 00000000 .debug_loc
00000000 l d .debug_pubnames 00000000 .debug_pubnames
00000000 l d .debug_pubtypes 00000000 .debug_pubtypes
00000000 l d .debug_aranges 00000000 .debug_aranges
00000000 l d .debug_ranges 00000000 .debug_ranges
00000000 l d .debug_line 00000000 .debug_line
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .comment 00000000 .comment
00000000 l d .ARM.attributes 00000000 .ARM.attributes
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l df *ABS* 00000000 vectors.c
00000000 l df *ABS* 00000000 boot.c
000020bc l F .text 00000034 UartReceiveByte
20000008 l O .bss 00000001 xcpCtoRxLength.2654
20000009 l O .bss 00000001 xcpCtoRxInProgress.2655
0000343c l O .text 00000010 C.3.3551
2000000c l O .bss 00000041 xcpCtoReqPacket.2653
000020bc l F .text 0000002c UartReceiveByte
20000008 l O .bss 00000041 xcpCtoReqPacket.5451
2000004c l O .bss 00000001 xcpCtoRxLength.5452
2000004d l O .bss 00000001 xcpCtoRxInProgress.5453
00000000 l df *ABS* 00000000 cstart.c
000022de l F .text 00000000 zero_loop
00002276 l F .text 00000000 zero_loop
00000000 l df *ABS* 00000000 irq.c
00000000 l df *ABS* 00000000 led.c
20000050 l O .bss 00000004 timer_counter_last.2646
20000054 l O .bss 00000001 led_toggle_state.2645
20000050 l O .bss 00000004 timer_counter_last.5444
20000054 l O .bss 00000001 led_toggle_state.5443
00000000 l df *ABS* 00000000 main.c
00000000 l df *ABS* 00000000 timer.c
20000058 l O .bss 00000004 millisecond_counter
@ -80,95 +73,70 @@ SYMBOL TABLE:
20000000 l O .data 00000004 SystemLFXOClock
20000004 l O .data 00000004 SystemHFXOClock
00000000 l df *ABS* 00000000 lcdcontroller.c
000027e4 l F .text 00000060 LCD_enableSegment
00002844 l F .text 00000070 LCD_disableSegment
000026c0 l F .text 00000060 LCD_enableSegment
00002720 l F .text 00000070 LCD_disableSegment
00000000 l df *ABS* 00000000 efm32_cmu.c
00002a40 l F .text 00000010 BITBAND_Peripheral
00002a50 l F .text 00000038 CMU_FlashWaitStateMax
00002a88 l F .text 0000000c CMU_DivToLog2
00002a94 l F .text 00000064 CMU_FlashWaitStateControl
00002af8 l F .text 0000000a CMU_AUXClkGet
00002b04 l F .text 00000020 CMU_Sync
00002b24 l F .text 00000052 CMU_LFClkGet
00002904 l F .text 00000010 BITBAND_Peripheral
00002914 l F .text 00000030 CMU_FlashWaitStateMax
00002944 l F .text 0000000c CMU_DivToLog2
00002950 l F .text 00000058 CMU_FlashWaitStateControl
000029a8 l F .text 00000008 CMU_AUXClkGet
000029b0 l F .text 00000018 CMU_Sync
000029c8 l F .text 0000004c CMU_LFClkGet
00000000 l df *ABS* 00000000 efm32_emu.c
20000060 l O .bss 00000002 cmuStatus
00000000 l df *ABS* 00000000 efm32_gpio.c
00000000 l df *ABS* 00000000 efm32_leuart.c
000032f8 l F .text 00000010 LEUART_Sync
00003028 l F .text 00000010 LEUART_Sync
00000000 l df *ABS* 00000000 efm32_system.c
00000000 l df *ABS* 00000000 core_cm3.c
00000000 l df *ABS* 00000000 efm32_acmp.c
00000000 l df *ABS* 00000000 efm32_adc.c
00000000 l df *ABS* 00000000 efm32_aes.c
00000000 l df *ABS* 00000000 efm32_assert.c
00000000 l df *ABS* 00000000 efm32_dac.c
00000000 l df *ABS* 00000000 efm32_dbg.c
00000000 l df *ABS* 00000000 efm32_dma.c
00000000 l df *ABS* 00000000 efm32_ebi.c
00000000 l df *ABS* 00000000 efm32_i2c.c
00000000 l df *ABS* 00000000 efm32_int.c
00000000 l df *ABS* 00000000 efm32_lcd.c
00000000 l df *ABS* 00000000 efm32_lesense.c
00000000 l df *ABS* 00000000 efm32_letimer.c
00000000 l df *ABS* 00000000 efm32_mpu.c
00000000 l df *ABS* 00000000 efm32_msc.c
00000000 l df *ABS* 00000000 efm32_opamp.c
00000000 l df *ABS* 00000000 efm32_pcnt.c
00000000 l df *ABS* 00000000 efm32_prs.c
00000000 l df *ABS* 00000000 efm32_rmu.c
00000000 l df *ABS* 00000000 efm32_rtc.c
00000000 l df *ABS* 00000000 efm32_timer.c
00000000 l df *ABS* 00000000 efm32_usart.c
00000000 l df *ABS* 00000000 efm32_vcmp.c
00000000 l df *ABS* 00000000 efm32_wdog.c
00000000 l df *ABS* 00000000 strlen.c
000031f4 g F .text 0000001e GPIO_DriveModeSet
000031dc g F .text 00000016 EMU_UpdateOscConfig
00002298 g F .text 0000005c reset_handler
00002e5c g F .text 000001e6 CMU_ClockFreqGet
0000336c g F .text 00000022 LEUART_Enable
00003390 g F .text 00000018 LEUART_FreezeEnable
00002300 g F .text 00000004 IrqInterruptEnable
00000000 l df *ABS* 00000000
00000100 l *ABS* 00000000 __STACKSIZE__
00002f34 g F .text 0000001c GPIO_DriveModeSet
00002f20 g F .text 00000014 EMU_UpdateOscConfig
0000223c g F .text 00000060 reset_handler
00002c50 g F .text 00000170 CMU_ClockFreqGet
0000308c g F .text 00000020 LEUART_Enable
000030ac g F .text 00000018 LEUART_FreezeEnable
000022a8 g F .text 00000004 IrqInterruptEnable
2000005c g O .bss 00000004 frameCounter
00003044 g F .text 00000074 CMU_OscillatorEnable
000028f0 g F .text 000000a8 LCD_Symbol
0000344c g .text 00000000 _etext
000026d0 g F .text 00000012 TimerISRHandler
00002db0 g F .text 000000aa CMU_ClockSelectGet
00002dc0 g F .text 00000064 CMU_OscillatorEnable
000027c8 g F .text 000000a4 LCD_Symbol
0000315c g .text 00000000 _etext
000025d0 g F .text 00000010 TimerISRHandler
00002bb4 g F .text 0000009c CMU_ClockSelectGet
20000064 g O .bss 00000004 SystemCoreClock
000027d8 g F .text 0000000c SystemLFXOClockGet
00002d28 g F .text 00000088 CMU_ClockEnable
000028d4 g F .text 0000001c LCD_AllOff
00003408 g F .text 0000000e LEUART_Rx
000026b4 g F .text 0000000c SystemLFXOClockGet
00002b3c g F .text 00000078 CMU_ClockEnable
000027ac g F .text 0000001c LCD_AllOff
0000311c g F .text 0000000e LEUART_Rx
20000068 g .bss 00000000 _ebss
000028b4 g F .text 00000020 LCD_IRQHandler
00000100 g *ABS* 00000000 __STACKSIZE__
000026e4 g F .text 00000002 UnusedISR
00002304 g F .text 00000016 LedInit
000033a8 g F .text 0000005e LEUART_Init
000030b8 g F .text 00000122 CMU_ClockSelectSet
00002790 g F .text 0000001c LCD_IRQHandler
000025e0 g F .text 00000002 UnusedISR
000022ac g F .text 00000014 LedInit
000030c4 g F .text 00000058 LEUART_Init
00002e24 g F .text 000000fc CMU_ClockSelectSet
20000008 g .bss 00000000 _bss
000026e8 g F .text 000000b6 SystemHFClockGet
00002998 g F .text 000000a6 LCD_Init
0000239c g F .text 000002b0 main
0000265c g F .text 0000000c TimerSet
00003214 g F .text 000000e2 GPIO_PinModeSet
000020f0 g F .text 000000ea BootComInit
000027cc g F .text 00000002 SystemInit
00002b78 g F .text 000001b0 CMU_ClockDivSet
0000264c g F .text 00000010 TimerDeinit
000025e4 g F .text 000000a0 SystemHFClockGet
0000286c g F .text 00000098 LCD_Init
00002318 g F .text 00000240 main
00002568 g F .text 0000000c TimerSet
00002f50 g F .text 000000d8 GPIO_PinModeSet
000020e8 g F .text 000000d0 BootComInit
000026a8 g F .text 00000002 SystemInit
00002a14 g F .text 00000128 CMU_ClockDivSet
00002558 g F .text 00000010 TimerDeinit
20000000 g .data 00000000 _data
0000231c g F .text 00000080 LedToggle
000027d0 g F .text 00000006 SystemLFRCOClockGet
00003308 g F .text 00000064 LEUART_BaudrateSet
00003418 g F .text 00000024 SYSTEM_ChipRevisionGet
000027a0 g F .text 0000002a SystemCoreClockGet
000022c0 g F .text 00000058 LedToggle
000026ac g F .text 00000006 SystemLFRCOClockGet
00003038 g F .text 00000054 LEUART_BaudrateSet
0000312c g F .text 00000020 SYSTEM_ChipRevisionGet
00002684 g F .text 00000024 SystemCoreClockGet
20000168 g .bss 00000000 _estack
20000008 g .data 00000000 _edata
00002000 g O .text 000000bc _vectab
000021dc g F .text 000000bc BootComCheckActivationRequest
000021b8 g F .text 00000084 BootComCheckActivationRequest
20000068 g .bss 00000000 _stack
000026c4 g F .text 0000000c TimerGet
00002668 g F .text 0000005a TimerInit
000025c4 g F .text 0000000c TimerGet
00002574 g F .text 00000050 TimerInit

View File

@ -1,328 +1,281 @@
S025000062696E2F64656D6F70726F675F6F6C696D65785F65666D3332673838302E737265634A
S11320006801002099220000E5260000E526000072
S1132010E5260000E5260000E5260000E526000090
S1132020E5260000E5260000E5260000E526000080
S1132030E5260000E5260000E5260000D126000084
S1132040E5260000E5260000E5260000E526000060
S1132050E5260000E5260000E5260000E526000050
S1132060E5260000E5260000E5260000E526000040
S1132070E5260000E5260000E5260000E526000030
S1132080E5260000E5260000E5260000E526000020
S1132090E5260000E5260000E5260000E526000010
S11320A0E5260000E5260000E5260000B52800002E
S11320B0E5260000E5260000EE11AA5510B50446F9
S11320C04FF48843C4F20803DB6A13F0040F0CD006
S11320D04FF48840C4F2080043F20943C0F20003FD
S11320E0984720704FF0010010BD4FF0000010BD64
S11320F070B584B043F23C43C0F200036E460FCB8C
S113210086E80F004FF44240C0F202004FF0010194
S113211042F62954C0F20004A0474FF002004FF0E9
S113212006014FF004024FF0010343F21525C0F2FB
S11321300005A8474FF002004FF007014FF00102DD
S11321404FF00003A8474FF40C50C0F204004FF0C6
S11321500101A0474FF00300C0F212004FF002014A
S113216043F2B903C0F2000398474FF4AA55C0F2F2
S1132170160528464FF0010142F67933C0F20003F8
S1132180984728464FF00101A0474FF000058DF80D
S113219000504FF48844C4F208042046694643F2D0
S11321A0A933C0F200039847204629464FF416523B
S11321B043F20933C0F2000398474FF00303636509
S11321C04FF00403636320464FF0050143F26D337F
S11321D0C0F20003984704B070BD00BF08B540F2D8
S11321E00903C2F200031B78CBB940F20C00C2F21F
S11321F0000042F2BD03C0F200039847012848D111
S113220040F20903C2F200034FF001021A7040F2D7
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@ -160,7 +160,7 @@ CFLAGS = -g -D inline= -mthumb -mcpu=cortex-m3 -mlong-calls -O1 -T memory.x
CFLAGS += -D PACK_STRUCT_END=__attribute\(\(packed\)\) -D sprintf=usprintf -Wno-main
CFLAGS += -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) -D snprintf=usnprintf
CFLAGS += -D printf=uipprintf -ffunction-sections -fdata-sections $(INC_PATH)
CFLAGS += -D EFM32G880F128
CFLAGS += -D EFM32G880F128 -Wno-attributes
LFLAGS = -nostartfiles -Xlinker -M -Xlinker -Map=$(BIN_PATH)/$(PROJ_NAME).map
LFLAGS += $(LIB_PATH) -Xlinker --gc-sections
OFLAGS = -O srec

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@ -1,418 +1,418 @@
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S11318F8007202000082020000B2020000E202004C
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S113191811F03F0101700649096811F0F001054A08
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S11319D8002000000020000001000000004000007A
S11319E80020000002000000006000000020000049
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@ -424,42 +424,41 @@ S1131A48002000000A0000000060010000200000DF
S1131A580B00000000800100002000000C000000C2
S1131A6800A00100002000000D00000000C00100DB
S1131A78002000000E00000000E00100002000002B
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S9031B5190

View File

@ -41,10 +41,15 @@
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
* big endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
#define BOOT_CPU_XTAL_SPEED_KHZ (32000)
#define BOOT_CPU_SYSTEM_SPEED_KHZ (14000)
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
#define BOOT_CPU_CONNECT_STATE_PREFIX __no_init

View File

@ -67,6 +67,30 @@ blt_bool BackDoorEntryHook(void)
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/****************************************************************************************
** NAME: CpuUserProgramStartHook
** PARAMETER: none
** RETURN VALUE: BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
** DESCRIPTION: Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/

View File

@ -29,8 +29,8 @@
</option>
<option>
<name>Variant</name>
<version>19</version>
<state>37</state>
<version>20</version>
<state>38</state>
</option>
<option>
<name>GEndianMode</name>
@ -87,7 +87,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>6.30.3.53229</state>
<state>6.50.5.4846</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@ -137,13 +137,13 @@
</option>
<option>
<name>GFPUCoreSlave</name>
<version>19</version>
<state>37</state>
<version>20</version>
<state>38</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>19</version>
<state>37</state>
<version>20</version>
<state>38</state>
</option>
<option>
<name>OGUseCmsis</name>
@ -162,6 +162,10 @@
<version>28</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CCOptimizationNoSizeConstraints</name>
<state>0</state>
</option>
<option>
<name>CCDefines</name>
<state>EFM32G880F128</state>
@ -613,7 +617,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>14</version>
<version>15</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -781,10 +785,6 @@
<name>CrcAlign</name>
<state>1</state>
</option>
<option>
<name>CrcAlgo</name>
<state>1</state>
</option>
<option>
<name>CrcPoly</name>
<state>0x11021</state>
@ -887,6 +887,16 @@
<name>IlinkStackCallGraphFile</name>
<state></state>
</option>
<option>
<name>CrcAlgorithm</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CrcUnitSize</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -943,7 +953,7 @@
</option>
<option>
<name>Variant</name>
<version>19</version>
<version>20</version>
<state>0</state>
</option>
<option>
@ -1051,12 +1061,12 @@
</option>
<option>
<name>GFPUCoreSlave</name>
<version>19</version>
<version>20</version>
<state>0</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>19</version>
<version>20</version>
<state>0</state>
</option>
<option>
@ -1076,6 +1086,10 @@
<version>28</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>CCOptimizationNoSizeConstraints</name>
<state>0</state>
</option>
<option>
<name>CCDefines</name>
<state>NDEBUG</state>
@ -1519,7 +1533,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>14</version>
<version>15</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1687,10 +1701,6 @@
<name>CrcAlign</name>
<state>1</state>
</option>
<option>
<name>CrcAlgo</name>
<state>1</state>
</option>
<option>
<name>CrcPoly</name>
<state>0x11021</state>
@ -1793,6 +1803,16 @@
<name>IlinkStackCallGraphFile</name>
<state></state>
</option>
<option>
<name>CrcAlgorithm</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CrcUnitSize</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<settings>

View File

@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
IAR Embedded Workbench for ARM v6.30 was used as the editor during the development of this software program. This directory contains
IAR Embedded Workbench for ARM v6.50 was used as the editor during the development of this software program. This directory contains
the Embedded Workbench project and worksapce files. More info is available at: http://www.iar.com/

View File

@ -2,14 +2,23 @@
@REM C-SPY Debugger, as an aid to preparing a command line for running
@REM the cspybat command line utility using the appropriate settings.
@REM
@REM You can launch cspybat by typing the name of this batch file followed
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
@REM Note that this file is generated every time a new debug session
@REM is initialized, so you may want to move or rename the file before
@REM making changes.
@REM
@REM You can launch cspybat by typing the name of this batch file followed
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
@REM
@REM Read about available command line parameters in the C-SPY Debugging
@REM Guide. Hints about additional command line parameters that may be
@REM useful in specific cases:
@REM --download_only Downloads a code image without starting a debug
@REM session afterwards.
@REM --silent Omits the sign-on message.
@REM --timeout Limits the maximum allowed execution time.
@REM
"C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\common\bin\cspybat" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\bin\armproc.dll" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\bin\armjlink.dll" %1 --plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\bin\armbat.dll" --flash_loader "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\config\flashloader\EnergyMicro\FlashEFM32.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\CONFIG\debugger\EnergyMicro\EFM32G880F128.ddf" "--drv_verify_download" "--semihosting" "--device=EFM32G880F128" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=72000000,0,2000000"
"C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armjlink.dll" %1 --plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --macro "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\EnergyMicro\Trace_EFM32.dmac" --flash_loader "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\EnergyMicro\FlashEFM32.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\EnergyMicro\EFM32G880F128.ddf" "--drv_verify_download" "--semihosting" "--device=EFM32G880F128" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=72000000,0,2000000"

View File

@ -1,5 +1,97 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Project/>
<Project>
<Desktop>
<Static>
<Debug-Log>
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1861</ColumnWidth1></Debug-Log>
<Build>
<ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1395</ColumnWidth1><ColumnWidth2>372</ColumnWidth2><ColumnWidth3>93</ColumnWidth3></Build>
<Workspace>
<ColumnWidths>
<Column0>124</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<col-names>
<item>Disassembly</item><item>_I0</item></col-names>
<col-widths>
<item>500</item><item>20</item></col-widths>
<DisasmHistory/>
<ShowCodeCoverage>1</ShowCodeCoverage><ShowInstrProfiling>1</ShowInstrProfiling></Disassembly>
</Static>
<Windows>
<Wnd0>
<Tabs>
<Tab>
<Identity>TabID-15722-3606</Identity>
<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
<Session/>
</Tab>
<Tab>
<Identity>TabID-15200-3615</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
<Session/>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd0><Wnd1>
<Tabs>
<Tab>
<Identity>TabID-26471-3609</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>efm32G880</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd1><Wnd2>
<Tabs>
<Tab>
<Identity>TabID-4451-3612</Identity>
<TabName>Disassembly</TabName>
<Factory>Disassembly</Factory>
<Session/>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd2></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>36</YPos2><SelStart2>2963</SelStart2><SelEnd2>2963</SelEnd2></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\..\..\Source\ARMCM3_EFM32\timer.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\..\..\..\Source\ARMCM3_EFM32\timer.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-02c0d7a8><key>iaridepm.enu1</key></Toolbar-02c0d7a8></Sizes></Row0><Row1><Sizes><Toolbar-03430168><key>debuggergui.enu1</key></Toolbar-03430168></Sizes></Row1><Row2><Sizes><Toolbar-03430230><key>armjlink.enu1</key></Toolbar-03430230></Sizes></Row2></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>717</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>104167</sizeHorzCX><sizeHorzCY>198413</sizeHorzCY><sizeVertCX>104167</sizeVertCX><sizeVertCY>713294</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>717</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>104167</sizeHorzCX><sizeHorzCY>198413</sizeHorzCY><sizeVertCX>104167</sizeVertCX><sizeVertCY>713294</sizeVertCY></Rect></Wnd2></Sizes></Row0></Right><Bottom><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>200</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>198413</sizeHorzCY><sizeVertCX>104167</sizeVertCX><sizeVertCY>198413</sizeVertCY></Rect></Wnd0></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Project>

View File

@ -10,6 +10,91 @@ LimitSize=0
ByteLimit=50
[Breakpoints]
Count=0
[DebugChecksum]
Checksum=-1802937773
[Exceptions]
StopOnUncaught=_ 0
StopOnThrow=_ 0
[CallStack]
ShowArgs=0
[Disassembly]
MixedMode=1
[JLinkDriver]
CStepIntDis=_ 0
[SWOTraceHWSettings]
OverrideDefaultClocks=0
CpuClock=72000000
ClockAutoDetect=0
ClockWanted=2000000
JtagSpeed=2000000
Prescaler=36
TimeStampPrescIndex=0
TimeStampPrescData=0
PcSampCYCTAP=1
PcSampPOSTCNT=15
PcSampIndex=0
DataLogMode=0
ITMportsEnable=0
ITMportsTermIO=0
ITMportsLogFile=0
ITMlogFile=$PROJ_DIR$\ITM.log
[CallStackLog]
Enabled=0
[DriverProfiling]
Enabled=0
Mode=3
Graph=0
Symbiont=0
Exclusions=
[RecentFlashDownload]
Path=C:\Work\software\OpenBLT\Target\Demo\ARMCM3_EFM32_Olimex_EM32G880F128STK_GCC\Boot\bin\openbtl_olimex_efm32g880.bin
[DataLog]
LogEnabled=0
SumEnabled=0
GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=1
[EventLog]
LogEnabled=0
SumEnabled=0
GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=1
Title0=Ch0
Symbol0=0 4 1
Title1=Ch1
Symbol1=0 4 1
Title2=Ch2
Symbol2=0 4 1
Title3=Ch3
Symbol3=0 4 1
SumSortOrder=0
[InterruptLog]
LogEnabled=0
SumEnabled=0
GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=1
SumSortOrder=0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[Trace2]
Enabled=0
ShowSource=0
[SWOTraceWindow]
PcSampling=0
InterruptLogs=0
ForcedTimeStamps=0
EventCPI=0
EventEXC=0
EventFOLD=0
EventLSU=0
EventSLEEP=0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[Disassemble mode]
mode=0
[Breakpoints2]

View File

@ -25,7 +25,7 @@
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View File

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View File

@ -29,8 +29,8 @@
</option>
<option>
<name>Variant</name>
<version>19</version>
<state>37</state>
<version>20</version>
<state>38</state>
</option>
<option>
<name>GEndianMode</name>
@ -87,7 +87,7 @@
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>6.30.3.53229</state>
<state>6.50.5.4846</state>
</option>
<option>
<name>GeneralEnableMisra</name>
@ -137,13 +137,13 @@
</option>
<option>
<name>GFPUCoreSlave</name>
<version>19</version>
<state>37</state>
<version>20</version>
<state>38</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>19</version>
<state>37</state>
<version>20</version>
<state>38</state>
</option>
<option>
<name>OGUseCmsis</name>
@ -162,6 +162,10 @@
<version>28</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CCOptimizationNoSizeConstraints</name>
<state>0</state>
</option>
<option>
<name>CCDefines</name>
<state>EFM32G880F128</state>
@ -611,7 +615,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>14</version>
<version>15</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -779,10 +783,6 @@
<name>CrcAlign</name>
<state>1</state>
</option>
<option>
<name>CrcAlgo</name>
<state>1</state>
</option>
<option>
<name>CrcPoly</name>
<state>0x11021</state>
@ -885,6 +885,16 @@
<name>IlinkStackCallGraphFile</name>
<state></state>
</option>
<option>
<name>CrcAlgorithm</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CrcUnitSize</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -941,7 +951,7 @@
</option>
<option>
<name>Variant</name>
<version>19</version>
<version>20</version>
<state>0</state>
</option>
<option>
@ -1049,12 +1059,12 @@
</option>
<option>
<name>GFPUCoreSlave</name>
<version>19</version>
<version>20</version>
<state>0</state>
</option>
<option>
<name>GBECoreSlave</name>
<version>19</version>
<version>20</version>
<state>0</state>
</option>
<option>
@ -1074,6 +1084,10 @@
<version>28</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
<name>CCOptimizationNoSizeConstraints</name>
<state>0</state>
</option>
<option>
<name>CCDefines</name>
<state>NDEBUG</state>
@ -1517,7 +1531,7 @@
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>14</version>
<version>15</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1685,10 +1699,6 @@
<name>CrcAlign</name>
<state>1</state>
</option>
<option>
<name>CrcAlgo</name>
<state>1</state>
</option>
<option>
<name>CrcPoly</name>
<state>0x11021</state>
@ -1791,6 +1801,16 @@
<name>IlinkStackCallGraphFile</name>
<state></state>
</option>
<option>
<name>CrcAlgorithm</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CrcUnitSize</name>
<version>0</version>
<state>0</state>
</option>
</data>
</settings>
<settings>

View File

@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
IAR Embedded Workbench for ARM v6.30 was used as the editor during the development of this software program. This directory contains
IAR Embedded Workbench for ARM v6.50 was used as the editor during the development of this software program. This directory contains
the Embedded Workbench project and worksapce files. More info is available at: http://www.iar.com/

View File

@ -2,14 +2,23 @@
@REM C-SPY Debugger, as an aid to preparing a command line for running
@REM the cspybat command line utility using the appropriate settings.
@REM
@REM You can launch cspybat by typing the name of this batch file followed
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
@REM Note that this file is generated every time a new debug session
@REM is initialized, so you may want to move or rename the file before
@REM making changes.
@REM
@REM You can launch cspybat by typing the name of this batch file followed
@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
@REM
@REM Read about available command line parameters in the C-SPY Debugging
@REM Guide. Hints about additional command line parameters that may be
@REM useful in specific cases:
@REM --download_only Downloads a code image without starting a debug
@REM session afterwards.
@REM --silent Omits the sign-on message.
@REM --timeout Limits the maximum allowed execution time.
@REM
"C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\common\bin\cspybat" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\bin\armproc.dll" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\bin\armsim2.dll" %1 --plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\bin\armbat.dll" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.0 Kickstart\arm\CONFIG\debugger\EnergyMicro\EFM32G880F128.ddf" "--semihosting" "--device=EFM32G880F128"
"C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armsim2.dll" %1 --plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --macro "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\EnergyMicro\Trace_EFM32.dmac" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\EnergyMicro\EFM32G880F128.ddf" "--semihosting" "--device=EFM32G880F128"

View File

@ -15,6 +15,12 @@ GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=1
SumSortOrder=0
[DataLog]
LogEnabled=0
SumEnabled=0
GraphEnabled=0
ShowTimeLog=1
ShowTimeSum=1
[Disassemble mode]
mode=0
[Breakpoints2]

View File

@ -12,7 +12,7 @@
<Column0>289</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
<Column0>362</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build>
@ -24,7 +24,7 @@
<Windows>
<Wnd2>
<Wnd0>
<Tabs>
<Tab>
<Identity>TabID-15953-11523</Identity>
@ -36,7 +36,7 @@
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd2><Wnd3>
<SelectedTab>0</SelectedTab></Wnd0><Wnd1>
<Tabs>
<Tab>
<Identity>TabID-26827-12343</Identity>
@ -46,20 +46,20 @@
</Tab>
<Tab><Identity>TabID-26138-18087</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs>
<SelectedTab>0</SelectedTab></Wnd3></Windows>
<SelectedTab>0</SelectedTab></Wnd1></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\lib\CMSIS\CM3\CoreSupport\core_cm3.c</Filename><XPos>0</XPos><YPos>128</YPos><SelStart>4450</SelStart><SelEnd>4450</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\vectors.c</Filename><XPos>0</XPos><YPos>105</YPos><SelStart>7856</SelStart><SelEnd>7856</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\main.c</Filename><XPos>0</XPos><YPos>32</YPos><SelStart>2687</SelStart><SelEnd>2687</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\led.c</Filename><XPos>0</XPos><YPos>32</YPos><SelStart>2220</SelStart><SelEnd>2220</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\boot.c</Filename><XPos>0</XPos><YPos>31</YPos><SelStart>2430</SelStart><SelEnd>2430</SelEnd></Tab><ActiveTab>4</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\timer.c</Filename><XPos>0</XPos><YPos>43</YPos><SelStart>3070</SelStart><SelEnd>3081</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\lib\CMSIS\CM3\CoreSupport\core_cm3.h</Filename><XPos>0</XPos><YPos>1121</YPos><SelStart>68737</SelStart><SelEnd>68750</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\timer.h</Filename><XPos>0</XPos><YPos>32</YPos><SelStart>1997</SelStart><SelEnd>1997</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\lib\CMSIS\CM3\CoreSupport\core_cm3.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\vectors.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\led.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\boot.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><ActiveTab>4</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\timer.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\lib\CMSIS\CM3\CoreSupport\core_cm3.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\..\timer.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>0</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-00837930><key>iaridepm.enu1</key></Toolbar-00837930></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>587</Bottom><Right>363</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>125000</sizeHorzCX><sizeHorzCY>240964</sizeHorzCY><sizeVertCX>228125</sizeVertCX><sizeVertCY>709639</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>200</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>240964</sizeHorzCY><sizeVertCX>125000</sizeVertCX><sizeVertCY>240964</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
<Top><Row0><Sizes><Toolbar-02a1d7a8><key>iaridepm.enu1</key></Toolbar-02a1d7a8></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>722</Bottom><Right>436</Right><x>-2</x><y>-2</y><xscreen>240</xscreen><yscreen>243</yscreen><sizeHorzCX>125000</sizeHorzCX><sizeHorzCY>241071</sizeHorzCY><sizeVertCX>228125</sizeVertCX><sizeVertCY>718254</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>241</Bottom><Right>1922</Right><x>-2</x><y>-2</y><xscreen>1924</xscreen><yscreen>243</yscreen><sizeHorzCX>1002083</sizeHorzCX><sizeHorzCY>241071</sizeHorzCY><sizeVertCX>125000</sizeVertCX><sizeVertCY>241071</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>

View File

@ -41,10 +41,15 @@
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
* big endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
#define BOOT_CPU_XTAL_SPEED_KHZ (8000)
#define BOOT_CPU_SYSTEM_SPEED_KHZ (50000)
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
#define BOOT_CPU_USER_PROGRAM_START_HOOK (0)
/****************************************************************************************
@ -65,6 +70,37 @@
#define BOOT_COM_UART_CHANNEL_INDEX (0)
/****************************************************************************************
* F I L E S Y S T E M I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The file system interface is selected by setting the BOOT_FILE_SYS_ENABLE configurable
* to 1. This enables support for firmware updates from a file stored on a locally
* attached file system such as an SD-card. Note that this interface can be enabled
* together with one of the remote communication interfaces such as UART, CAN or USB.
*
* Set BOOT_FILE_LOGGING_ENABLE to 1 if you would like log messages to be created during
* a firmware update. The hook function FileFirmwareUpdateLogHook() will be called each
* time a new string formatted log entry is available. This could be used during testing
* by outputting the string on UART or to create a log file on the file system itself.
*
* Set BOOT_FILE_ERROR_HOOK_ENABLE to 1 if you would like to be informed in case an error
* occurs during the firmware update. This could for example be used to turn on an error
* LED to inform the user that something went wrong. Inspecting the log messages provides
* additional information on the error cause.
*
* Set BOOT_FILE_STARTED_HOOK_ENABLE to 1 if you would like to be informed when a new
* firmware update is started by the bootloader.
*
* Set BOOT_FILE_COMPLETED_HOOK_ENABLE to 1 if you would like to be informed when a
* firmware update is completed by the bootloader.
*/
#define BOOT_FILE_SYS_ENABLE (1)
#define BOOT_FILE_LOGGING_ENABLE (1)
#define BOOT_FILE_ERROR_HOOK_ENABLE (1)
#define BOOT_FILE_STARTED_HOOK_ENABLE (1)
#define BOOT_FILE_COMPLETED_HOOK_ENABLE (1)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/

View File

@ -33,6 +33,11 @@
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#if (BOOT_FILE_LOGGING_ENABLE > 0)
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/uartlib.h"
#endif
/****************************************************************************************
@ -67,6 +72,30 @@ blt_bool BackDoorEntryHook(void)
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/****************************************************************************************
** NAME: CpuUserProgramStartHook
** PARAMETER: none
** RETURN VALUE: BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
** DESCRIPTION: Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
@ -176,4 +205,180 @@ void CopServiceHook(void)
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
/****************************************************************************************
* F I L E S Y S T E M I N T E R F A C E H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_FILE_SYS_ENABLE > 0)
/****************************************************************************************
* Constant data declarations
****************************************************************************************/
static const blt_char firmwareFilename[] = "/demoprog_ek_lm3s6965.srec";
/****************************************************************************************
* Local data declarations
****************************************************************************************/
#if (BOOT_FILE_LOGGING_ENABLE > 0)
static struct
{
FIL handle;
blt_bool canUse;
} logfile;
#endif
/****************************************************************************************
** NAME: FileIsFirmwareUpdateRequestedHook
** PARAMETER: none
** RETURN VALUE: BLT_TRUE if a firmware update is requested, BLT_FALSE otherwise.
** DESCRIPTION: Callback that gets called continuously when the bootloader is idle to
** check whether a firmware update from local file storage should be
** started. This could for example be when a switch is pressed, when a
** certain file is found on the local file storage, etc.
**
****************************************************************************************/
blt_bool FileIsFirmwareUpdateRequestedHook(void)
{
FILINFO fileInfoObject = { 0 }; /* needs to be zeroed according to f_stat docs */;
/* Current example implementation looks for a predetermined firmware file on the
* SD-card. If the SD-card is accessible and the firmware file was found the firmware
* update is started. When successfully completed, the firmware file is deleted.
* During the firmware update, progress information is written to a file called
* bootlog.txt and additionally outputted on UART @57600 bps for debugging purposes.
*/
/* check if firmware file is present and SD-card is accessible */
if (f_stat(firmwareFilename, &fileInfoObject) == FR_OK)
{
/* check if the filesize is valid and that it is not a directory */
if ( (fileInfoObject.fsize > 0) && (!(fileInfoObject.fattrib & AM_DIR)) )
{
/* all conditions are met to start a firmware update from local file storage */
return BLT_TRUE;
}
}
/* still here so no firmware update request is pending */
return BLT_FALSE;
} /*** end of FileIsFirmwareUpdateRequestedHook ***/
/****************************************************************************************
** NAME: FileGetFirmwareFilenameHook
** PARAMETER: none
** RETURN VALUE: valid firmware filename with full path or BLT_NULL.
** DESCRIPTION: Callback to obtain the filename of the firmware file that should be
** used during the firmware update from the local file storage. This
** hook function is called at the beginning of the firmware update from
** local storage sequence.
**
****************************************************************************************/
const blt_char *FileGetFirmwareFilenameHook(void)
{
return firmwareFilename;
} /*** end of FileGetFirmwareFilenameHook ***/
#if (BOOT_FILE_STARTED_HOOK_ENABLE > 0)
/****************************************************************************************
** NAME: FileFirmwareUpdateStartedHook
** PARAMETER: none
** RETURN VALUE: none
** DESCRIPTION: Callback that gets called to inform the application that a firmware
** update from local storage just started.
**
****************************************************************************************/
void FileFirmwareUpdateStartedHook(void)
{
#if (BOOT_FILE_LOGGING_ENABLE > 0)
/* create/overwrite the logfile */
logfile.canUse = BLT_FALSE;
if (f_open(&logfile.handle, "/bootlog.txt", FA_CREATE_ALWAYS | FA_WRITE) == FR_OK)
{
logfile.canUse = BLT_TRUE;
}
#endif
} /*** end of FileFirmwareUpdateStartedHook ***/
#endif /* BOOT_FILE_STARTED_HOOK_ENABLE > 0 */
#if (BOOT_FILE_COMPLETED_HOOK_ENABLE > 0)
/****************************************************************************************
** NAME: FileFirmwareUpdateCompletedHook
** PARAMETER: none
** RETURN VALUE: none
** DESCRIPTION: Callback that gets called to inform the application that a firmware
** update was successfully completed.
**
****************************************************************************************/
void FileFirmwareUpdateCompletedHook(void)
{
#if (BOOT_FILE_LOGGING_ENABLE > 0)
/* close the log file */
if (logfile.canUse == BLT_TRUE)
{
f_close(&logfile.handle);
}
/* wait for all logging related transmission to complete */
while (UARTBusy(UART0_BASE) == true);
#endif
/* now delete the firmware file from the disk since the update was successful */
f_unlink(firmwareFilename);
} /*** end of FileFirmwareUpdateCompletedHook ***/
#endif /* BOOT_FILE_COMPLETED_HOOK_ENABLE > 0 */
#if (BOOT_FILE_ERROR_HOOK_ENABLE > 0)
/****************************************************************************************
** NAME: FileFirmwareUpdateErrorHook
** PARAMETER: error_code additional information on the error that occurred.
** RETURN VALUE: none
** DESCRIPTION: Callback that gets called in case an error occurred during a firmware
** update. Refer to <file.h> for a list of available error codes.
**
****************************************************************************************/
void FileFirmwareUpdateErrorHook(blt_int8u error_code)
{
} /*** end of FileFirmwareUpdateErrorHook ***/
#endif /* BOOT_FILE_ERROR_HOOK_ENABLE > 0 */
#if (BOOT_FILE_LOGGING_ENABLE > 0)
/****************************************************************************************
** NAME: FileFirmwareUpdateLogHook
** PARAMETER: info_string pointer to a character array with the log entry info.
** RETURN VALUE: none
** DESCRIPTION: Callback that gets called each time new log information becomes
** available during a firmware update.
**
****************************************************************************************/
void FileFirmwareUpdateLogHook(blt_char *info_string)
{
/* write the string to the log file */
if (logfile.canUse == BLT_TRUE)
{
if (f_puts(info_string, &logfile.handle) < 0)
{
logfile.canUse = BLT_FALSE;
f_close(&logfile.handle);
}
}
/* echo all characters in the string on UART */
while(*info_string != '\0')
{
/* write character to transmit holding register */
UARTCharPutNonBlocking(UART0_BASE, *info_string);
/* wait for tx holding register to be empty */
while(UARTSpaceAvail(UART0_BASE) == false);
/* point to the next character in the string */
info_string++;
}
} /*** end of FileFirmwareUpdateLogHook ***/
#endif /* BOOT_FILE_LOGGING_ENABLE > 0 */
#endif /* BOOT_FILE_SYS_ENABLE > 0 */
/*********************************** end of hooks.c ************************************/

View File

@ -1,14 +1,14 @@
<!DOCTYPE CrossStudio_Project_File>
<solution Name="lm3s6965_crossworks" target="8" version="2">
<project Name="openbtl_ek_lm3s6965">
<configuration Name="Common" Placement="Flash" Target="LM3S6965" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_linker_heap_size="128" arm_linker_process_stack_size="0" arm_linker_stack_size="128" arm_simulator_memory_simulation_filename="$(TargetsDir)/LM3S/LM3SSimulatorMemory.dll" arm_simulator_memory_simulation_parameter="0x40000;0x10000" arm_target_debug_interface_type="ADIv5" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" arm_use_gcc_libraries="Yes" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_preprocessor_definitions="gcc" c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../lib;$(ProjectDir)/../lib/inc;$(ProjectDir)/../lib/driverlib;$(ProjectDir)/../../../../Source;$(ProjectDir)/../../../../Source/ARMCM3_LM3S;$(ProjectDir)/../../../../Source/ARMCM3_LM3S/Crossworks" gcc_entry_point="reset_handler" gcc_optimization_level="Optimize For Size" link_include_standard_libraries="No" linker_additional_files="" linker_keep_symbols="_vectors;EntryFromProg" linker_memory_map_file="$(TargetsDir)/LM3S/LM3S6965_MemoryMap.xml" linker_output_format="srec" linker_printf_width_precision_supported="No" linker_scanf_fmt_level="int" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/LM3S/propertyGroups.xml" target_get_partname_script="GetPartName()" target_reset_script="Reset()"/>
<configuration Name="Common" Placement="Flash" Target="LM3S6965" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_library_optimization="Small" arm_linker_heap_size="128" arm_linker_process_stack_size="0" arm_linker_stack_size="128" arm_simulator_memory_simulation_filename="$(TargetsDir)/LM3S/LM3SSimulatorMemory.dll" arm_simulator_memory_simulation_parameter="0x40000;0x10000" arm_target_debug_interface_type="ADIv5" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" arm_use_gcc_libraries="Yes" build_intermediate_directory="$(Configuration)/../../obj" build_output_directory="$(ProjectDir)/../bin" c_preprocessor_definitions="gcc" c_user_include_directories="$(ProjectDir)/..;$(ProjectDir)/../lib;$(ProjectDir)/../lib/inc;$(ProjectDir)/../lib/fatfs;$(ProjectDir)/../lib/driverlib;$(ProjectDir)/../../../../Source;$(ProjectDir)/../../../../Source/fatfs/src;$(ProjectDir)/../../../../Source/ARMCM3_LM3S;$(ProjectDir)/../../../../Source/ARMCM3_LM3S/Crossworks" gcc_entry_point="reset_handler" gcc_optimization_level="Optimize For Size" link_include_standard_libraries="Yes" linker_DebugIO_enabled="No" linker_additional_files="" linker_keep_symbols="_vectors;EntryFromProg" linker_memory_map_file="$(TargetsDir)/LM3S/LM3S6965_MemoryMap.xml" linker_output_format="srec" linker_printf_enabled="No" linker_printf_width_precision_supported="No" linker_scanf_enabled="No" linker_scanf_fmt_level="int" linker_section_placement_file="$(StudioDir)/targets/Cortex_M/flash_placement.xml" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/LM3S/propertyGroups.xml" target_get_partname_script="GetPartName()" target_reset_script="Reset()"/>
<configuration Name="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/LM3S/Release/Loader.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" target_reset_script="FLASHReset()"/>
<folder Name="Source Files">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<folder Name="Demo">
<folder Name="Boot">
<folder Name="lib">
<folder Name="inc">
<folder Name="inc" file_name="">
<file file_name="../lib/inc/hw_ints.h"/>
<file file_name="../lib/inc/hw_nvic.h"/>
<file file_name="../lib/inc/hw_sysctl.h"/>
@ -17,8 +17,9 @@
<file file_name="../lib/inc/hw_gpio.h"/>
<file file_name="../lib/inc/hw_uart.h"/>
<file file_name="../lib/inc/hw_memmap.h"/>
<file file_name="../lib/inc/hw_ssi.h"/>
</folder>
<folder Name="driverlib">
<folder Name="driverlib" file_name="">
<file file_name="../lib/driverlib/sysctl.c"/>
<file file_name="../lib/driverlib/sysctl.h"/>
<file file_name="../lib/driverlib/debug.h"/>
@ -32,6 +33,13 @@
<file file_name="../lib/driverlib/flashlib.h"/>
<file file_name="../lib/driverlib/uartlib.c"/>
<file file_name="../lib/driverlib/uartlib.h"/>
<file file_name="../lib/driverlib/pin_map.h"/>
<file file_name="../lib/driverlib/ssi.c"/>
<file file_name="../lib/driverlib/ssi.h"/>
</folder>
<folder Name="fatfs" file_name="">
<file file_name="../lib/fatfs/ffconf.h"/>
<file file_name="../lib/fatfs/mmc.c"/>
</folder>
</folder>
<file file_name="../config.h"/>
@ -39,7 +47,7 @@
<file file_name="../main.c"/>
</folder>
</folder>
<folder Name="Source">
<folder Name="Source" file_name="">
<folder Name="ARMCM3_LM3S">
<folder Name="Crossworks">
<file file_name="../../../../Source/ARMCM3_LM3S/Crossworks/cstart.s"/>
@ -70,6 +78,15 @@
<file file_name="../../../../Source/plausibility.h"/>
<file file_name="../../../../Source/xcp.c"/>
<file file_name="../../../../Source/xcp.h"/>
<folder Name="fatfs" file_name="">
<file file_name="../../../../Source/fatfs/src/diskio.h"/>
<file file_name="../../../../Source/fatfs/src/ff.c"/>
<file file_name="../../../../Source/fatfs/src/ff.h"/>
<file file_name="../../../../Source/fatfs/src/integer.h"/>
<file file_name="../../../../Source/fatfs/src/option/unicode.c"/>
</folder>
<file file_name="../../../../Source/file.c"/>
<file file_name="../../../../Source/file.h"/>
</folder>
</folder>
<folder Name="System Files">

View File

@ -2,23 +2,18 @@
<session>
<Bookmarks/>
<Breakpoints/>
<ETMWindow>
<ETMRegister number="0" value="800" />
<ETMRegister number="8" value="6f" />
<ETMRegister number="9" value="1000000" />
</ETMWindow>
<ExecutionCountWindow/>
<ExecutionProfileWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_ek_lm3s6965" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_ek_lm3s6965" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_ek_lm3s6965" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" name="openbtl_ek_lm3s6965" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="lm3s6965_crossworks" name="unnamed" />
@ -26,19 +21,18 @@
<ProjectSessionItem path="lm3s6965_crossworks;openbtl_ek_lm3s6965;Source Files" name="unnamed" />
<ProjectSessionItem path="lm3s6965_crossworks;openbtl_ek_lm3s6965;Source Files;Source" name="unnamed" />
<ProjectSessionItem path="lm3s6965_crossworks;openbtl_ek_lm3s6965;Source Files;Source;ARMCM3_LM3S" name="unnamed" />
<ProjectSessionItem path="lm3s6965_crossworks;openbtl_ek_lm3s6965;Source Files;Source;ARMCM3_LM3S;Crossworks" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_ek_lm3s6965" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_ek_lm3s6965" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_ek_lm3s6965" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
<RegisterWindow openNodes="" binaryNodes="" hiddenNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" name="openbtl_ek_lm3s6965" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
@ -57,8 +51,8 @@
<Watches active="0" update="Never" />
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_LM3S_EK_LM3S6965_Crossworks\Boot\main.c" y="72" path="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_LM3S_EK_LM3S6965_Crossworks\Boot\main.c" left="0" selected="0" name="unnamed" top="72" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_LM3S\Crossworks\cstart.s" y="87" path="D:\usr\feaser\software\OpenBLT\Target\Source\ARMCM3_LM3S\Crossworks\cstart.s" left="0" selected="1" name="unnamed" top="74" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_LM3S_EK_LM3S6965_Crossworks\Boot\main.c" y="61" path="C:\Work\software\OpenBLT\Target\Demo\ARMCM3_LM3S_EK_LM3S6965_Crossworks\Boot\main.c" left="0" selected="0" name="unnamed" top="37" />
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\Work\software\OpenBLT\Target\Source\ARMCM3_LM3S\cpu.c" y="78" path="C:\Work\software\OpenBLT\Target\Source\ARMCM3_LM3S\cpu.c" left="0" selected="1" name="unnamed" top="45" />
</Files>
<ARMCrossStudioWindow activeProject="openbtl_ek_lm3s6965" autoConnectTarget="Texas Instruments ICDI" debugSearchFileMap="" fileDialogInitialDirectory="D:\usr\feaser\software\OpenBLT\Target\Demo\ARMCM3_LM3S_EK_LM3S6965_Crossworks\Boot\lib\driverlib" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Debug" />
<ARMCrossStudioWindow activeProject="openbtl_ek_lm3s6965" autoConnectTarget="Texas Instruments ICDI" debugSearchFileMap="" fileDialogInitialDirectory="C:\Work\software\OpenBLT\Target\Source" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Debug" />
</session>

View File

@ -1,4 +1,4 @@
Integrated Development Environment
----------------------------------
Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
Rowleys CrossWorks (version 2.3.1) was used as the editor during the development of this software program. This directory contains
the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/

View File

@ -3,23 +3,38 @@
// cpu.c - Instruction wrappers for special CPU instructions needed by the
// drivers.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

View File

@ -2,23 +2,38 @@
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

View File

@ -2,23 +2,38 @@
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

View File

@ -2,23 +2,38 @@
//
// flash.c - Driver for programming the on-chip flash.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -48,7 +63,11 @@ static const unsigned long g_pulFMPPERegs[] =
FLASH_FMPPE,
FLASH_FMPPE1,
FLASH_FMPPE2,
FLASH_FMPPE3
FLASH_FMPPE3,
FLASH_FMPPE4,
FLASH_FMPPE5,
FLASH_FMPPE6,
FLASH_FMPPE7
};
//*****************************************************************************
@ -62,7 +81,11 @@ static const unsigned long g_pulFMPRERegs[] =
FLASH_FMPRE,
FLASH_FMPRE1,
FLASH_FMPRE2,
FLASH_FMPRE3
FLASH_FMPRE3,
FLASH_FMPRE4,
FLASH_FMPRE5,
FLASH_FMPRE6,
FLASH_FMPRE7
};
//*****************************************************************************
@ -70,7 +93,8 @@ static const unsigned long g_pulFMPRERegs[] =
//! Gets the number of processor clocks per micro-second.
//!
//! This function returns the number of clocks per micro-second, as presently
//! known by the flash controller.
//! known by the flash controller. This function is only valid on Sandstorm-
//! and Fury-class devices.
//!
//! \return Returns the number of processor clocks per micro-second.
//
@ -93,7 +117,7 @@ FlashUsecGet(void)
//! This function is used to tell the flash controller the number of processor
//! clocks per micro-second. This value must be programmed correctly or the
//! flash most likely will not program correctly; it has no affect on reading
//! flash.
//! flash. This function is only valid on Sandstorm- and Fury-class devices.
//!
//! \return None.
//
@ -113,11 +137,11 @@ FlashUsecSet(unsigned long ulClocks)
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 1 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//! This function erases a 1-kB block of the on-chip flash. After erasing,
//! the block is filled with 0xFF bytes. Read-only and execute-only blocks
//! cannot be erased.
//!
//! This function will not return until the block has been erased.
//! This function does not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
@ -132,9 +156,10 @@ FlashClear(unsigned long ulAddress)
ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
//
// Clear the flash access interrupt.
// Clear the flash access and error interrupts.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_ERMISC);
//
// Erase the block.
@ -150,9 +175,10 @@ FlashClear(unsigned long ulAddress)
}
//
// Return an error if an access violation occurred.
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_ERRIS))
{
return(-1);
}
@ -173,19 +199,16 @@ FlashClear(unsigned long ulAddress)
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Programming each location consists of the result of an AND operation
//! of the new data and the existing data; in other words bits that contain
//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
//! to 1. Therefore, a word can be programmed multiple times as long as these
//! rules are followed; if a program operation attempts to change a 0 bit to
//! a 1 bit, that bit will not have its value changed.
//! This function programs a sequence of words into the on-chip flash.
//! Each word in a page of flash can only be programmed one time between an
//! erase of that page; programming a word multiple times results in an
//! unpredictable value in that word of flash.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! Because the flash is programmed one word at a time, the starting address
//! and byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//! This function does not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
@ -201,9 +224,10 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
ASSERT(!(ulCount & 3));
//
// Clear the flash access interrupt.
// Clear the flash access and error interrupts.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
@ -280,7 +304,8 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS))
{
return(-1);
}
@ -297,7 +322,7 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function will get the current protection for the specified 2 kB block
//! This function gets the current protection for the specified 2-kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
@ -390,17 +415,17 @@ FlashProtectGet(unsigned long ulAddress)
//! \param eProtect is the protection to be applied to the block. Can be one
//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
//!
//! This function will set the protection for the specified 2 kB block of
//! flash. Blocks which are read/write can be made read-only or execute-only.
//! Blocks which are read-only can be made execute-only. Blocks which are
//! This function sets the protection for the specified 2-kB block of
//! flash. Blocks that are read/write can be made read-only or execute-only.
//! Blocks that are read-only can be made execute-only. Blocks that are
//! execute-only cannot have their protection modified. Attempts to make the
//! block protection less stringent (that is, read-only to read/write) will
//! result in a failure (and be prevented by the hardware).
//! block protection less stringent (that is, read-only to read/write)
//! result in a failure (and are prevented by the hardware).
//!
//! Changes to the flash protection are maintained only until the next reset.
//! This allows the application to be executed in the desired flash protection
//! environment to check for inappropriate flash access (via the flash
//! interrupt). To make the flash protection permanent, use the
//! This protocol allows the application to be executed in the desired flash
//! protection environment to check for inappropriate flash access (via the
//! flash interrupt). To make the flash protection permanent, use the
//! FlashProtectSave() function.
//!
//! \return Returns 0 on success, or -1 if an invalid address or an invalid
@ -536,7 +561,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
{
ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
}
//
@ -555,11 +580,11 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
//
//! Saves the flash protection settings.
//!
//! This function will make the currently programmed flash protection settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change the flash protection.
//! This function makes the currently programmed flash protection settings
//! permanent. On some devices, this operation is non-reversible; a chip reset
//! or power cycle does not change the flash protection.
//!
//! This function will not return until the protection has been saved.
//! This function does not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@ -567,7 +592,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
long
FlashProtectSave(void)
{
int ulTemp, ulLimit;
unsigned long ulTemp, ulLimit;
//
// If running on a Sandstorm-class device, only trigger a save of the first
@ -604,8 +629,8 @@ FlashProtectSave(void)
//! \param pulUser0 is a pointer to the location to store USER Register 0.
//! \param pulUser1 is a pointer to the location to store USER Register 1.
//!
//! This function will read the contents of user registers (0 and 1), and
//! store them in the specified locations.
//! This function reads the contents of user registers (0 and 1), and
//! stores them in the specified locations.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@ -646,7 +671,7 @@ FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
//! \param ulUser0 is the value to store in USER Register 0.
//! \param ulUser1 is the value to store in USER Register 1.
//!
//! This function will set the contents of the user registers (0 and 1) to
//! This function sets the contents of the user registers (0 and 1) to
//! the specified values.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
@ -679,11 +704,11 @@ FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
//
//! Saves the user registers.
//!
//! This function will make the currently programmed user register settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change this setting.
//! This function makes the currently programmed user register settings
//! permanent. On some devices, this operation is non-reversible; a chip reset
//! or power cycle does not change this setting.
//!
//! This function will not return until the protection has been saved.
//! This function does not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@ -739,12 +764,12 @@ FlashUserSave(void)
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt will be
//! automatically enabled when the handler is registered.
//! This function sets the handler to be called when the flash interrupt
//! occurs. The flash controller can generate an interrupt when an invalid
//! flash access occurs, such as trying to program or erase a read-only block,
//! or trying to read from an execute-only block. It can also generate an
//! interrupt when a program or erase operation has completed. The interrupt
//! is automatically enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -770,9 +795,9 @@ FlashIntRegister(void (*pfnHandler)(void))
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//! This function clears the handler to be called when the flash interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -801,9 +826,9 @@ FlashIntUnregister(void)
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//! This function enables the indicated flash controller interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@ -824,9 +849,9 @@ FlashIntEnable(unsigned long ulIntFlags)
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//! This function disables the indicated flash controller interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@ -847,9 +872,9 @@ FlashIntDisable(unsigned long ulIntFlags)
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//! This function returns the interrupt status for the flash controller.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
@ -880,10 +905,10 @@ FlashIntStatus(tBoolean bMasked)
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//! no longer assert. This function must be called in the interrupt handler
//! to keep the interrupt from being triggered again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid

View File

@ -2,23 +2,38 @@
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -56,8 +71,13 @@ tFlashProtection;
// returned from FlashIntStatus().
//
//*****************************************************************************
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
//*****************************************************************************
//

View File

@ -2,23 +2,38 @@
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -71,7 +86,8 @@ extern "C"
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
//*****************************************************************************
//
@ -84,6 +100,7 @@ extern "C"
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
@ -94,620 +111,8 @@ extern "C"
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter.
//
//*****************************************************************************
//
// GPIO pin A0
//
#define GPIO_PA0_U0RX 0x00000001
#define GPIO_PA0_I2C1SCL 0x00000008
#define GPIO_PA0_U1RX 0x00000009
//
// GPIO pin A1
//
#define GPIO_PA1_U0TX 0x00000401
#define GPIO_PA1_I2C1SDA 0x00000408
#define GPIO_PA1_U1TX 0x00000409
//
// GPIO pin A2
//
#define GPIO_PA2_SSI0CLK 0x00000801
#define GPIO_PA2_PWM4 0x00000804
#define GPIO_PA2_I2S0RXSD 0x00000809
//
// GPIO pin A3
//
#define GPIO_PA3_SSI0FSS 0x00000c01
#define GPIO_PA3_PWM5 0x00000c04
#define GPIO_PA3_I2S0RXMCLK 0x00000c09
//
// GPIO pin A4
//
#define GPIO_PA4_SSI0RX 0x00001001
#define GPIO_PA4_PWM6 0x00001004
#define GPIO_PA4_CAN0RX 0x00001005
#define GPIO_PA4_I2S0TXSCK 0x00001009
//
// GPIO pin A5
//
#define GPIO_PA5_SSI0TX 0x00001401
#define GPIO_PA5_PWM7 0x00001404
#define GPIO_PA5_CAN0TX 0x00001405
#define GPIO_PA5_I2S0TXWS 0x00001409
//
// GPIO pin A6
//
#define GPIO_PA6_I2C1SCL 0x00001801
#define GPIO_PA6_CCP1 0x00001802
#define GPIO_PA6_PWM0 0x00001804
#define GPIO_PA6_PWM4 0x00001805
#define GPIO_PA6_CAN0RX 0x00001806
#define GPIO_PA6_USB0EPEN 0x00001808
#define GPIO_PA6_U1CTS 0x00001809
//
// GPIO pin A7
//
#define GPIO_PA7_I2C1SDA 0x00001c01
#define GPIO_PA7_CCP4 0x00001c02
#define GPIO_PA7_PWM1 0x00001c04
#define GPIO_PA7_PWM5 0x00001c05
#define GPIO_PA7_CAN0TX 0x00001c06
#define GPIO_PA7_CCP3 0x00001c07
#define GPIO_PA7_USB0PFLT 0x00001c08
#define GPIO_PA7_U1DCD 0x00001c09
//
// GPIO pin B0
//
#define GPIO_PB0_CCP0 0x00010001
#define GPIO_PB0_PWM2 0x00010002
#define GPIO_PB0_U1RX 0x00010005
//
// GPIO pin B1
//
#define GPIO_PB1_CCP2 0x00010401
#define GPIO_PB1_PWM3 0x00010402
#define GPIO_PB1_CCP1 0x00010404
#define GPIO_PB1_U1TX 0x00010405
//
// GPIO pin B2
//
#define GPIO_PB2_I2C0SCL 0x00010801
#define GPIO_PB2_IDX0 0x00010802
#define GPIO_PB2_CCP3 0x00010804
#define GPIO_PB2_CCP0 0x00010805
#define GPIO_PB2_USB0EPEN 0x00010808
//
// GPIO pin B3
//
#define GPIO_PB3_I2C0SDA 0x00010c01
#define GPIO_PB3_FAULT0 0x00010c02
#define GPIO_PB3_FAULT3 0x00010c04
#define GPIO_PB3_USB0PFLT 0x00010c08
//
// GPIO pin B4
//
#define GPIO_PB4_U2RX 0x00011004
#define GPIO_PB4_CAN0RX 0x00011005
#define GPIO_PB4_IDX0 0x00011006
#define GPIO_PB4_U1RX 0x00011007
#define GPIO_PB4_EPI0S23 0x00011008
//
// GPIO pin B5
//
#define GPIO_PB5_C0O 0x00011401
#define GPIO_PB5_CCP5 0x00011402
#define GPIO_PB5_CCP6 0x00011403
#define GPIO_PB5_CCP0 0x00011404
#define GPIO_PB5_CAN0TX 0x00011405
#define GPIO_PB5_CCP2 0x00011406
#define GPIO_PB5_U1TX 0x00011407
#define GPIO_PB5_EPI0S22 0x00011408
//
// GPIO pin B6
//
#define GPIO_PB6_CCP1 0x00011801
#define GPIO_PB6_CCP7 0x00011802
#define GPIO_PB6_C0O 0x00011803
#define GPIO_PB6_FAULT1 0x00011804
#define GPIO_PB6_IDX0 0x00011805
#define GPIO_PB6_CCP5 0x00011806
#define GPIO_PB6_I2S0TXSCK 0x00011809
//
// GPIO pin B7
//
#define GPIO_PB7_NMI 0x00011c04
//
// GPIO pin C0
//
#define GPIO_PC0_TCK 0x00020003
//
// GPIO pin C1
//
#define GPIO_PC1_TMS 0x00020403
//
// GPIO pin C2
//
#define GPIO_PC2_TDI 0x00020803
//
// GPIO pin C3
//
#define GPIO_PC3_TDO 0x00020c03
//
// GPIO pin C4
//
#define GPIO_PC4_CCP5 0x00021001
#define GPIO_PC4_PHA0 0x00021002
#define GPIO_PC4_PWM6 0x00021004
#define GPIO_PC4_CCP2 0x00021005
#define GPIO_PC4_CCP4 0x00021006
#define GPIO_PC4_EPI0S2 0x00021008
#define GPIO_PC4_CCP1 0x00021009
//
// GPIO pin C5
//
#define GPIO_PC5_CCP1 0x00021401
#define GPIO_PC5_C1O 0x00021402
#define GPIO_PC5_C0O 0x00021403
#define GPIO_PC5_FAULT2 0x00021404
#define GPIO_PC5_CCP3 0x00021405
#define GPIO_PC5_USB0EPEN 0x00021406
#define GPIO_PC5_EPI0S3 0x00021408
//
// GPIO pin C6
//
#define GPIO_PC6_CCP3 0x00021801
#define GPIO_PC6_PHB0 0x00021802
#define GPIO_PC6_C2O 0x00021803
#define GPIO_PC6_PWM7 0x00021804
#define GPIO_PC6_U1RX 0x00021805
#define GPIO_PC6_CCP0 0x00021806
#define GPIO_PC6_USB0PFLT 0x00021807
#define GPIO_PC6_EPI0S4 0x00021808
//
// GPIO pin C7
//
#define GPIO_PC7_CCP4 0x00021c01
#define GPIO_PC7_PHB0 0x00021c02
#define GPIO_PC7_CCP0 0x00021c04
#define GPIO_PC7_U1TX 0x00021c05
#define GPIO_PC7_USB0PFLT 0x00021c06
#define GPIO_PC7_C1O 0x00021c07
#define GPIO_PC7_EPI0S5 0x00021c08
//
// GPIO pin D0
//
#define GPIO_PD0_PWM0 0x00030001
#define GPIO_PD0_CAN0RX 0x00030002
#define GPIO_PD0_IDX0 0x00030003
#define GPIO_PD0_U2RX 0x00030004
#define GPIO_PD0_U1RX 0x00030005
#define GPIO_PD0_CCP6 0x00030006
#define GPIO_PD0_I2S0RXSCK 0x00030008
#define GPIO_PD0_U1CTS 0x00030009
//
// GPIO pin D1
//
#define GPIO_PD1_PWM1 0x00030401
#define GPIO_PD1_CAN0TX 0x00030402
#define GPIO_PD1_PHA0 0x00030403
#define GPIO_PD1_U2TX 0x00030404
#define GPIO_PD1_U1TX 0x00030405
#define GPIO_PD1_CCP7 0x00030406
#define GPIO_PD1_I2S0RXWS 0x00030408
#define GPIO_PD1_U1DCD 0x00030409
#define GPIO_PD1_CCP2 0x0003040a
#define GPIO_PD1_PHB1 0x0003040b
//
// GPIO pin D2
//
#define GPIO_PD2_U1RX 0x00030801
#define GPIO_PD2_CCP6 0x00030802
#define GPIO_PD2_PWM2 0x00030803
#define GPIO_PD2_CCP5 0x00030804
#define GPIO_PD2_EPI0S20 0x00030808
//
// GPIO pin D3
//
#define GPIO_PD3_U1TX 0x00030c01
#define GPIO_PD3_CCP7 0x00030c02
#define GPIO_PD3_PWM3 0x00030c03
#define GPIO_PD3_CCP0 0x00030c04
#define GPIO_PD3_EPI0S21 0x00030c08
//
// GPIO pin D4
//
#define GPIO_PD4_CCP0 0x00031001
#define GPIO_PD4_CCP3 0x00031002
#define GPIO_PD4_I2S0RXSD 0x00031008
#define GPIO_PD4_U1RI 0x00031009
#define GPIO_PD4_EPI0S19 0x0003100a
//
// GPIO pin D5
//
#define GPIO_PD5_CCP2 0x00031401
#define GPIO_PD5_CCP4 0x00031402
#define GPIO_PD5_I2S0RXMCLK 0x00031408
#define GPIO_PD5_U2RX 0x00031409
#define GPIO_PD5_EPI0S28 0x0003140a
//
// GPIO pin D6
//
#define GPIO_PD6_FAULT0 0x00031801
#define GPIO_PD6_I2S0TXSCK 0x00031808
#define GPIO_PD6_U2TX 0x00031809
#define GPIO_PD6_EPI0S29 0x0003180a
//
// GPIO pin D7
//
#define GPIO_PD7_IDX0 0x00031c01
#define GPIO_PD7_C0O 0x00031c02
#define GPIO_PD7_CCP1 0x00031c03
#define GPIO_PD7_I2S0TXWS 0x00031c08
#define GPIO_PD7_U1DTR 0x00031c09
#define GPIO_PD7_EPI0S30 0x00031c0a
//
// GPIO pin E0
//
#define GPIO_PE0_PWM4 0x00040001
#define GPIO_PE0_SSI1CLK 0x00040002
#define GPIO_PE0_CCP3 0x00040003
#define GPIO_PE0_EPI0S8 0x00040008
#define GPIO_PE0_USB0PFLT 0x00040009
//
// GPIO pin E1
//
#define GPIO_PE1_PWM5 0x00040401
#define GPIO_PE1_SSI1FSS 0x00040402
#define GPIO_PE1_FAULT0 0x00040403
#define GPIO_PE1_CCP2 0x00040404
#define GPIO_PE1_CCP6 0x00040405
#define GPIO_PE1_EPI0S9 0x00040408
//
// GPIO pin E2
//
#define GPIO_PE2_CCP4 0x00040801
#define GPIO_PE2_SSI1RX 0x00040802
#define GPIO_PE2_PHB1 0x00040803
#define GPIO_PE2_PHA0 0x00040804
#define GPIO_PE2_CCP2 0x00040805
#define GPIO_PE2_EPI0S24 0x00040808
//
// GPIO pin E3
//
#define GPIO_PE3_CCP1 0x00040c01
#define GPIO_PE3_SSI1TX 0x00040c02
#define GPIO_PE3_PHA1 0x00040c03
#define GPIO_PE3_PHB0 0x00040c04
#define GPIO_PE3_CCP7 0x00040c05
#define GPIO_PE3_EPI0S25 0x00040c08
//
// GPIO pin E4
//
#define GPIO_PE4_CCP3 0x00041001
#define GPIO_PE4_FAULT0 0x00041004
#define GPIO_PE4_U2TX 0x00041005
#define GPIO_PE4_CCP2 0x00041006
#define GPIO_PE4_I2S0TXWS 0x00041009
//
// GPIO pin E5
//
#define GPIO_PE5_CCP5 0x00041401
#define GPIO_PE5_I2S0TXSD 0x00041409
//
// GPIO pin E6
//
#define GPIO_PE6_PWM4 0x00041801
#define GPIO_PE6_C1O 0x00041802
#define GPIO_PE6_U1CTS 0x00041809
//
// GPIO pin E7
//
#define GPIO_PE7_PWM5 0x00041c01
#define GPIO_PE7_C2O 0x00041c02
#define GPIO_PE7_U1DCD 0x00041c09
//
// GPIO pin F0
//
#define GPIO_PF0_CAN1RX 0x00050001
#define GPIO_PF0_PHB0 0x00050002
#define GPIO_PF0_PWM0 0x00050003
#define GPIO_PF0_I2S0TXSD 0x00050008
#define GPIO_PF0_U1DSR 0x00050009
//
// GPIO pin F1
//
#define GPIO_PF1_CAN1TX 0x00050401
#define GPIO_PF1_IDX1 0x00050402
#define GPIO_PF1_PWM1 0x00050403
#define GPIO_PF1_I2S0TXMCLK 0x00050408
#define GPIO_PF1_U1RTS 0x00050409
#define GPIO_PF1_CCP3 0x0005040a
//
// GPIO pin F2
//
#define GPIO_PF2_LED1 0x00050801
#define GPIO_PF2_PWM4 0x00050802
#define GPIO_PF2_PWM2 0x00050804
#define GPIO_PF2_SSI1CLK 0x00050809
//
// GPIO pin F3
//
#define GPIO_PF3_LED0 0x00050c01
#define GPIO_PF3_PWM5 0x00050c02
#define GPIO_PF3_PWM3 0x00050c04
#define GPIO_PF3_SSI1FSS 0x00050c09
//
// GPIO pin F4
//
#define GPIO_PF4_CCP0 0x00051001
#define GPIO_PF4_C0O 0x00051002
#define GPIO_PF4_FAULT0 0x00051004
#define GPIO_PF4_EPI0S12 0x00051008
#define GPIO_PF4_SSI1RX 0x00051009
//
// GPIO pin F5
//
#define GPIO_PF5_CCP2 0x00051401
#define GPIO_PF5_C1O 0x00051402
#define GPIO_PF5_EPI0S15 0x00051408
#define GPIO_PF5_SSI1TX 0x00051409
//
// GPIO pin F6
//
#define GPIO_PF6_CCP1 0x00051801
#define GPIO_PF6_C2O 0x00051802
#define GPIO_PF6_PHA0 0x00051804
#define GPIO_PF6_I2S0TXMCLK 0x00051809
#define GPIO_PF6_U1RTS 0x0005180a
//
// GPIO pin F7
//
#define GPIO_PF7_CCP4 0x00051c01
#define GPIO_PF7_PHB0 0x00051c04
#define GPIO_PF7_EPI0S12 0x00051c08
#define GPIO_PF7_FAULT1 0x00051c09
//
// GPIO pin G0
//
#define GPIO_PG0_U2RX 0x00060001
#define GPIO_PG0_PWM0 0x00060002
#define GPIO_PG0_I2C1SCL 0x00060003
#define GPIO_PG0_PWM4 0x00060004
#define GPIO_PG0_USB0EPEN 0x00060007
#define GPIO_PG0_EPI0S13 0x00060008
//
// GPIO pin G1
//
#define GPIO_PG1_U2TX 0x00060401
#define GPIO_PG1_PWM1 0x00060402
#define GPIO_PG1_I2C1SDA 0x00060403
#define GPIO_PG1_PWM5 0x00060404
#define GPIO_PG1_EPI0S14 0x00060408
//
// GPIO pin G2
//
#define GPIO_PG2_PWM0 0x00060801
#define GPIO_PG2_FAULT0 0x00060804
#define GPIO_PG2_IDX1 0x00060808
#define GPIO_PG2_I2S0RXSD 0x00060809
//
// GPIO pin G3
//
#define GPIO_PG3_PWM1 0x00060c01
#define GPIO_PG3_FAULT2 0x00060c04
#define GPIO_PG3_FAULT0 0x00060c08
#define GPIO_PG3_I2S0RXMCLK 0x00060c09
//
// GPIO pin G4
//
#define GPIO_PG4_CCP3 0x00061001
#define GPIO_PG4_FAULT1 0x00061004
#define GPIO_PG4_EPI0S15 0x00061008
#define GPIO_PG4_PWM6 0x00061009
#define GPIO_PG4_U1RI 0x0006100a
//
// GPIO pin G5
//
#define GPIO_PG5_CCP5 0x00061401
#define GPIO_PG5_IDX0 0x00061404
#define GPIO_PG5_FAULT1 0x00061405
#define GPIO_PG5_PWM7 0x00061408
#define GPIO_PG5_I2S0RXSCK 0x00061409
#define GPIO_PG5_U1DTR 0x0006140a
//
// GPIO pin G6
//
#define GPIO_PG6_PHA1 0x00061801
#define GPIO_PG6_PWM6 0x00061804
#define GPIO_PG6_FAULT1 0x00061808
#define GPIO_PG6_I2S0RXWS 0x00061809
#define GPIO_PG6_U1RI 0x0006180a
//
// GPIO pin G7
//
#define GPIO_PG7_PHB1 0x00061c01
#define GPIO_PG7_PWM7 0x00061c04
#define GPIO_PG7_CCP5 0x00061c08
#define GPIO_PG7_EPI0S31 0x00061c09
//
// GPIO pin H0
//
#define GPIO_PH0_CCP6 0x00070001
#define GPIO_PH0_PWM2 0x00070002
#define GPIO_PH0_EPI0S6 0x00070008
#define GPIO_PH0_PWM4 0x00070009
//
// GPIO pin H1
//
#define GPIO_PH1_CCP7 0x00070401
#define GPIO_PH1_PWM3 0x00070402
#define GPIO_PH1_EPI0S7 0x00070408
#define GPIO_PH1_PWM5 0x00070409
//
// GPIO pin H2
//
#define GPIO_PH2_IDX1 0x00070801
#define GPIO_PH2_C1O 0x00070802
#define GPIO_PH2_FAULT3 0x00070804
#define GPIO_PH2_EPI0S1 0x00070808
//
// GPIO pin H3
//
#define GPIO_PH3_PHB0 0x00070c01
#define GPIO_PH3_FAULT0 0x00070c02
#define GPIO_PH3_USB0EPEN 0x00070c04
#define GPIO_PH3_EPI0S0 0x00070c08
//
// GPIO pin H4
//
#define GPIO_PH4_USB0PFLT 0x00071004
#define GPIO_PH4_EPI0S10 0x00071008
#define GPIO_PH4_SSI1CLK 0x0007100b
//
// GPIO pin H5
//
#define GPIO_PH5_EPI0S11 0x00071408
#define GPIO_PH5_FAULT2 0x0007140a
#define GPIO_PH5_SSI1FSS 0x0007140b
//
// GPIO pin H6
//
#define GPIO_PH6_EPI0S26 0x00071808
#define GPIO_PH6_PWM4 0x0007180a
#define GPIO_PH6_SSI1RX 0x0007180b
//
// GPIO pin H7
//
#define GPIO_PH7_EPI0S27 0x00071c08
#define GPIO_PH7_PWM5 0x00071c0a
#define GPIO_PH7_SSI1TX 0x00071c0b
//
// GPIO pin J0
//
#define GPIO_PJ0_EPI0S16 0x00080008
#define GPIO_PJ0_PWM0 0x0008000a
#define GPIO_PJ0_I2C1SCL 0x0008000b
//
// GPIO pin J1
//
#define GPIO_PJ1_EPI0S17 0x00080408
#define GPIO_PJ1_USB0PFLT 0x00080409
#define GPIO_PJ1_PWM1 0x0008040a
#define GPIO_PJ1_I2C1SDA 0x0008040b
//
// GPIO pin J2
//
#define GPIO_PJ2_EPI0S18 0x00080808
#define GPIO_PJ2_CCP0 0x00080809
#define GPIO_PJ2_FAULT0 0x0008080a
//
// GPIO pin J3
//
#define GPIO_PJ3_EPI0S19 0x00080c08
#define GPIO_PJ3_U1CTS 0x00080c09
#define GPIO_PJ3_CCP6 0x00080c0a
//
// GPIO pin J4
//
#define GPIO_PJ4_EPI0S28 0x00081008
#define GPIO_PJ4_U1DCD 0x00081009
#define GPIO_PJ4_CCP4 0x0008100a
//
// GPIO pin J5
//
#define GPIO_PJ5_EPI0S29 0x00081408
#define GPIO_PJ5_U1DSR 0x00081409
#define GPIO_PJ5_CCP2 0x0008140a
//
// GPIO pin J6
//
#define GPIO_PJ6_EPI0S30 0x00081808
#define GPIO_PJ6_U1RTS 0x00081809
#define GPIO_PJ6_CCP1 0x0008180a
//
// GPIO pin J7
//
#define GPIO_PJ7_U1DTR 0x00081c09
#define GPIO_PJ7_CCP0 0x00081c0a
//*****************************************************************************
//
// Prototypes for the APIs.
@ -741,12 +146,18 @@ extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
@ -754,6 +165,25 @@ extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
//****************************************************************************
//
// The definitions for GPIOPinConfigure previously resided in this file but
// have been moved to pin_map.h and made part-specific (in other words, only
// those definitions that are valid based on the selected part, as defined by
// PART_<partnum>, will be made available). For backwards compatibility,
// pin_map.h is included here so that the expected definitions will still be
// available (though part-specific now, so some that were previously available
// but inappropriate for the given part will not be available).
//
//*****************************************************************************
#ifndef DEPRECATED
#include "pin_map.h"
#endif
//*****************************************************************************
//

View File

@ -2,23 +2,38 @@
//
// interrupt.c - Driver for the NVIC Interrupt Controller.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -59,7 +74,58 @@ static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
NVIC_PRI32, NVIC_PRI33, NVIC_PRI34
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt enable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulEnRegs[] =
{
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt disable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulDisRegs[] =
{
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt pend for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulPendRegs[] =
{
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt unpend for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulUnpendRegs[] =
{
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4
};
//*****************************************************************************
@ -97,30 +163,32 @@ IntDefaultHandler(void)
//
//*****************************************************************************
#if defined(ewarm)
#pragma data_alignment=1024
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
#elif defined(sourcerygxx)
static __attribute__((section(".cs3.region-head.ram")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#elif defined(ccs)
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
#elif defined(ccs) || defined(DOXYGEN)
#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#else
static __attribute__((section("vtable")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
#endif
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//! This function allows the processor to respond to interrupts. This function
//! does not affect the set of interrupts enabled in the interrupt controller;
//! it just gates the single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! <tt>tBoolean</tt>, a compiler error occurs in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were disabled when the function was
@ -140,14 +208,15 @@ IntMasterEnable(void)
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//! This function prevents the processor from receiving interrupts. This
//! function does not affect the set of interrupts enabled in the interrupt
//! controller; it just gates the single interrupt from the controller to the
//! processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! <tt>tBoolean</tt>, a compiler error occurs in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were already disabled when the
@ -172,16 +241,16 @@ IntMasterDisable(void)
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function will be called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//! if it is enabled (via IntEnable()), the handler function is called in
//! interrupt context. Because the handler function can preempt other code,
//! care must be taken to protect memory or peripherals that are accessed by
//! the handler and other non-handler code.
//!
//! \note The use of this function (directly or indirectly via a peripheral
//! driver interrupt register function) moves the interrupt vector table from
//! flash to SRAM. Therefore, care must be taken when linking the application
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
//! otherwise NVIC will not look in the correct portion of memory for the
//! otherwise the NVIC does not look in the correct portion of memory for the
//! vector table (it requires the vector table be on a 1 kB memory alignment).
//! Normally, the SRAM vector table is so placed via the use of linker scripts.
//! See the discussion of compile-time versus run-time interrupt handler
@ -222,7 +291,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
}
//
// Point NVIC at the RAM vector table.
// Point the NVIC at the RAM vector table.
//
HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
}
@ -240,7 +309,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source will be
//! given interrupt is asserted to the processor. The interrupt source is
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
@ -270,7 +339,7 @@ IntUnregister(unsigned long ulInterrupt)
//! \param ulBits specifies the number of bits of preemptable priority.
//!
//! This function specifies the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification. The range of
//! sub-priority levels in the interrupt priority specification. The range of
//! the grouping values are dependent upon the hardware implementation; on
//! the Stellaris family, three bits are available for hardware interrupt
//! prioritization and therefore priority grouping values of three through
@ -298,7 +367,7 @@ IntPriorityGroupingSet(unsigned long ulBits)
//! Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//! sub-priority levels in the interrupt priority specification.
//!
//! \return The number of bits of preemptable priority.
//
@ -346,7 +415,7 @@ IntPriorityGroupingGet(void)
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits. The remaining bits can be
//! used to sub-prioritize the interrupt sources, and may be used by the
@ -456,19 +525,13 @@ IntEnable(unsigned long ulInterrupt)
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@ -524,20 +587,83 @@ IntDisable(unsigned long ulInterrupt)
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Disable the general interrupt.
//
HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
else if(ulInterrupt >= 48)
}
//*****************************************************************************
//
//! Returns if a peripheral interrupt is enabled.
//!
//! \param ulInterrupt specifies the interrupt to check.
//!
//! This function checks if the specified interrupt is enabled in the interrupt
//! controller.
//!
//! \return A non-zero value if the interrupt is enabled.
//
//*****************************************************************************
unsigned long
IntIsEnabled(unsigned long ulInterrupt)
{
unsigned long ulRet;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Initialize the return value.
//
ulRet = 0;
//
// Determine the interrupt to disable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Disable the general interrupt.
// Check the MemManage interrupt.
//
HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_MEM;
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Check the bus fault interrupt.
//
ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_BUS;
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Check the usage fault interrupt.
//
ulRet = HWREG(NVIC_SYS_HND_CTRL) & NVIC_SYS_HND_CTRL_USAGE;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Check the System Tick interrupt.
//
ulRet = HWREG(NVIC_ST_CTRL) & NVIC_ST_CTRL_INTEN;
}
else if(ulInterrupt >= 16)
{
//
// Check the general interrupt.
//
ulRet = HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) &
(1 << ((ulInterrupt - 16) & 31));
}
return(ulRet);
}
//*****************************************************************************
@ -546,13 +672,13 @@ IntDisable(unsigned long ulInterrupt)
//!
//! \param ulInterrupt specifies the interrupt to be pended.
//!
//! The specified interrupt is pended in the interrupt controller. This will
//! cause the interrupt controller to execute the corresponding interrupt
//! handler at the next available time, based on the current interrupt state
//! priorities. For example, if called by a higher priority interrupt handler,
//! the specified interrupt handler will not be called until after the current
//! interrupt handler has completed execution. The interrupt must have been
//! enabled for it to be called.
//! The specified interrupt is pended in the interrupt controller. Pending an
//! interrupt causes the interrupt controller to execute the corresponding
//! interrupt handler at the next available time, based on the current
//! interrupt state priorities. For example, if called by a higher priority
//! interrupt handler, the specified interrupt handler is not called until
//! after the current interrupt handler has completed execution. The interrupt
//! must have been enabled for it to be called.
//!
//! \return None.
//
@ -589,32 +715,26 @@ IntPendSet(unsigned long ulInterrupt)
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Pend the general interrupt.
//
HWREG(NVIC_PEND0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Pend the general interrupt.
//
HWREG(NVIC_PEND1) = 1 << (ulInterrupt - 48);
HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
//*****************************************************************************
//
//! Unpends an interrupt.
//! Un-pends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be unpended.
//! \param ulInterrupt specifies the interrupt to be un-pended.
//!
//! The specified interrupt is unpended in the interrupt controller. This will
//! cause any previously generated interrupts that have not been handled yet
//! (due to higher priority interrupts or the interrupt no having been enabled
//! yet) to be discarded.
//! The specified interrupt is un-pended in the interrupt controller. This
//! will cause any previously generated interrupts that have not been handled
//! yet (due to higher priority interrupts or the interrupt no having been
//! enabled yet) to be discarded.
//!
//! \return None.
//
@ -644,19 +764,13 @@ IntPendClear(unsigned long ulInterrupt)
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Unpend the general interrupt.
//
HWREG(NVIC_UNPEND0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Unpend the general interrupt.
//
HWREG(NVIC_UNPEND1) = 1 << (ulInterrupt - 48);
HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@ -664,19 +778,19 @@ IntPendClear(unsigned long ulInterrupt)
//
//! Sets the priority masking level
//!
//! \param ulPriorityMask is the priority level that will be masked.
//! \param ulPriorityMask is the priority level that is masked.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level is masked. This
//! can be used to globally disable a set of interrupts with priority below
//! a predetermined threshold. A value of 0 disables priority
//! interrupts at the specified or lesser priority level are masked. Masking
//! interrupts can be used to globally disable a set of interrupts with
//! priority below a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//! a priority level mask of 4 allows interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater are blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits.
//!
@ -699,10 +813,10 @@ IntPriorityMaskSet(unsigned long ulPriorityMask)
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//! a priority level mask of 4 allows interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater are blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits.
//!

View File

@ -2,23 +2,38 @@
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -60,6 +75,7 @@ extern void IntPrioritySet(unsigned long ulInterrupt,
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
extern unsigned long IntIsEnabled(unsigned long ulInterrupt);
extern void IntPendSet(unsigned long ulInterrupt);
extern void IntPendClear(unsigned long ulInterrupt);
extern void IntPriorityMaskSet(unsigned long ulPriorityMask);

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,870 @@
//*****************************************************************************
//
// ssi.c - Driver for Synchronous Serial Interface.
//
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ssi_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ssi.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/ssi.h"
//*****************************************************************************
//
// A mapping of timer base address to interupt number.
//
//*****************************************************************************
static const unsigned long g_ppulSSIIntMap[][2] =
{
{ SSI0_BASE, INT_SSI0 },
{ SSI1_BASE, INT_SSI1 },
{ SSI2_BASE, INT_SSI2 },
{ SSI3_BASE, INT_SSI3 },
};
//*****************************************************************************
//
//! \internal
//! Checks an SSI base address.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function determines if a SSI module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
SSIBaseValid(unsigned long ulBase)
{
return((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE) ||
(ulBase == SSI2_BASE) || (ulBase == SSI3_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the SSI interrupt number.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! Given a SSI base address, returns the corresponding interrupt number.
//!
//! \return Returns an SSI interrupt number, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
SSIIntNumberGet(unsigned long ulBase)
{
unsigned long ulIdx;
//
// Loop through the table that maps SSI base addresses to interrupt
// numbers.
//
for(ulIdx = 0; ulIdx < (sizeof(g_ppulSSIIntMap) /
sizeof(g_ppulSSIIntMap[0])); ulIdx++)
{
//
// See if this base address matches.
//
if(g_ppulSSIIntMap[ulIdx][0] == ulBase)
{
//
// Return the corresponding interrupt number.
//
return(g_ppulSSIIntMap[ulIdx][1]);
}
}
//
// The base address could not be found, so return an error.
//
return(-1);
}
//*****************************************************************************
//
//! Configures the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulSSIClk is the rate of the clock supplied to the SSI module.
//! \param ulProtocol specifies the data transfer protocol.
//! \param ulMode specifies the mode of operation.
//! \param ulBitRate specifies the clock rate.
//! \param ulDataWidth specifies number of bits transferred per frame.
//!
//! This function configures the synchronous serial interface. It sets
//! the SSI protocol, mode of operation, bit rate, and data width.
//!
//! The \e ulProtocol parameter defines the data frame format. The
//! \e ulProtocol parameter can be one of the following values:
//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
//! frame formats encode the following polarity and phase configurations:
//!
//! <pre>
//! Polarity Phase Mode
//! 0 0 SSI_FRF_MOTO_MODE_0
//! 0 1 SSI_FRF_MOTO_MODE_1
//! 1 0 SSI_FRF_MOTO_MODE_2
//! 1 1 SSI_FRF_MOTO_MODE_3
//! </pre>
//!
//! The \e ulMode parameter defines the operating mode of the SSI module. The
//! SSI module can operate as a master or slave; if it is a slave, the SSI can
//! be configured to disable output on its serial output line. The \e ulMode
//! parameter can be one of the following values: \b SSI_MODE_MASTER,
//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
//!
//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
//! must satisfy the following clock ratio criteria:
//!
//! - FSSI >= 2 * bit rate (master mode); this speed cannot exceed 25 MHz.
//! - FSSI >= 12 * bit rate or 6 * bit rate (slave modes), depending on the
//! capability of the specific microcontroller
//!
//! where FSSI is the frequency of the clock supplied to the SSI module.
//!
//! The \e ulDataWidth parameter defines the width of the data transfers and
//! can be a value between 4 and 16, inclusive.
//!
//! The peripheral clock is the same as the processor clock. This value is
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! This function replaces the original SSIConfig() API and performs the same
//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
//! this API.
//!
//! \return None.
//
//*****************************************************************************
void
SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate, unsigned long ulDataWidth)
{
unsigned long ulMaxBitRate;
unsigned long ulRegVal;
unsigned long ulPreDiv;
unsigned long ulSCR;
unsigned long ulSPH_SPO;
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
(ulProtocol == SSI_FRF_MOTO_MODE_1) ||
(ulProtocol == SSI_FRF_MOTO_MODE_2) ||
(ulProtocol == SSI_FRF_MOTO_MODE_3) ||
(ulProtocol == SSI_FRF_TI) ||
(ulProtocol == SSI_FRF_NMW));
ASSERT((ulMode == SSI_MODE_MASTER) ||
(ulMode == SSI_MODE_SLAVE) ||
(ulMode == SSI_MODE_SLAVE_OD));
ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) ||
((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12))));
ASSERT((ulSSIClk / ulBitRate) <= (254 * 256));
ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
//
// Set the mode.
//
ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
HWREG(ulBase + SSI_O_CR1) = ulRegVal;
//
// Set the clock predivider.
//
ulMaxBitRate = ulSSIClk / ulBitRate;
ulPreDiv = 0;
do
{
ulPreDiv += 2;
ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
}
while(ulSCR > 255);
HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
//
// Set protocol and clock rate.
//
ulSPH_SPO = (ulProtocol & 3) << 6;
ulProtocol &= SSI_CR0_FRF_M;
ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
HWREG(ulBase + SSI_O_CR0) = ulRegVal;
}
//*****************************************************************************
//
//! Enables the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function enables operation of the synchronous serial interface. The
//! synchronous serial interface must be configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
SSIEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Read-modify-write the enable bit.
//
HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
}
//*****************************************************************************
//
//! Disables the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function disables operation of the synchronous serial interface.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Read-modify-write the enable bit.
//
HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pfnHandler is a pointer to the function to be called when the
//! synchronous serial interface interrupt occurs.
//!
//! This function registers the handler to be called when an SSI interrupt
//! occurs. This function enables the global interrupt in the interrupt
//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If
//! necessary, it is the interrupt handler's responsibility to clear the
//! interrupt source via SSIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = SSIIntNumberGet(ulBase);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(ulInt, pfnHandler);
//
// Enable the synchronous serial interface interrupt.
//
IntEnable(ulInt);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function clears the handler to be called when an SSI interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntUnregister(unsigned long ulBase)
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = SSIIntNumberGet(ulBase);
//
// Disable the interrupt.
//
IntDisable(ulInt);
//
// Unregister the interrupt handler.
//
IntUnregister(ulInt);
}
//*****************************************************************************
//
//! Enables individual SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated SSI interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor. The \e ulIntFlags
//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or
//! \b SSI_RXOR values.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Enable the specified interrupts.
//
HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated SSI interrupt sources. The
//! \e ulIntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF,
//! \b SSI_RXTO, or \b SSI_RXOR values.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Disable the specified interrupts.
//
HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase specifies the SSI module base address.
//! \param bMasked is \b false if the raw interrupt status is required or
//! \b true if the masked interrupt status is required.
//!
//! This function returns the interrupt status for the SSI module. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
//
//*****************************************************************************
unsigned long
SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + SSI_O_MIS));
}
else
{
return(HWREG(ulBase + SSI_O_RIS));
}
}
//*****************************************************************************
//
//! Clears SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears the specified SSI interrupt sources so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep the interrupts from being triggered again immediately upon exit. The
//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and
//! \b SSI_RXOR values.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
}
//*****************************************************************************
//
//! Puts a data element into the SSI transmit FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulData is the data to be transmitted over the SSI interface.
//!
//! This function places the supplied data into the transmit FIFO of the
//! specified SSI module. If there is no space available in the transmit FIFO,
//! this function waits until there is space available before returning.
//!
//! \note The upper 32 - N bits of \e ulData are discarded by the hardware,
//! where N is the data width as configured by SSIConfigSetExpClk(). For
//! example, if the interface is configured for 8-bit data width, the upper 24
//! bits of \e ulData are discarded.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDataPut(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
//
// Wait until there is space.
//
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
{
}
//
// Write the data to the SSI.
//
HWREG(ulBase + SSI_O_DR) = ulData;
}
//*****************************************************************************
//
//! Puts a data element into the SSI transmit FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulData is the data to be transmitted over the SSI interface.
//!
//! This function places the supplied data into the transmit FIFO of the
//! specified SSI module. If there is no space in the FIFO, then this function
//! returns a zero.
//!
//! This function replaces the original SSIDataNonBlockingPut() API and
//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
//! the original API to this API.
//!
//! \note The upper 32 - N bits of \e ulData are discarded by the hardware,
//! where N is the data width as configured by SSIConfigSetExpClk(). For
//! example, if the interface is configured for 8-bit data width, the upper 24
//! bits of \e ulData are discarded.
//!
//! \return Returns the number of elements written to the SSI transmit FIFO.
//
//*****************************************************************************
long
SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
//
// Check for space to write.
//
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
{
HWREG(ulBase + SSI_O_DR) = ulData;
return(1);
}
else
{
return(0);
}
}
//*****************************************************************************
//
//! Gets a data element from the SSI receive FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pulData is a pointer to a storage location for data that was
//! received over the SSI interface.
//!
//! This function gets received data from the receive FIFO of the specified
//! SSI module and places that data into the location specified by the
//! \e pulData parameter. If there is no data available, this function waits
//! until data is received before returning.
//!
//! \note Only the lower N bits of the value written to \e pulData contain
//! valid data, where N is the data width as configured by
//! SSIConfigSetExpClk(). For example, if the interface is configured for
//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
//! contain valid data.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDataGet(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Wait until there is data to be read.
//
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
{
}
//
// Read data from SSI.
//
*pulData = HWREG(ulBase + SSI_O_DR);
}
//*****************************************************************************
//
//! Gets a data element from the SSI receive FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pulData is a pointer to a storage location for data that was
//! received over the SSI interface.
//!
//! This function gets received data from the receive FIFO of the specified SSI
//! module and places that data into the location specified by the \e ulData
//! parameter. If there is no data in the FIFO, then this function returns a
//! zero.
//!
//! This function replaces the original SSIDataNonBlockingGet() API and
//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
//! the original API to this API.
//!
//! \note Only the lower N bits of the value written to \e pulData contain
//! valid data, where N is the data width as configured by
//! SSIConfigSetExpClk(). For example, if the interface is configured for
//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
//! contain valid data.
//!
//! \return Returns the number of elements read from the SSI receive FIFO.
//
//*****************************************************************************
long
SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Check for data to read.
//
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
{
*pulData = HWREG(ulBase + SSI_O_DR);
return(1);
}
else
{
return(0);
}
}
//*****************************************************************************
//
//! Enables SSI DMA operation.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
//!
//! This function enables the specified SSI DMA features. The SSI can be
//! configured to use DMA for transmit and/or receive data transfers.
//! The \e ulDMAFlags parameter is the logical OR of any of the following
//! values:
//!
//! - SSI_DMA_RX - enable DMA for receive
//! - SSI_DMA_TX - enable DMA for transmit
//!
//! \note The uDMA controller must also be set up before DMA can be used
//! with the SSI.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Set the requested bits in the SSI DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
}
//*****************************************************************************
//
//! Disables SSI DMA operation.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulDMAFlags is a bit mask of the DMA features to disable.
//!
//! This function is used to disable SSI DMA features that were enabled
//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
//! \e ulDMAFlags parameter is the logical OR of any of the following values:
//!
//! - SSI_DMA_RX - disable DMA for receive
//! - SSI_DMA_TX - disable DMA for transmit
//!
//! \return None.
//
//*****************************************************************************
void
SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Clear the requested bits in the SSI DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
}
//*****************************************************************************
//
//! Determines whether the SSI transmitter is busy or not.
//!
//! \param ulBase is the base address of the SSI port.
//!
//! This function allows the caller to determine whether all transmitted bytes
//! have cleared the transmitter hardware. If \b false is returned, then the
//! transmit FIFO is empty and all bits of the last transmitted word have left
//! the hardware shift register.
//!
//! \return Returns \b true if the SSI is transmitting or \b false if all
//! transmissions are complete.
//
//*****************************************************************************
tBoolean
SSIBusy(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Determine if the SSI is busy.
//
return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false);
}
//*****************************************************************************
//
//! Sets the data clock source for the specified SSI peripheral.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulSource is the baud clock source for the SSI.
//!
//! This function allows the baud clock source for the SSI to be selected.
//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
//!
//! Changing the baud clock source changes the data rate generated by the
//! SSI. Therefore, the data rate should be reconfigured after any change to
//! the SSI clock source.
//!
//! \note The ability to specify the SSI baud clock source varies with the
//! Stellaris part and SSI in use. Please consult the data sheet for the part
//! in use to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulSource == SSI_CLOCK_SYSTEM) || (ulSource == SSI_CLOCK_PIOSC));
//
// Set the SSI clock source.
//
HWREG(ulBase + SSI_O_CC) = ulSource;
}
//*****************************************************************************
//
//! Gets the data clock source for the specified SSI peripheral.
//!
//! \param ulBase is the base address of the SSI port.
//!
//! This function returns the data clock source for the specified SSI. The
//! possible data clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
//!
//! \note The ability to specify the SSI data clock source varies with the
//! Stellaris part and SSI in use. Please consult the data sheet for the part
//! in use to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
SSIClockSourceGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Return the SSI clock source.
//
return(HWREG(ulBase + SSI_O_CC));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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@ -0,0 +1,151 @@
//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half full or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or more
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfigSetExpClk.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
//
//*****************************************************************************
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values that can be passed to SSIClockSourceSet() or returned from
// SSIClockSourceGet().
//
//*****************************************************************************
#define SSI_CLOCK_SYSTEM 0x00000000
#define SSI_CLOCK_PIOSC 0x00000005
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SSIDataGetNonBlocking(unsigned long ulBase,
unsigned long *pulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern tBoolean SSIBusy(unsigned long ulBase);
extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long SSIClockSourceGet(unsigned long ulBase);
//*****************************************************************************
//
// Several SSI APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define SSIConfig(a, b, c, d, e) \
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
#define SSIDataNonBlockingGet(a, b) \
SSIDataGetNonBlocking(a, b)
#define SSIDataNonBlockingPut(a, b) \
SSIDataPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__

View File

@ -2,23 +2,38 @@
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -55,7 +70,10 @@ extern "C"
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#endif
#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
@ -98,11 +116,82 @@ extern "C"
#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
#define SYSCTL_PERIPH_ETH 0x20105000 // Ethernet
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0
#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1
#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0
#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1
#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2
#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
#define SYSCTL_PERIPH2_EPI0 0xf0001000 // EPI0
#define SYSCTL_PERIPH2_ETH 0xf0002c00 // ETH
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A
#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B
#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C
#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D
#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E
#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F
#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G
#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H
#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module
#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0
#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
#define SYSCTL_PERIPH2_I2S0 0xf0002400 // I2S0
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0
#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1
#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0
#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0
#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1
#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2
#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0
#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1
#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA
#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0
#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0
#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1
#define SYSCTL_PERIPH2_HIBERNATE \
0xf0001400 // Hibernate
//*****************************************************************************
//
@ -194,7 +283,9 @@ extern "C"
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
@ -393,16 +484,95 @@ extern "C"
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
//*****************************************************************************
//
// Prototypes for the APIs.
@ -412,6 +582,9 @@ extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
@ -437,8 +610,11 @@ extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);

View File

@ -2,23 +2,38 @@
//
// uart.c - Driver for the UART.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -49,6 +64,23 @@
(CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \
16 : 8)
//*****************************************************************************
//
// A mapping of UART base address to interupt number.
//
//*****************************************************************************
static const unsigned long g_ppulUARTIntMap[][2] =
{
{ UART0_BASE, INT_UART0 },
{ UART1_BASE, INT_UART1 },
{ UART2_BASE, INT_UART2 },
{ UART3_BASE, INT_UART3 },
{ UART4_BASE, INT_UART4 },
{ UART5_BASE, INT_UART5 },
{ UART6_BASE, INT_UART6 },
{ UART7_BASE, INT_UART7 },
};
//*****************************************************************************
//
//! \internal
@ -67,10 +99,55 @@ static tBoolean
UARTBaseValid(unsigned long ulBase)
{
return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
(ulBase == UART2_BASE));
(ulBase == UART2_BASE) || (ulBase == UART3_BASE) ||
(ulBase == UART4_BASE) || (ulBase == UART5_BASE) ||
(ulBase == UART6_BASE) || (ulBase == UART7_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the UART interrupt number.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Given a UART base address, this function returns the corresponding
//! interrupt number.
//!
//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
UARTIntNumberGet(unsigned long ulBase)
{
unsigned long ulIdx;
//
// Loop through the table that maps UART base addresses to interrupt
// numbers.
//
for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) /
sizeof(g_ppulUARTIntMap[0])); ulIdx++)
{
//
// See if this base address matches.
//
if(g_ppulUARTIntMap[ulIdx][0] == ulBase)
{
//
// Return the corresponding interrupt number.
//
return(g_ppulUARTIntMap[ulIdx][1]);
}
}
//
// The base address could not be found, so return an error.
//
return(-1);
}
//*****************************************************************************
//
//! Sets the type of parity.
@ -78,11 +155,12 @@ UARTBaseValid(unsigned long ulBase)
//! \param ulBase is the base address of the UART port.
//! \param ulParity specifies the type of parity to use.
//!
//! Sets the type of parity to use for transmitting and expect when receiving.
//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
//! parity bit; it is always either one or zero based on the mode.
//! This function configures the type of parity to use for transmitting and
//! expect when receiving. The \e ulParity parameter must be one of
//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two
//! parameters allow direct control of the parity bit; it is always either one
//! or zero based on the mode.
//!
//! \return None.
//
@ -149,8 +227,8 @@ UARTParityModeGet(unsigned long ulBase)
//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
//!
//! This function sets the FIFO level at which transmit and receive interrupts
//! are generated.
//! This function configures the FIFO level at which transmit and receive
//! interrupts are generated.
//!
//! \return None.
//
@ -245,10 +323,15 @@ UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
//! select the parity mode (no parity bit, even parity bit, odd parity bit,
//! parity bit always one, and parity bit always zero, respectively).
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//! The peripheral clock is the same as the processor clock. The frequency of
//! the system clock is the value returned by SysCtlClockGet(), or it can be
//! explicitly hard coded if it is constant and known (to save the
//! code/execution overhead of a call to SysCtlClockGet()).
//!
//! For Stellaris parts that have the ability to specify the UART baud clock
//! source (via UARTClockSourceSet()), the peripheral clock can be changed to
//! PIOSC. In this case, the peripheral clock should be specified as
//! 16,000,000 (the nominal rate of PIOSC).
//!
//! This function replaces the original UARTConfigSet() API and performs the
//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
@ -336,17 +419,22 @@ UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
//! \param pulBaud is a pointer to storage for the baud rate.
//! \param pulConfig is a pointer to storage for the data format.
//!
//! The baud rate and data format for the UART is determined, given an
//! explicitly provided peripheral clock (hence the ExpClk suffix). The
//! This function determines the baud rate and data format for the UART, given
//! an explicitly provided peripheral clock (hence the ExpClk suffix). The
//! returned baud rate is the actual baud rate; it may not be the exact baud
//! rate requested or an ``official'' baud rate. The data format returned in
//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
//! UARTConfigSetExpClk().
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//! The peripheral clock is the same as the processor clock. The frequency of
//! the system clock is the value returned by SysCtlClockGet(), or it can be
//! explicitly hard coded if it is constant and known (to save the
//! code/execution overhead of a call to SysCtlClockGet()).
//!
//! For Stellaris parts that have the ability to specify the UART baud clock
//! source (via UARTClockSourceSet()), the peripheral clock can be changed to
//! PIOSC. In this case, the peripheral clock should be specified as
//! 16,000,000 (the nominal rate of PIOSC).
//!
//! This function replaces the original UARTConfigGet() API and performs the
//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
@ -399,8 +487,8 @@ UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
//!
//! \param ulBase is the base address of the UART port.
//!
//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
//! FIFOs.
//! This function sets the UARTEN, TXE, and RXE bits and enables the transmit
//! and receive FIFOs.
//!
//! \return None.
//
@ -431,7 +519,7 @@ UARTEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of
//! transmission of the current character, and flushes the transmit FIFO.
//!
//! \return None.
@ -495,7 +583,7 @@ UARTFIFOEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! This functions disables the transmit and receive FIFOs in the UART.
//! This function disables the transmit and receive FIFOs in the UART.
//!
//! \return None.
//
@ -521,10 +609,18 @@ UARTFIFODisable(unsigned long ulBase)
//! \param ulBase is the base address of the UART port.
//! \param bLowPower indicates if SIR Low Power Mode is to be used.
//!
//! Enables the SIREN control bit for IrDA mode on the UART. If the
//! \e bLowPower flag is set, then SIRLP bit will also be set.
//! This function enables the SIREN control bit for IrDA mode on the UART. If
//! the \e bLowPower flag is set, then SIRLP bit is also set. This
//! function only has an effect if the UART has not been enabled
//! by a call to UARTEnable(). The call UARTEnableSIR() must be made before
//! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function
//! calls the UARTEnable() function. Another option is to call UARTDisable()
//! followed by UARTEnableSIR() and then enable the UART by calling
//! UARTEnable().
//!
//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
//! \note The availability of SIR (IrDA) operation varies with the Stellaris
//! part in use. Please consult the datasheet for the part you are using to
//! determine whether this support is available.
//!
//! \return None.
//
@ -556,9 +652,17 @@ UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
//! This function clears the SIREN (IrDA) and SIRLP (Low Power) bits. This
//! function only has an effect if the UART has not been enabled by a
//! call to UARTEnable(). The call UARTEnableSIR() must be made before
//! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function
//! calls the UARTEnable() function. Another option is to call UARTDisable()
//! followed by UARTEnableSIR() and then enable the UART by calling
//! UARTEnable().
//!
//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
//! \note The availability of SIR (IrDA) operation varies with the Stellaris
//! part in use. Please consult the datasheet for the part you are using to
//! determine whether this support is available.
//!
//! \return None.
//
@ -579,17 +683,17 @@ UARTDisableSIR(unsigned long ulBase)
//*****************************************************************************
//
//! Enables ISO 7816 smart card mode on the specified UART.
//! Enables ISO7816 smart card mode on the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Enables the SMART control bit for ISO 7816 smart card mode on the UART.
//! This call also sets 8 bit word length and even parity as required by ISO
//! 7816.
//! This function enables the SMART control bit for the ISO7816 smart card mode
//! on the UART. This call also sets 8-bit word length and even parity as
//! required by ISO7816.
//!
//! \note The availability of ISO 7816 smart card mode varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//! \note The availability of SIR (IrDA) operation varies with the Stellaris
//! part in use. Please consult the datasheet for the part you are using to
//! determine whether this support is available.
//!
//! \return None.
//
@ -606,9 +710,9 @@ UARTSmartCardEnable(unsigned long ulBase)
ASSERT(UARTBaseValid(ulBase));
//
// Set 8 bit word length, even parity, 2 stop bits (even though the STP2
// bit is ignored when in smartcard mode, this lets the caller read back
// the actual setting in use).
// Set 8-bit word length, even parity, 2 stop bits (note that although the
// STP2 bit is ignored when in smartcard mode, this code lets the caller
// read back the actual setting in use).
//
ulVal = HWREG(ulBase + UART_O_LCRH);
ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
@ -624,15 +728,16 @@ UARTSmartCardEnable(unsigned long ulBase)
//*****************************************************************************
//
//! Disables ISO 7816 smart card mode on the specified UART.
//! Disables ISO7816 smart card mode on the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Clears the SMART (ISO 7816 smart card) bits in the UART control register.
//! This function clears the SMART (ISO7816 smart card) bit in the UART
//! control register.
//!
//! \note The availability of ISO 7816 smart card mode varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//! \note The availability of ISO7816 smart card mode varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return None.
//
@ -660,16 +765,17 @@ UARTSmartCardDisable(unsigned long ulBase)
//! \param ulControl is a bit-mapped flag indicating which modem control bits
//! should be set.
//!
//! Sets the states of the DTR or RTS modem handshake outputs from the UART.
//! This function configures the states of the DTR or RTS modem handshake
//! outputs from the UART.
//!
//! The \e ulControl parameter is the logical OR of any of the following:
//!
//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
//!
//! \note The availability of hardware modem handshake signals varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//! \note The availability of ISO7816 smart card mode varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return None.
//
@ -702,7 +808,8 @@ UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
//! \param ulControl is a bit-mapped flag indicating which modem control bits
//! should be set.
//!
//! Clears the states of the DTR or RTS modem handshake outputs from the UART.
//! This function clears the states of the DTR or RTS modem handshake outputs
//! from the UART.
//!
//! The \e ulControl parameter is the logical OR of any of the following:
//!
@ -742,15 +849,15 @@ UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Returns the current states of each of the two UART modem control signals,
//! DTR and RTS.
//! This function returns the current states of each of the two UART modem
//! control signals, DTR and RTS.
//!
//! \note The availability of hardware modem handshake signals varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//!
//! \return Returns the states of the handshake output signals. This will be a
//! logical logical OR combination of values \b UART_OUTPUT_RTS and
//! \return Returns the states of the handshake output signals. This value is
//! a logical OR combination of values \b UART_OUTPUT_RTS and
//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
//! associated signal is asserted.
//
@ -773,16 +880,16 @@ UARTModemControlGet(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Returns the current states of each of the four UART modem status signals,
//! RI, DCD, DSR and CTS.
//! This function returns the current states of each of the four UART modem
//! status signals, RI, DCD, DSR and CTS.
//!
//! \note The availability of hardware modem handshake signals varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//!
//! \return Returns the states of the handshake output signals. This will be a
//! logical logical OR combination of values \b UART_INPUT_RI, \b
//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
//! \return Returns the states of the handshake output signals. This value
//! is a logical OR combination of values \b UART_INPUT_RI,
//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
//! presence of each flag indicates that the associated signal is asserted.
//
//*****************************************************************************
@ -804,17 +911,18 @@ UARTModemStatusGet(unsigned long ulBase)
//! Sets the UART hardware flow control mode to be used.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulMode indicates the flow control modes to be used. This is a
//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b
//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
//! \param ulMode indicates the flow control modes to be used. This parameter
//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and
//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
//!
//! Sets the required hardware flow control modes. If \e ulMode contains
//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS
//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX,
//! the RTS output is controlled by the hardware and is asserted only when
//! there is space available in the receive FIFO. If no hardware flow control
//! is required, UART_FLOWCONTROL_NONE should be passed.
//! This function configures the required hardware flow control modes. If
//! \e ulMode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted
//! if the incoming CTS signal is asserted. If \e ulMode contains flag
//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is
//! asserted only when there is space available in the receive FIFO. If no
//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be
//! passed.
//!
//! \note The availability of hardware flow control varies with the Stellaris
//! part and UART in use. Please consult the datasheet for the part you are
@ -847,17 +955,17 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Returns the current hardware flow control mode.
//! This function returns the current hardware flow control mode.
//!
//! \note The availability of hardware flow control varies with the Stellaris
//! part and UART in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return Returns the current flow control mode in use. This is a
//! \return Returns the current flow control mode in use. This value is a
//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
//! flow control is in use. If hardware flow control is disabled, \b
//! UART_FLOWCONTROL_NONE will be returned.
//! flow control is in use. If hardware flow control is disabled,
//! \b UART_FLOWCONTROL_NONE is returned.
//
//*****************************************************************************
unsigned long
@ -887,9 +995,9 @@ UARTFlowControlGet(unsigned long ulBase)
//! default, the transmit interrupt is asserted when the FIFO level falls past
//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
//! transmit interrupt will only be asserted once the transmitter is completely
//! idle - the transmit FIFO is empty and all bits, including any stop bits,
//! have cleared the transmitter.
//! transmit interrupt is asserted once the transmitter is completely idle -
//! the transmit FIFO is empty and all bits, including any stop bits, have
//! cleared the transmitter.
//!
//! \note The availability of end-of-transmission mode varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
@ -923,12 +1031,12 @@ UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
//! \param ulBase is the base address of the UART port.
//!
//! This function returns the current operating mode for the UART transmit
//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the
//! transmit interrupt is currently set to be asserted once the transmitter is
//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit
//! interrupt is currently configured to be asserted once the transmitter is
//! completely idle - the transmit FIFO is empty and all bits, including any
//! stop bits, have cleared the transmitter. The return value will be \b
//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
//! level of the transmit FIFO.
//! stop bits, have cleared the transmitter. The return value is
//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based
//! on the level of the transmit FIFO.
//!
//! \note The availability of end-of-transmission mode varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
@ -1012,7 +1120,8 @@ UARTSpaceAvail(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Gets a character from the receive FIFO for the specified port.
//! This function gets a character from the receive FIFO for the specified
//! port.
//!
//! This function replaces the original UARTCharNonBlockingGet() API and
//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
@ -1057,9 +1166,9 @@ UARTCharGetNonBlocking(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Gets a character from the receive FIFO for the specified port. If there
//! are no characters available, this function waits until a character is
//! received before returning.
//! This function gets a character from the receive FIFO for the specified
//! port. If there are no characters available, this function waits until a
//! character is received before returning.
//!
//! \return Returns the character read from the specified port, cast as a
//! \e long.
@ -1093,9 +1202,10 @@ UARTCharGet(unsigned long ulBase)
//! \param ulBase is the base address of the UART port.
//! \param ucData is the character to be transmitted.
//!
//! Writes the character \e ucData to the transmit FIFO for the specified port.
//! This function does not block, so if there is no space available, then a
//! \b false is returned, and the application must retry the function later.
//! This function writes the character \e ucData to the transmit FIFO for the
//! specified port. This function does not block, so if there is no space
//! available, then a \b false is returned and the application must retry the
//! function later.
//!
//! This function replaces the original UARTCharNonBlockingPut() API and
//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
@ -1145,9 +1255,9 @@ UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
//! \param ulBase is the base address of the UART port.
//! \param ucData is the character to be transmitted.
//!
//! Sends the character \e ucData to the transmit FIFO for the specified port.
//! If there is no space available in the transmit FIFO, this function waits
//! until there is space available before returning.
//! This function sends the character \e ucData to the transmit FIFO for the
//! specified port. If there is no space available in the transmit FIFO, this
//! function waits until there is space available before returning.
//!
//! \return None.
//
@ -1211,10 +1321,10 @@ UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Allows the caller to determine whether all transmitted bytes have cleared
//! the transmitter hardware. If \b false is returned, the transmit FIFO is
//! empty and all bits of the last transmitted character, including all stop
//! bits, have left the hardware shift register.
//! This function allows the caller to determine whether all transmitted bytes
//! have cleared the transmitter hardware. If \b false is returned, the
//! transmit FIFO is empty and all bits of the last transmitted character,
//! including all stop bits, have left the hardware shift register.
//!
//! \return Returns \b true if the UART is transmitting or \b false if all
//! transmissions are complete.
@ -1243,8 +1353,8 @@ UARTBusy(unsigned long ulBase)
//! UART interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; specific UART
//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
//! function enables the global interrupt in the interrupt controller; specific
//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
@ -1266,8 +1376,7 @@ UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//
// Determine the interrupt number based on the UART port.
//
ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
ulInt = UARTIntNumberGet(ulBase);
//
// Register the interrupt handler.
@ -1287,9 +1396,9 @@ UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//! \param ulBase is the base address of the UART port.
//!
//! This function does the actual unregistering of the interrupt handler. It
//! will clear the handler to be called when a UART interrupt occurs. This
//! will also mask off the interrupt in the interrupt controller so that the
//! interrupt handler no longer is called.
//! clears the handler to be called when a UART interrupt occurs. This
//! function also masks off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -1310,8 +1419,7 @@ UARTIntUnregister(unsigned long ulBase)
//
// Determine the interrupt number based on the UART port.
//
ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
ulInt = UARTIntNumberGet(ulBase);
//
// Disable the interrupt.
@ -1331,12 +1439,13 @@ UARTIntUnregister(unsigned long ulBase)
//! \param ulBase is the base address of the UART port.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated UART interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//! This function enables the indicated UART interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b UART_INT_9BIT - 9-bit Address Match interrupt
//! - \b UART_INT_OE - Overrun Error interrupt
//! - \b UART_INT_BE - Break Error interrupt
//! - \b UART_INT_PE - Parity Error interrupt
@ -1373,9 +1482,9 @@ UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ulBase is the base address of the UART port.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated UART interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//! This function disables the indicated UART interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to UARTIntEnable().
@ -1405,9 +1514,9 @@ UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the specified UART. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//! This function returns the interrupt status for the specified UART. Either
//! the raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in UARTIntEnable().
@ -1444,12 +1553,12 @@ UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
//!
//! The specified UART interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being recognized again immediately upon exit.
//! interrupt from being triggered again immediately upon exit.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to UARTIntEnable().
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
@ -1483,7 +1592,7 @@ UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
//!
//! The specified UART DMA features are enabled. The UART can be
//! configured to use DMA for transmit or receive, and to disable
//! configured to use DMA for transmit or receive and to disable
//! receive if an error occurs. The \e ulDMAFlags parameter is the
//! logical OR of any of the following values:
//!
@ -1552,8 +1661,8 @@ UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
//! This function returns the current state of each of the 4 receiver error
//! sources. The returned errors are equivalent to the four error bits
//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
//! with the exception that the overrun error is set immediately the overrun
//! occurs rather than when a character is next read.
//! with the exception that the overrun error is set immediately when the
//! overrun occurs rather than when a character is next read.
//!
//! \return Returns a logical OR combination of the receiver error flags,
//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
@ -1597,12 +1706,240 @@ UARTRxErrorClear(unsigned long ulBase)
ASSERT(UARTBaseValid(ulBase));
//
// Any write to the Error Clear Register will clear all bits which are
// Any write to the Error Clear Register clears all bits which are
// currently set.
//
HWREG(ulBase + UART_O_ECR) = 0;
}
//*****************************************************************************
//
//! Sets the baud clock source for the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulSource is the baud clock source for the UART.
//!
//! This function allows the baud clock source for the UART to be selected.
//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b UART_CLOCK_PIOSC).
//!
//! Changing the baud clock source changes the baud rate generated by the
//! UART. Therefore, the baud rate should be reconfigured after any change to
//! the baud clock source.
//!
//! \note The ability to specify the UART baud clock source varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
ASSERT((ulSource == UART_CLOCK_SYSTEM) || (ulSource == UART_CLOCK_PIOSC));
//
// Set the UART clock source.
//
HWREG(ulBase + UART_O_CC) = ulSource;
}
//*****************************************************************************
//
//! Gets the baud clock source for the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function returns the baud clock source for the specified UART. The
//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b UART_CLOCK_PIOSC).
//!
//! \note The ability to specify the UART baud clock source varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
UARTClockSourceGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Return the UART clock source.
//
return(HWREG(ulBase + UART_O_CC));
}
//*****************************************************************************
//
//! Enables 9-bit mode on the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function enables the 9-bit operational mode of the UART.
//!
//! \note The availability of 9-bit mode varies with the Stellaris part in use.
//! Please consult the datasheet for the part you are using to determine
//! whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UART9BitEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Enable 9-bit mode.
//
HWREG(ulBase + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN;
}
//*****************************************************************************
//
//! Disables 9-bit mode on the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function disables the 9-bit operational mode of the UART.
//!
//! \note The availability of 9-bit mode varies with the Stellaris part in use.
//! Please consult the datasheet for the part you are using to determine
//! whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UART9BitDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Disable 9-bit mode.
//
HWREG(ulBase + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN;
}
//*****************************************************************************
//
//! Sets the device address(es) for 9-bit mode.
//!
//! \param ulBase is the base address of the UART port.
//! \param ucAddr is the device address.
//! \param ucMask is the device address mask.
//!
//! This function configures the device address or range of device addresses
//! that respond to requests on the 9-bit UART port. The received address is
//! masked with the mask and then compared against the given address, allowing
//! either a single address (if \b ucMask is 0xff) or a set of addresses to be
//! matched.
//!
//! \note The availability of 9-bit mode varies with the Stellaris part in use.
//! Please consult the datasheet for the part you are using to determine
//! whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
unsigned char ucMask)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Set the address and mask.
//
HWREG(ulBase + UART_O_9BITADDR) = ucAddr << UART_9BITADDR_ADDR_S;
HWREG(ulBase + UART_O_9BITAMASK) = ucMask << UART_9BITAMASK_MASK_S;
}
//*****************************************************************************
//
//! Sends an address character from the specified port when operating in 9-bit
//! mode.
//!
//! \param ulBase is the base address of the UART port.
//! \param ucAddr is the address to be transmitted.
//!
//! This function waits until all data has been sent from the specified port
//! and then sends the given address as an address byte. It then waits until
//! the address byte has been transmitted before returning.
//!
//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(),
//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive
//! data characters in 9-bit mode.
//!
//! \note The availability of 9-bit mode varies with the Stellaris part in use.
//! Please consult the datasheet for the part you are using to determine
//! whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr)
{
unsigned long ulLCRH;
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Wait until the FIFO is empty and the UART is not busy.
//
while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY))
{
}
//
// Force the address/data bit to 1 to indicate this is an address byte.
//
ulLCRH = HWREG(ulBase + UART_O_LCRH);
HWREG(ulBase + UART_O_LCRH) = ((ulLCRH & ~UART_LCRH_EPS) | UART_LCRH_SPS |
UART_LCRH_PEN);
//
// Send the address.
//
HWREG(ulBase + UART_O_DR) = ucAddr;
//
// Wait until the address has been sent.
//
while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY))
{
}
//
// Restore the address/data setting.
//
HWREG(ulBase + UART_O_LCRH) = ulLCRH;
}
//*****************************************************************************
//
// Close the Doxygen group.

View File

@ -2,23 +2,38 @@
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -42,6 +57,7 @@ extern "C"
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
@ -159,6 +175,15 @@ extern "C"
#define UART_TXINT_MODE_FIFO 0x00000000
#define UART_TXINT_MODE_EOT 0x00000010
//*****************************************************************************
//
// Values that can be passed to UARTClockSourceSet() or returned from
// UARTClockSourceGet().
//
//*****************************************************************************
#define UART_CLOCK_SYSTEM 0x00000000
#define UART_CLOCK_PIOSC 0x00000005
//*****************************************************************************
//
// API Function prototypes
@ -212,6 +237,13 @@ extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long UARTClockSourceGet(unsigned long ulBase);
extern void UART9BitEnable(unsigned long ulBase);
extern void UART9BitDisable(unsigned long ulBase);
extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
unsigned char ucMask);
extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr);
//*****************************************************************************
//

View File

@ -0,0 +1,192 @@
/*---------------------------------------------------------------------------/
/ FatFs - FAT file system module configuration file R0.09b (C)ChaN, 2013
/----------------------------------------------------------------------------/
/
/ CAUTION! Do not forget to make clean the project after any changes to
/ the configuration options.
/
/----------------------------------------------------------------------------*/
#ifndef _FFCONF
#define _FFCONF 82786 /* Revision ID */
/*---------------------------------------------------------------------------/
/ Functions and Buffer Configurations
/----------------------------------------------------------------------------*/
#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
/ object instead of the sector buffer in the individual file object for file
/ data transfer. This reduces memory consumption 512 bytes each file object. */
#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
/* Setting _FS_READONLY to 1 defines read only configuration. This removes
/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
/ f_truncate and useless f_getfree. */
#define _FS_MINIMIZE 0 /* 0 to 3 */
/* The _FS_MINIMIZE option defines minimization level to remove some functions.
/
/ 0: Full function.
/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
/ are removed.
/ 2: f_opendir and f_readdir are removed in addition to 1.
/ 3: f_lseek is removed in addition to 2. */
#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */
/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
#define _USE_MKFS 0 /* 0:Disable or 1:Enable */
/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
#define _USE_LABEL 0 /* 0:Disable or 1:Enable */
/* To enable volume label functions, set _USE_LAVEL to 1 */
#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
/*---------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/----------------------------------------------------------------------------*/
#define _CODE_PAGE 437
/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
/ Incorrect setting of the code page can cause a file open failure.
/
/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
/ 949 - Korean (DBCS, OEM, Windows)
/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
/ 1250 - Central Europe (Windows)
/ 1251 - Cyrillic (Windows)
/ 1252 - Latin 1 (Windows)
/ 1253 - Greek (Windows)
/ 1254 - Turkish (Windows)
/ 1255 - Hebrew (Windows)
/ 1256 - Arabic (Windows)
/ 1257 - Baltic (Windows)
/ 1258 - Vietnam (OEM, Windows)
/ 437 - U.S. (OEM)
/ 720 - Arabic (OEM)
/ 737 - Greek (OEM)
/ 775 - Baltic (OEM)
/ 850 - Multilingual Latin 1 (OEM)
/ 858 - Multilingual Latin 1 + Euro (OEM)
/ 852 - Latin 2 (OEM)
/ 855 - Cyrillic (OEM)
/ 866 - Russian (OEM)
/ 857 - Turkish (OEM)
/ 862 - Hebrew (OEM)
/ 874 - Thai (OEM, Windows)
/ 1 - ASCII only (Valid for non LFN cfg.)
*/
#define _USE_LFN 1 /* 0 to 3 */
#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
/* The _USE_LFN option switches the LFN support.
/
/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
/ Unicode handling functions ff_convert() and ff_wtoupper() must be added
/ to the project. When enable to use heap, memory control functions
/ ff_memalloc() and ff_memfree() must be added to the project. */
#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
/* To switch the character code set on FatFs API to Unicode,
/ enable LFN feature and set _LFN_UNICODE to 1. */
#define _FS_RPATH 0 /* 0 to 2 */
/* The _FS_RPATH option configures relative path feature.
/
/ 0: Disable relative path feature and remove related functions.
/ 1: Enable relative path. f_chdrive() and f_chdir() are available.
/ 2: f_getcwd() is available in addition to 1.
/
/ Note that output of the f_readdir fnction is affected by this option. */
/*---------------------------------------------------------------------------/
/ Physical Drive Configurations
/----------------------------------------------------------------------------*/
#define _VOLUMES 1
/* Number of volumes (logical drives) to be used. */
#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
/* Maximum sector size to be handled.
/ Always set 512 for memory card and hard disk but a larger value may be
/ required for on-board flash memory, floppy disk and optical disk.
/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size
/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Enable multiple partition */
/* When set to 0, each volume is bound to the same physical drive number and
/ it can mount only first primaly partition. When it is set to 1, each volume
/ is tied to the partitions listed in VolToPart[]. */
#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
/ should be added to the disk_ioctl functio. */
/*---------------------------------------------------------------------------/
/ System Configurations
/----------------------------------------------------------------------------*/
#define _WORD_ACCESS 0 /* 0 or 1 */
/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
/ option defines which access method is used to the word data on the FAT volume.
/
/ 0: Byte-by-byte access.
/ 1: Word access. Do not choose this unless following condition is met.
/
/ When the byte order on the memory is big-endian or address miss-aligned word
/ access results incorrect behavior, the _WORD_ACCESS must be set to 0.
/ If it is not the case, the value can also be set to 1 to improve the
/ performance and code size.
*/
/* A header file that defines sync object types on the O/S, such as
/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
/
/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
/ 1: Enable reentrancy. Also user provided synchronization handlers,
/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
/ function must be added to the project. */
#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
/* To enable file lock control feature, set _FS_LOCK to 1 or greater.
The value defines how many files can be opened simultaneously. */
#endif /* _FFCONFIG */

View File

@ -0,0 +1,672 @@
/*------------------------------------------------------------------------/
/ MMCv3/SDv1/SDv2 (in SPI mode) control module
/-------------------------------------------------------------------------/
/
/ Copyright (C) 2013, ChaN, all right reserved.
/
/ * This software is a free software and there is NO WARRANTY.
/ * No restriction on use. You can use, modify and redistribute it for
/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
/ * Redistributions of source code must retain the above copyright notice.
/
/-------------------------------------------------------------------------*/
/*
* This file was modified from a sample available from the FatFs
* web site. It was modified to work with a Stellaris EK-LM3S6965
* evaluation board.
*
* Note that the SSI port is shared with the osram display. The code
* in this file does not attempt to share the SSI port with the osram,
* it assumes the osram is not being used.
*/
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/gpio.h"
#include "driverlib/ssi.h"
#include "driverlib/sysctl.h"
#include "diskio.h"
#include "boot.h"
/*--------------------------------------------------------------------------
Module Private Functions
---------------------------------------------------------------------------*/
/* Definitions for MMC/SDC command */
#define CMD0 (0) /* GO_IDLE_STATE */
#define CMD1 (1) /* SEND_OP_COND */
#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */
#define CMD8 (8) /* SEND_IF_COND */
#define CMD9 (9) /* SEND_CSD */
#define CMD10 (10) /* SEND_CID */
#define CMD12 (12) /* STOP_TRANSMISSION */
#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */
#define CMD16 (16) /* SET_BLOCKLEN */
#define CMD17 (17) /* READ_SINGLE_BLOCK */
#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
#define CMD23 (23) /* SET_BLOCK_COUNT */
#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24 (24) /* WRITE_BLOCK */
#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
#define CMD41 (41) /* SEND_OP_COND (ACMD) */
#define CMD55 (55) /* APP_CMD */
#define CMD58 (58) /* READ_OCR */
/* Peripheral definitions for EK-LM3S6965 board */
// SSI port
#define SDC_SSI_BASE SSI0_BASE
#define SDC_SSI_SYSCTL_PERIPH SYSCTL_PERIPH_SSI0
// GPIO for SSI pins
#define SDC_GPIO_PORT_BASE GPIO_PORTA_BASE
#define SDC_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOA
#define SDC_SSI_CLK GPIO_PIN_2
#define SDC_SSI_TX GPIO_PIN_5
#define SDC_SSI_RX GPIO_PIN_4
#define SDC_SSI_FSS GPIO_PIN_3
#define SDC_SSI_PINS (SDC_SSI_TX | SDC_SSI_RX | SDC_SSI_CLK)
// GPIO for card chip select
#define SDC_CS_GPIO_PORT_BASE GPIO_PORTD_BASE
#define SDC_CS_GPIO_SYSCTL_PERIPH SYSCTL_PERIPH_GPIOD
#define SDC_CS GPIO_PIN_0
/* Control signals (Platform dependent) */
#define CS_LOW() GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, 0) /* MMC CS = L */
#define CS_HIGH() GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS) /* MMC CS = H */
#define FCLK_SLOW() /* Set slow clock (100k-400k) */
#define FCLK_FAST() set_max_speed() /* Set fast clock (depends on the CSD) */
static volatile
DSTATUS Stat = STA_NOINIT; /* Disk status */
static
UINT CardType;
/*-----------------------------------------------------------------------*/
/* Send 80 or so clock transitions with CS and DI held high. This is */
/* required after card power up to get it into SPI mode */
/*-----------------------------------------------------------------------*/
static
void send_initial_clock_train(void)
{
unsigned int i;
DWORD dat;
/* Ensure CS is held high. */
CS_HIGH();
/* Switch the SSI TX line to a GPIO and drive it high too. */
GPIOPinTypeGPIOOutput(SDC_GPIO_PORT_BASE, SDC_SSI_TX);
GPIOPinWrite(SDC_GPIO_PORT_BASE, SDC_SSI_TX, SDC_SSI_TX);
/* Send 10 bytes over the SSI. This causes the clock to wiggle the */
/* required number of times. */
for(i = 0 ; i < 10 ; i++)
{
/* Write DUMMY data. SSIDataPut() waits until there is room in the */
/* FIFO. */
SSIDataPut(SDC_SSI_BASE, 0xFF);
/* Flush data read during data write. */
SSIDataGet(SDC_SSI_BASE, &dat);
}
/* Revert to hardware control of the SSI TX line. */
GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_TX);
}
/*-----------------------------------------------------------------------*/
/* Power Control (Platform dependent) */
/*-----------------------------------------------------------------------*/
/* When the target system does not support socket power control, there */
/* is nothing to do in these functions. */
static
void power_on (void)
{
/*
* This doesn't really turn the power on, but initializes the
* SSI port and pins needed to talk to the card.
*/
/* Enable the peripherals used to drive the SDC on SSI, and the CS */
SysCtlPeripheralEnable(SDC_SSI_SYSCTL_PERIPH);
SysCtlPeripheralEnable(SDC_GPIO_SYSCTL_PERIPH);
SysCtlPeripheralEnable(SDC_CS_GPIO_SYSCTL_PERIPH);
/* Configure the appropriate pins to be SSI instead of GPIO */
GPIOPinTypeSSI(SDC_GPIO_PORT_BASE, SDC_SSI_PINS);
GPIOPinTypeGPIOOutput(SDC_CS_GPIO_PORT_BASE, SDC_CS);
GPIOPadConfigSet(SDC_GPIO_PORT_BASE, SDC_SSI_PINS, GPIO_STRENGTH_4MA,
GPIO_PIN_TYPE_STD_WPU);
GPIOPadConfigSet(SDC_CS_GPIO_PORT_BASE, SDC_CS, GPIO_STRENGTH_4MA,
GPIO_PIN_TYPE_STD_WPU);
/* Deassert the SSI0 chip select */
GPIOPinWrite(SDC_CS_GPIO_PORT_BASE, SDC_CS, SDC_CS);
/* Configure the SSI0 port */
SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 400000, 8);
SSIEnable(SDC_SSI_BASE);
/* Set DI and CS high and apply more than 74 pulses to SCLK for the card */
/* to be able to accept a native command. */
send_initial_clock_train();
}
// set the SSI speed to the max setting
static
void set_max_speed(void)
{
unsigned long i;
/* Disable the SSI */
SSIDisable(SDC_SSI_BASE);
/* Set the maximum speed as half the system clock, with a max of 12.5 MHz. */
i = SysCtlClockGet() / 2;
if(i > 12500000)
{
i = 12500000;
}
/* Configure the SSI0 port */
SSIConfigSetExpClk(SDC_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, i, 8);
/* Enable the SSI */
SSIEnable(SDC_SSI_BASE);
}
static
void power_off (void)
{
Stat |= STA_NOINIT; /* Force uninitialized */
}
/*-----------------------------------------------------------------------*/
/* Transmit/Receive data to/from MMC via SPI (Platform dependent) */
/*-----------------------------------------------------------------------*/
static
BYTE xchg_spi (BYTE dat)
{
DWORD rcvdat;
SSIDataPut(SDC_SSI_BASE, dat); /* write data */
SSIDataGet(SDC_SSI_BASE, &rcvdat); /* read data frm rx fifo */
return (BYTE)rcvdat;
}
static
void rcvr_spi_m (BYTE *dst)
{
*dst = xchg_spi(0xFF);
}
/*-----------------------------------------------------------------------*/
/* Wait for card ready */
/*-----------------------------------------------------------------------*/
static
int wait_ready (void)
{
BYTE d;
ULONG timeOutTime;
/* set timeout for 500 ms from now */
timeOutTime = TimerGet() + 500;
do {
d = xchg_spi(0xFF);
} while ((d != 0xFF) && (TimerGet() < timeOutTime));
return (d == 0xFF) ? 1 : 0;
}
/*-----------------------------------------------------------------------*/
/* Deselect the card and release SPI bus */
/*-----------------------------------------------------------------------*/
static
void deselect (void)
{
CS_HIGH();
xchg_spi(0xFF); /* Dummy clock (force DO hi-z for multiple slave SPI) */
}
/*-----------------------------------------------------------------------*/
/* Select the card and wait ready */
/*-----------------------------------------------------------------------*/
static
int select (void) /* 1:Successful, 0:Timeout */
{
CS_LOW();
xchg_spi(0xFF); /* Dummy clock (force DO enabled) */
if (wait_ready()) return 1; /* OK */
deselect();
return 0; /* Timeout */
}
/*-----------------------------------------------------------------------*/
/* Receive a data packet from MMC */
/*-----------------------------------------------------------------------*/
static
int rcvr_datablock ( /* 1:OK, 0:Failed */
BYTE *buff, /* Data buffer to store received data */
UINT btr /* Byte count (must be multiple of 4) */
)
{
BYTE token;
ULONG timeOutTime;
/* set timeout for 100 ms from now */
timeOutTime = TimerGet() + 100;
do { /* Wait for data packet in timeout of 100ms */
token = xchg_spi(0xFF);
} while ((token == 0xFF) && (TimerGet() < timeOutTime));
if(token != 0xFE) return 0; /* If not valid data token, retutn with error */
do { /* Receive the data block into buffer */
rcvr_spi_m(buff++);
rcvr_spi_m(buff++);
} while (btr -= 2);
xchg_spi(0xFF); /* Discard CRC */
xchg_spi(0xFF);
return 1; /* Return with success */
}
/*-----------------------------------------------------------------------*/
/* Send a data packet to MMC */
/*-----------------------------------------------------------------------*/
#if _USE_WRITE
static
int xmit_datablock ( /* 1:OK, 0:Failed */
const BYTE *buff, /* 512 byte data block to be transmitted */
BYTE token /* Data token */
)
{
BYTE resp;
UINT wc;
if (!wait_ready()) return 0;
xchg_spi(token); /* Xmit a token */
if (token != 0xFD) { /* Not StopTran token */
wc = 512;
do { /* Xmit the 512 byte data block to MMC */
xchg_spi(*buff++);
xchg_spi(*buff++);
} while (wc -= 2);
xchg_spi(0xFF); /* CRC (Dummy) */
xchg_spi(0xFF);
resp = xchg_spi(0xFF); /* Receive a data response */
if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */
return 0;
}
return 1;
}
#endif
/*-----------------------------------------------------------------------*/
/* Send a command packet to MMC */
/*-----------------------------------------------------------------------*/
static
BYTE send_cmd (
BYTE cmd, /* Command byte */
DWORD arg /* Argument */
)
{
BYTE n, res;
if (cmd & 0x80) { /* ACMD<n> is the command sequense of CMD55-CMD<n> */
cmd &= 0x7F;
res = send_cmd(CMD55, 0);
if (res > 1) return res;
}
/* Select the card and wait for ready */
deselect();
if (!select()) return 0xFF;
/* Send command packet */
xchg_spi(0x40 | cmd); /* Start + Command index */
xchg_spi((BYTE)(arg >> 24)); /* Argument[31..24] */
xchg_spi((BYTE)(arg >> 16)); /* Argument[23..16] */
xchg_spi((BYTE)(arg >> 8)); /* Argument[15..8] */
xchg_spi((BYTE)arg); /* Argument[7..0] */
n = 0x01; /* Dummy CRC + Stop */
if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) + Stop */
if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) + Stop */
xchg_spi(n);
/* Receive command response */
if (cmd == CMD12) xchg_spi(0xFF); /* Skip a stuff byte on stop to read */
n = 10; /* Wait for a valid response in timeout of 10 attempts */
do
res = xchg_spi(0xFF);
while ((res & 0x80) && --n);
return res; /* Return with the response value */
}
/*--------------------------------------------------------------------------
Public Functions
---------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------*/
/* Initialize Disk Drive */
/*-----------------------------------------------------------------------*/
DSTATUS disk_initialize (
BYTE pdrv /* Physical drive nmuber (0) */
)
{
BYTE n, cmd, ty, ocr[4];
ULONG timeOutTime;
if (pdrv) return STA_NOINIT; /* Supports only single drive */
if (Stat & STA_NODISK) return Stat; /* No card in the socket */
power_on(); /* Force socket power on */
CS_LOW(); /* CS = L */
ty = 0;
if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */
timeOutTime = TimerGet() + 1000; /* Initialization timeout of 1000 msec */
if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */
for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); /* Get trailing return value of R7 resp */
if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */
while ((TimerGet() < timeOutTime) && send_cmd(ACMD41, 0x40000000)); /* Wait for leaving idle state (ACMD41 with HCS bit) */
if ((TimerGet() < timeOutTime) && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */
for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF);
ty = (ocr[0] & 0x40) ? CT_SD2|CT_BLOCK : CT_SD2; /* SDv2 */
}
}
} else { /* SDv1 or MMCv3 */
if (send_cmd(ACMD41, 0) <= 1) {
ty = CT_SD1; cmd = ACMD41; /* SDv1 */
} else {
ty = CT_MMC; cmd = CMD1; /* MMCv3 */
}
while ((TimerGet() < timeOutTime) && send_cmd(cmd, 0)); /* Wait for leaving idle state */
if (!(TimerGet() < timeOutTime) || send_cmd(CMD16, 512) != 0) /* Set read/write block length to 512 */
ty = 0;
}
}
CardType = ty;
deselect();
if (ty) { /* Initialization succeded */
Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */
FCLK_FAST();
} else { /* Initialization failed */
power_off();
}
return Stat;
}
/*-----------------------------------------------------------------------*/
/* Get Disk Status */
/*-----------------------------------------------------------------------*/
DSTATUS disk_status (
BYTE pdrv /* Physical drive nmuber (0) */
)
{
if (pdrv) return STA_NOINIT; /* Supports only single drive */
return Stat;
}
/*-----------------------------------------------------------------------*/
/* Read Sector(s) */
/*-----------------------------------------------------------------------*/
DRESULT disk_read (
BYTE pdrv, /* Physical drive nmuber (0) */
BYTE *buff, /* Pointer to the data buffer to store read data */
DWORD sector, /* Start sector number (LBA) */
BYTE count /* Sector count (1..255) */
)
{
if (pdrv || !count) return RES_PARERR;
if (Stat & STA_NOINIT) return RES_NOTRDY;
if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */
if (count == 1) { /* Single block read */
if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */
&& rcvr_datablock(buff, 512))
count = 0;
}
else { /* Multiple block read */
if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */
do {
if (!rcvr_datablock(buff, 512)) break;
buff += 512;
} while (--count);
send_cmd(CMD12, 0); /* STOP_TRANSMISSION */
}
}
deselect();
return count ? RES_ERROR : RES_OK;
}
/*-----------------------------------------------------------------------*/
/* Write Sector(s) */
/*-----------------------------------------------------------------------*/
#if _USE_WRITE
DRESULT disk_write (
BYTE pdrv, /* Physical drive nmuber (0) */
const BYTE *buff, /* Pointer to the data to be written */
DWORD sector, /* Start sector number (LBA) */
BYTE count /* Sector count (1..255) */
)
{
if (pdrv || !count) return RES_PARERR;
if (Stat & STA_NOINIT) return RES_NOTRDY;
if (Stat & STA_PROTECT) return RES_WRPRT;
if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */
if (count == 1) { /* Single block write */
if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */
&& xmit_datablock(buff, 0xFE))
count = 0;
}
else { /* Multiple block write */
if (CardType & CT_SDC) send_cmd(ACMD23, count);
if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */
do {
if (!xmit_datablock(buff, 0xFC)) break;
buff += 512;
} while (--count);
if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */
count = 1;
}
}
deselect();
return count ? RES_ERROR : RES_OK;
}
#endif
/*-----------------------------------------------------------------------*/
/* Miscellaneous Functions */
/*-----------------------------------------------------------------------*/
#if _USE_IOCTL
DRESULT disk_ioctl (
BYTE pdrv, /* Physical drive nmuber (0) */
BYTE cmd, /* Control code */
void *buff /* Buffer to send/receive data block */
)
{
DRESULT res;
BYTE n, csd[16], *ptr = buff;
DWORD csz;
if (pdrv) return RES_PARERR;
if (Stat & STA_NOINIT) return RES_NOTRDY;
res = RES_ERROR;
switch (cmd) {
case CTRL_SYNC : /* Flush write-back cache, Wait for end of internal process */
if (select()) res = RES_OK;
break;
case GET_SECTOR_COUNT : /* Get number of sectors on the disk (WORD) */
if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) {
if ((csd[0] >> 6) == 1) { /* SDv2? */
csz = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1;
*(DWORD*)buff = csz << 10;
} else { /* SDv1 or MMCv3 */
n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
csz = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1;
*(DWORD*)buff = csz << (n - 9);
}
res = RES_OK;
}
break;
case GET_BLOCK_SIZE : /* Get erase block size in unit of sectors (DWORD) */
if (CardType & CT_SD2) { /* SDv2? */
if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */
xchg_spi(0xFF);
if (rcvr_datablock(csd, 16)) { /* Read partial block */
for (n = 64 - 16; n; n--) xchg_spi(0xFF); /* Purge trailing data */
*(DWORD*)buff = 16UL << (csd[10] >> 4);
res = RES_OK;
}
}
} else { /* SDv1 or MMCv3 */
if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */
if (CardType & CT_SD1) { /* SDv1 */
*(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1);
} else { /* MMCv3 */
*(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1);
}
res = RES_OK;
}
}
break;
case MMC_GET_TYPE : /* Get card type flags (1 byte) */
*ptr = CardType;
res = RES_OK;
break;
case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */
if ((send_cmd(CMD9, 0) == 0) /* READ_CSD */
&& rcvr_datablock(buff, 16))
res = RES_OK;
break;
case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */
if ((send_cmd(CMD10, 0) == 0) /* READ_CID */
&& rcvr_datablock(buff, 16))
res = RES_OK;
break;
case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */
if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */
for (n = 0; n < 4; n++)
*((BYTE*)buff+n) = xchg_spi(0xFF);
res = RES_OK;
}
break;
case MMC_GET_SDSTAT : /* Receive SD statsu as a data block (64 bytes) */
if ((CardType & CT_SD2) && send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */
xchg_spi(0xFF);
if (rcvr_datablock(buff, 64))
res = RES_OK;
}
break;
default:
res = RES_PARERR;
}
deselect();
return res;
}
#endif
/*---------------------------------------------------------*/
/* User Provided Timer Function for FatFs module */
/*---------------------------------------------------------*/
/* This is a real time clock service to be called from */
/* FatFs module. Any valid time must be returned even if */
/* the system does not support a real time clock. */
/* This is not required in read-only configuration. */
DWORD get_fattime (void)
{
/* No RTC supprt. Return a fixed value 2010/4/26 0:00:00 */
return ((DWORD)(2013 - 1980) << 25) /* Y */
| ((DWORD)5 << 21) /* M */
| ((DWORD)10 << 16) /* D */
| ((DWORD)0 << 11) /* H */
| ((DWORD)0 << 5) /* M */
| ((DWORD)0 >> 1); /* S */
}

View File

@ -2,23 +2,38 @@
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Firmware Development Package.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -42,6 +57,9 @@
#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
#define FLASH_FCTL 0x400FD0F8 // Flash Control
#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
#define FLASH_FSIZE 0x400FDFC0 // Flash Size
#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
#define FLASH_RMCTL 0x400FE0F0 // ROM Control
#define FLASH_FMPRE 0x400FE130 // Flash Memory Protection Read
// Enable
@ -62,6 +80,14 @@
// Enable 2
#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
// Enable 3
#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
// Enable 4
#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
// Enable 5
#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
// Enable 6
#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
// Enable 7
#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
// Enable 0
#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
@ -70,13 +96,21 @@
// Enable 2
#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
// Enable 3
#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
// Enable 4
#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
// Enable 5
#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
// Enable 6
#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
// Enable 7
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMA register.
//
//*****************************************************************************
#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
#define FLASH_FMA_OFFSET_M 0x0007FFFF // Address Offset
#define FLASH_FMA_OFFSET_S 0
//*****************************************************************************
@ -103,6 +137,12 @@
// The following are defines for the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
// Status
#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
@ -111,6 +151,11 @@
// The following are defines for the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
@ -119,6 +164,16 @@
// The following are defines for the bit fields in the FLASH_FCMISC register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
// Clear
#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
@ -154,6 +209,44 @@
//*****************************************************************************
#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FSIZE register.
//
//*****************************************************************************
#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_SSIZE register.
//
//*****************************************************************************
#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
//
//*****************************************************************************
#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMCTL register.
@ -214,8 +307,8 @@
// The following are defines for the bit fields in the FLASH_USERREG0 register.
//
//*****************************************************************************
#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
#define FLASH_USERREG0_NW 0x80000000 // Not Written
#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG0_DATA_S 0
//*****************************************************************************
@ -223,8 +316,8 @@
// The following are defines for the bit fields in the FLASH_USERREG1 register.
//
//*****************************************************************************
#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
#define FLASH_USERREG1_NW 0x80000000 // Not Written
#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG1_DATA_S 0
//*****************************************************************************
@ -232,8 +325,8 @@
// The following are defines for the bit fields in the FLASH_USERREG2 register.
//
//*****************************************************************************
#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
#define FLASH_USERREG2_NW 0x80000000 // Not Written
#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG2_DATA_S 0
//*****************************************************************************
@ -241,8 +334,8 @@
// The following are defines for the bit fields in the FLASH_USERREG3 register.
//
//*****************************************************************************
#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
#define FLASH_USERREG3_NW 0x80000000 // Not Written
#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG3_DATA_S 0
//*****************************************************************************
@ -314,8 +407,8 @@
// register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY_S 16
//*****************************************************************************

View File

@ -2,23 +2,38 @@
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Firmware Development Package.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -52,6 +67,41 @@
#define GPIO_O_CR 0x00000524 // GPIO Commit
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_IM register.
//
//*****************************************************************************
#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
#define GPIO_IM_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_RIS register.
//
//*****************************************************************************
#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
#define GPIO_RIS_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_MIS register.
//
//*****************************************************************************
#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
#define GPIO_MIS_GPIO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_ICR register.
//
//*****************************************************************************
#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
#define GPIO_ICR_GPIO_S 0
//*****************************************************************************
//
@ -70,460 +120,10 @@
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port A.
// The following are defines for the bit fields in the GPIO_O_SI register.
//
//*****************************************************************************
#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
#define GPIO_PCTL_PA0_I2C1SCL 0x00000008 // I2C1SCL on PA0
#define GPIO_PCTL_PA0_U1RX 0x00000009 // U1RX on PA0
#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask
#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
#define GPIO_PCTL_PA1_I2C1SDA 0x00000080 // I2C1SDA on PA1
#define GPIO_PCTL_PA1_U1TX 0x00000090 // U1TX on PA1
#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask
#define GPIO_PCTL_PA2_SSI0CLK 0x00000100 // SSI0CLK on PA2
#define GPIO_PCTL_PA2_PWM4 0x00000400 // PWM4 on PA2
#define GPIO_PCTL_PA2_I2S0RXSD 0x00000900 // I2S0RXSD on PA2
#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask
#define GPIO_PCTL_PA3_SSI0FSS 0x00001000 // SSI0FSS on PA3
#define GPIO_PCTL_PA3_PWM5 0x00004000 // PWM5 on PA3
#define GPIO_PCTL_PA3_I2S0RXMCLK \
0x00009000 // I2S0RXMCLK on PA3
#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask
#define GPIO_PCTL_PA4_SSI0RX 0x00010000 // SSI0RX on PA4
#define GPIO_PCTL_PA4_PWM6 0x00040000 // PWM6 on PA4
#define GPIO_PCTL_PA4_CAN0RX 0x00050000 // CAN0RX on PA4
#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000 // I2S0TXSCK on PA4
#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask
#define GPIO_PCTL_PA5_SSI0TX 0x00100000 // SSI0TX on PA5
#define GPIO_PCTL_PA5_PWM7 0x00400000 // PWM7 on PA5
#define GPIO_PCTL_PA5_CAN0TX 0x00500000 // CAN0TX on PA5
#define GPIO_PCTL_PA5_I2S0TXWS 0x00900000 // I2S0TXWS on PA5
#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
#define GPIO_PCTL_PA6_I2C1SCL 0x01000000 // I2C1SCL on PA6
#define GPIO_PCTL_PA6_CCP1 0x02000000 // CCP1 on PA6
#define GPIO_PCTL_PA6_PWM0 0x04000000 // PWM0 on PA6
#define GPIO_PCTL_PA6_PWM4 0x05000000 // PWM4 on PA6
#define GPIO_PCTL_PA6_CAN0RX 0x06000000 // CAN0RX on PA6
#define GPIO_PCTL_PA6_USB0EPEN 0x08000000 // USB0EPEN on PA6
#define GPIO_PCTL_PA6_U1CTS 0x09000000 // U1CTS on PA6
#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
#define GPIO_PCTL_PA7_I2C1SDA 0x10000000 // I2C1SDA on PA7
#define GPIO_PCTL_PA7_CCP4 0x20000000 // CCP4 on PA7
#define GPIO_PCTL_PA7_PWM1 0x40000000 // PWM1 on PA7
#define GPIO_PCTL_PA7_PWM5 0x50000000 // PWM5 on PA7
#define GPIO_PCTL_PA7_CAN0TX 0x60000000 // CAN0TX on PA7
#define GPIO_PCTL_PA7_CCP3 0x70000000 // CCP3 on PA7
#define GPIO_PCTL_PA7_USB0PFLT 0x80000000 // USB0PFLT on PA7
#define GPIO_PCTL_PA7_U1DCD 0x90000000 // U1DCD on PA7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port B.
//
//*****************************************************************************
#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
#define GPIO_PCTL_PB0_CCP0 0x00000001 // CCP0 on PB0
#define GPIO_PCTL_PB0_PWM2 0x00000002 // PWM2 on PB0
#define GPIO_PCTL_PB0_U1RX 0x00000005 // U1RX on PB0
#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask
#define GPIO_PCTL_PB1_CCP2 0x00000010 // CCP2 on PB1
#define GPIO_PCTL_PB1_PWM3 0x00000020 // PWM3 on PB1
#define GPIO_PCTL_PB1_CCP1 0x00000040 // CCP1 on PB1
#define GPIO_PCTL_PB1_U1TX 0x00000050 // U1TX on PB1
#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask
#define GPIO_PCTL_PB2_I2C0SCL 0x00000100 // I2C0SCL on PB2
#define GPIO_PCTL_PB2_IDX0 0x00000200 // IDX0 on PB2
#define GPIO_PCTL_PB2_CCP3 0x00000400 // CCP3 on PB2
#define GPIO_PCTL_PB2_CCP0 0x00000500 // CCP0 on PB2
#define GPIO_PCTL_PB2_USB0EPEN 0x00000800 // USB0EPEN on PB2
#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask
#define GPIO_PCTL_PB3_I2C0SDA 0x00001000 // I2C0SDA on PB3
#define GPIO_PCTL_PB3_FAULT0 0x00002000 // FAULT0 on PB3
#define GPIO_PCTL_PB3_FAULT3 0x00004000 // FAULT3 on PB3
#define GPIO_PCTL_PB3_USB0PFLT 0x00008000 // USB0PFLT on PB3
#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask
#define GPIO_PCTL_PB4_U2RX 0x00040000 // U2RX on PB4
#define GPIO_PCTL_PB4_CAN0RX 0x00050000 // CAN0RX on PB4
#define GPIO_PCTL_PB4_IDX0 0x00060000 // IDX0 on PB4
#define GPIO_PCTL_PB4_U1RX 0x00070000 // U1RX on PB4
#define GPIO_PCTL_PB4_EPI0S23 0x00080000 // EPI0S23 on PB4
#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask
#define GPIO_PCTL_PB5_C0O 0x00100000 // C0O on PB5
#define GPIO_PCTL_PB5_CCP5 0x00200000 // CCP5 on PB5
#define GPIO_PCTL_PB5_CCP6 0x00300000 // CCP6 on PB5
#define GPIO_PCTL_PB5_CCP0 0x00400000 // CCP0 on PB5
#define GPIO_PCTL_PB5_CAN0TX 0x00500000 // CAN0TX on PB5
#define GPIO_PCTL_PB5_CCP2 0x00600000 // CCP2 on PB5
#define GPIO_PCTL_PB5_U1TX 0x00700000 // U1TX on PB5
#define GPIO_PCTL_PB5_EPI0S22 0x00800000 // EPI0S22 on PB5
#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask
#define GPIO_PCTL_PB6_CCP1 0x01000000 // CCP1 on PB6
#define GPIO_PCTL_PB6_CCP7 0x02000000 // CCP7 on PB6
#define GPIO_PCTL_PB6_C0O 0x03000000 // C0O on PB6
#define GPIO_PCTL_PB6_FAULT1 0x04000000 // FAULT1 on PB6
#define GPIO_PCTL_PB6_IDX0 0x05000000 // IDX0 on PB6
#define GPIO_PCTL_PB6_CCP5 0x06000000 // CCP5 on PB6
#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000 // I2S0TXSCK on PB6
#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask
#define GPIO_PCTL_PB7_NMI 0x40000000 // NMI on PB7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port C.
//
//*****************************************************************************
#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
#define GPIO_PCTL_PC0_TCK 0x00000003 // TCK on PC0
#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask
#define GPIO_PCTL_PC1_TMS 0x00000030 // TMS on PC1
#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask
#define GPIO_PCTL_PC2_TDI 0x00000300 // TDI on PC2
#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask
#define GPIO_PCTL_PC3_TDO 0x00003000 // TDO on PC3
#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask
#define GPIO_PCTL_PC4_CCP5 0x00010000 // CCP5 on PC4
#define GPIO_PCTL_PC4_PHA0 0x00020000 // PHA0 on PC4
#define GPIO_PCTL_PC4_PWM6 0x00040000 // PWM6 on PC4
#define GPIO_PCTL_PC4_CCP2 0x00050000 // CCP2 on PC4
#define GPIO_PCTL_PC4_CCP4 0x00060000 // CCP4 on PC4
#define GPIO_PCTL_PC4_EPI0S2 0x00080000 // EPI0S2 on PC4
#define GPIO_PCTL_PC4_CCP1 0x00090000 // CCP1 on PC4
#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask
#define GPIO_PCTL_PC5_CCP1 0x00100000 // CCP1 on PC5
#define GPIO_PCTL_PC5_C1O 0x00200000 // C1O on PC5
#define GPIO_PCTL_PC5_C0O 0x00300000 // C0O on PC5
#define GPIO_PCTL_PC5_FAULT2 0x00400000 // FAULT2 on PC5
#define GPIO_PCTL_PC5_CCP3 0x00500000 // CCP3 on PC5
#define GPIO_PCTL_PC5_USB0EPEN 0x00600000 // USB0EPEN on PC5
#define GPIO_PCTL_PC5_EPI0S3 0x00800000 // EPI0S3 on PC5
#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
#define GPIO_PCTL_PC6_CCP3 0x01000000 // CCP3 on PC6
#define GPIO_PCTL_PC6_PHB0 0x02000000 // PHB0 on PC6
#define GPIO_PCTL_PC6_C2O 0x03000000 // C2O on PC6
#define GPIO_PCTL_PC6_PWM7 0x04000000 // PWM7 on PC6
#define GPIO_PCTL_PC6_U1RX 0x05000000 // U1RX on PC6
#define GPIO_PCTL_PC6_CCP0 0x06000000 // CCP0 on PC6
#define GPIO_PCTL_PC6_USB0PFLT 0x07000000 // USB0PFLT on PC6
#define GPIO_PCTL_PC6_EPI0S4 0x08000000 // EPI0S4 on PC6
#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
#define GPIO_PCTL_PC7_CCP4 0x10000000 // CCP4 on PC7
#define GPIO_PCTL_PC7_PHB0 0x20000000 // PHB0 on PC7
#define GPIO_PCTL_PC7_CCP0 0x40000000 // CCP0 on PC7
#define GPIO_PCTL_PC7_U1TX 0x50000000 // U1TX on PC7
#define GPIO_PCTL_PC7_USB0PFLT 0x60000000 // USB0PFLT on PC7
#define GPIO_PCTL_PC7_C1O 0x70000000 // C1O on PC7
#define GPIO_PCTL_PC7_EPI0S5 0x80000000 // EPI0S5 on PC7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port D.
//
//*****************************************************************************
#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
#define GPIO_PCTL_PD0_PWM0 0x00000001 // PWM0 on PD0
#define GPIO_PCTL_PD0_CAN0RX 0x00000002 // CAN0RX on PD0
#define GPIO_PCTL_PD0_IDX0 0x00000003 // IDX0 on PD0
#define GPIO_PCTL_PD0_U2RX 0x00000004 // U2RX on PD0
#define GPIO_PCTL_PD0_U1RX 0x00000005 // U1RX on PD0
#define GPIO_PCTL_PD0_CCP6 0x00000006 // CCP6 on PD0
#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008 // I2S0RXSCK on PD0
#define GPIO_PCTL_PD0_U1CTS 0x00000009 // U1CTS on PD0
#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask
#define GPIO_PCTL_PD1_PWM1 0x00000010 // PWM1 on PD1
#define GPIO_PCTL_PD1_CAN0TX 0x00000020 // CAN0TX on PD1
#define GPIO_PCTL_PD1_PHA0 0x00000030 // PHA0 on PD1
#define GPIO_PCTL_PD1_U2TX 0x00000040 // U2TX on PD1
#define GPIO_PCTL_PD1_U1TX 0x00000050 // U1TX on PD1
#define GPIO_PCTL_PD1_CCP7 0x00000060 // CCP7 on PD1
#define GPIO_PCTL_PD1_I2S0RXWS 0x00000080 // I2S0RXWS on PD1
#define GPIO_PCTL_PD1_U1DCD 0x00000090 // U1DCD on PD1
#define GPIO_PCTL_PD1_CCP2 0x000000A0 // CCP2 on PD1
#define GPIO_PCTL_PD1_PHB1 0x000000B0 // PHB1 on PD1
#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask
#define GPIO_PCTL_PD2_U1RX 0x00000100 // U1RX on PD2
#define GPIO_PCTL_PD2_CCP6 0x00000200 // CCP6 on PD2
#define GPIO_PCTL_PD2_PWM2 0x00000300 // PWM2 on PD2
#define GPIO_PCTL_PD2_CCP5 0x00000400 // CCP5 on PD2
#define GPIO_PCTL_PD2_EPI0S20 0x00000800 // EPI0S20 on PD2
#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask
#define GPIO_PCTL_PD3_U1TX 0x00001000 // U1TX on PD3
#define GPIO_PCTL_PD3_CCP7 0x00002000 // CCP7 on PD3
#define GPIO_PCTL_PD3_PWM3 0x00003000 // PWM3 on PD3
#define GPIO_PCTL_PD3_CCP0 0x00004000 // CCP0 on PD3
#define GPIO_PCTL_PD3_EPI0S21 0x00008000 // EPI0S21 on PD3
#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask
#define GPIO_PCTL_PD4_CCP0 0x00010000 // CCP0 on PD4
#define GPIO_PCTL_PD4_CCP3 0x00020000 // CCP3 on PD4
#define GPIO_PCTL_PD4_I2S0RXSD 0x00080000 // I2S0RXSD on PD4
#define GPIO_PCTL_PD4_U1RI 0x00090000 // U1RI on PD4
#define GPIO_PCTL_PD4_EPI0S19 0x000A0000 // EPI0S19 on PD4
#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask
#define GPIO_PCTL_PD5_CCP2 0x00100000 // CCP2 on PD5
#define GPIO_PCTL_PD5_CCP4 0x00200000 // CCP4 on PD5
#define GPIO_PCTL_PD5_I2S0RXMCLK \
0x00800000 // I2S0RXMCLK on PD5
#define GPIO_PCTL_PD5_U2RX 0x00900000 // U2RX on PD5
#define GPIO_PCTL_PD5_EPI0S28 0x00A00000 // EPI0S28 on PD5
#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
#define GPIO_PCTL_PD6_FAULT0 0x01000000 // FAULT0 on PD6
#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000 // I2S0TXSCK on PD6
#define GPIO_PCTL_PD6_U2TX 0x09000000 // U2TX on PD6
#define GPIO_PCTL_PD6_EPI0S29 0x0A000000 // EPI0S29 on PD6
#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
#define GPIO_PCTL_PD7_IDX0 0x10000000 // IDX0 on PD7
#define GPIO_PCTL_PD7_C0O 0x20000000 // C0O on PD7
#define GPIO_PCTL_PD7_CCP1 0x30000000 // CCP1 on PD7
#define GPIO_PCTL_PD7_I2S0TXWS 0x80000000 // I2S0TXWS on PD7
#define GPIO_PCTL_PD7_U1DTR 0x90000000 // U1DTR on PD7
#define GPIO_PCTL_PD7_EPI0S30 0xA0000000 // EPI0S30 on PD7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port E.
//
//*****************************************************************************
#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
#define GPIO_PCTL_PE0_PWM4 0x00000001 // PWM4 on PE0
#define GPIO_PCTL_PE0_SSI1CLK 0x00000002 // SSI1CLK on PE0
#define GPIO_PCTL_PE0_CCP3 0x00000003 // CCP3 on PE0
#define GPIO_PCTL_PE0_EPI0S8 0x00000008 // EPI0S8 on PE0
#define GPIO_PCTL_PE0_USB0PFLT 0x00000009 // USB0PFLT on PE0
#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask
#define GPIO_PCTL_PE1_PWM5 0x00000010 // PWM5 on PE1
#define GPIO_PCTL_PE1_SSI1FSS 0x00000020 // SSI1FSS on PE1
#define GPIO_PCTL_PE1_FAULT0 0x00000030 // FAULT0 on PE1
#define GPIO_PCTL_PE1_CCP2 0x00000040 // CCP2 on PE1
#define GPIO_PCTL_PE1_CCP6 0x00000050 // CCP6 on PE1
#define GPIO_PCTL_PE1_EPI0S9 0x00000080 // EPI0S9 on PE1
#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask
#define GPIO_PCTL_PE2_CCP4 0x00000100 // CCP4 on PE2
#define GPIO_PCTL_PE2_SSI1RX 0x00000200 // SSI1RX on PE2
#define GPIO_PCTL_PE2_PHB1 0x00000300 // PHB1 on PE2
#define GPIO_PCTL_PE2_PHA0 0x00000400 // PHA0 on PE2
#define GPIO_PCTL_PE2_CCP2 0x00000500 // CCP2 on PE2
#define GPIO_PCTL_PE2_EPI0S24 0x00000800 // EPI0S24 on PE2
#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask
#define GPIO_PCTL_PE3_CCP1 0x00001000 // CCP1 on PE3
#define GPIO_PCTL_PE3_SSI1TX 0x00002000 // SSI1TX on PE3
#define GPIO_PCTL_PE3_PHA1 0x00003000 // PHA1 on PE3
#define GPIO_PCTL_PE3_PHB0 0x00004000 // PHB0 on PE3
#define GPIO_PCTL_PE3_CCP7 0x00005000 // CCP7 on PE3
#define GPIO_PCTL_PE3_EPI0S25 0x00008000 // EPI0S25 on PE3
#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask
#define GPIO_PCTL_PE4_CCP3 0x00010000 // CCP3 on PE4
#define GPIO_PCTL_PE4_FAULT0 0x00040000 // FAULT0 on PE4
#define GPIO_PCTL_PE4_U2TX 0x00050000 // U2TX on PE4
#define GPIO_PCTL_PE4_CCP2 0x00060000 // CCP2 on PE4
#define GPIO_PCTL_PE4_I2S0TXWS 0x00090000 // I2S0TXWS on PE4
#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask
#define GPIO_PCTL_PE5_CCP5 0x00100000 // CCP5 on PE5
#define GPIO_PCTL_PE5_I2S0TXSD 0x00900000 // I2S0TXSD on PE5
#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask
#define GPIO_PCTL_PE6_PWM4 0x01000000 // PWM4 on PE6
#define GPIO_PCTL_PE6_C1O 0x02000000 // C1O on PE6
#define GPIO_PCTL_PE6_U1CTS 0x09000000 // U1CTS on PE6
#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask
#define GPIO_PCTL_PE7_PWM5 0x10000000 // PWM5 on PE7
#define GPIO_PCTL_PE7_C2O 0x20000000 // C2O on PE7
#define GPIO_PCTL_PE7_U1DCD 0x90000000 // U1DCD on PE7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port F.
//
//*****************************************************************************
#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
#define GPIO_PCTL_PF0_CAN1RX 0x00000001 // CAN1RX on PF0
#define GPIO_PCTL_PF0_PHB0 0x00000002 // PHB0 on PF0
#define GPIO_PCTL_PF0_PWM0 0x00000003 // PWM0 on PF0
#define GPIO_PCTL_PF0_I2S0TXSD 0x00000008 // I2S0TXSD on PF0
#define GPIO_PCTL_PF0_U1DSR 0x00000009 // U1DSR on PF0
#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask
#define GPIO_PCTL_PF1_CAN1TX 0x00000010 // CAN1TX on PF1
#define GPIO_PCTL_PF1_IDX1 0x00000020 // IDX1 on PF1
#define GPIO_PCTL_PF1_PWM1 0x00000030 // PWM1 on PF1
#define GPIO_PCTL_PF1_I2S0TXMCLK \
0x00000080 // I2S0TXMCLK on PF1
#define GPIO_PCTL_PF1_U1RTS 0x00000090 // U1RTS on PF1
#define GPIO_PCTL_PF1_CCP3 0x000000A0 // CCP3 on PF1
#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask
#define GPIO_PCTL_PF2_LED1 0x00000100 // LED1 on PF2
#define GPIO_PCTL_PF2_PWM4 0x00000200 // PWM4 on PF2
#define GPIO_PCTL_PF2_PWM2 0x00000400 // PWM2 on PF2
#define GPIO_PCTL_PF2_SSI1CLK 0x00000900 // SSI1CLK on PF2
#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask
#define GPIO_PCTL_PF3_LED0 0x00001000 // LED0 on PF3
#define GPIO_PCTL_PF3_PWM5 0x00002000 // PWM5 on PF3
#define GPIO_PCTL_PF3_PWM3 0x00004000 // PWM3 on PF3
#define GPIO_PCTL_PF3_SSI1FSS 0x00009000 // SSI1FSS on PF3
#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask
#define GPIO_PCTL_PF4_CCP0 0x00010000 // CCP0 on PF4
#define GPIO_PCTL_PF4_C0O 0x00020000 // C0O on PF4
#define GPIO_PCTL_PF4_FAULT0 0x00040000 // FAULT0 on PF4
#define GPIO_PCTL_PF4_EPI0S12 0x00080000 // EPI0S12 on PF4
#define GPIO_PCTL_PF4_SSI1RX 0x00090000 // SSI1RX on PF4
#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask
#define GPIO_PCTL_PF5_CCP2 0x00100000 // CCP2 on PF5
#define GPIO_PCTL_PF5_C1O 0x00200000 // C1O on PF5
#define GPIO_PCTL_PF5_EPI0S15 0x00800000 // EPI0S15 on PF5
#define GPIO_PCTL_PF5_SSI1TX 0x00900000 // SSI1TX on PF5
#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask
#define GPIO_PCTL_PF6_CCP1 0x01000000 // CCP1 on PF6
#define GPIO_PCTL_PF6_C2O 0x02000000 // C2O on PF6
#define GPIO_PCTL_PF6_PHA0 0x04000000 // PHA0 on PF6
#define GPIO_PCTL_PF6_I2S0TXMCLK \
0x09000000 // I2S0TXMCLK on PF6
#define GPIO_PCTL_PF6_U1RTS 0x0A000000 // U1RTS on PF6
#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask
#define GPIO_PCTL_PF7_CCP4 0x10000000 // CCP4 on PF7
#define GPIO_PCTL_PF7_PHB0 0x40000000 // PHB0 on PF7
#define GPIO_PCTL_PF7_EPI0S12 0x80000000 // EPI0S12 on PF7
#define GPIO_PCTL_PF7_FAULT1 0x90000000 // FAULT1 on PF7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port G.
//
//*****************************************************************************
#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask
#define GPIO_PCTL_PG0_U2RX 0x00000001 // U2RX on PG0
#define GPIO_PCTL_PG0_PWM0 0x00000002 // PWM0 on PG0
#define GPIO_PCTL_PG0_I2C1SCL 0x00000003 // I2C1SCL on PG0
#define GPIO_PCTL_PG0_PWM4 0x00000004 // PWM4 on PG0
#define GPIO_PCTL_PG0_USB0EPEN 0x00000007 // USB0EPEN on PG0
#define GPIO_PCTL_PG0_EPI0S13 0x00000008 // EPI0S13 on PG0
#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask
#define GPIO_PCTL_PG1_U2TX 0x00000010 // U2TX on PG1
#define GPIO_PCTL_PG1_PWM1 0x00000020 // PWM1 on PG1
#define GPIO_PCTL_PG1_I2C1SDA 0x00000030 // I2C1SDA on PG1
#define GPIO_PCTL_PG1_PWM5 0x00000040 // PWM5 on PG1
#define GPIO_PCTL_PG1_EPI0S14 0x00000080 // EPI0S14 on PG1
#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask
#define GPIO_PCTL_PG2_PWM0 0x00000100 // PWM0 on PG2
#define GPIO_PCTL_PG2_FAULT0 0x00000400 // FAULT0 on PG2
#define GPIO_PCTL_PG2_IDX1 0x00000800 // IDX1 on PG2
#define GPIO_PCTL_PG2_I2S0RXSD 0x00000900 // I2S0RXSD on PG2
#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask
#define GPIO_PCTL_PG3_PWM1 0x00001000 // PWM1 on PG3
#define GPIO_PCTL_PG3_FAULT2 0x00004000 // FAULT2 on PG3
#define GPIO_PCTL_PG3_FAULT0 0x00008000 // FAULT0 on PG3
#define GPIO_PCTL_PG3_I2S0RXMCLK \
0x00009000 // I2S0RXMCLK on PG3
#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask
#define GPIO_PCTL_PG4_CCP3 0x00010000 // CCP3 on PG4
#define GPIO_PCTL_PG4_FAULT1 0x00040000 // FAULT1 on PG4
#define GPIO_PCTL_PG4_EPI0S15 0x00080000 // EPI0S15 on PG4
#define GPIO_PCTL_PG4_PWM6 0x00090000 // PWM6 on PG4
#define GPIO_PCTL_PG4_U1RI 0x000A0000 // U1RI on PG4
#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask
#define GPIO_PCTL_PG5_CCP5 0x00100000 // CCP5 on PG5
#define GPIO_PCTL_PG5_IDX0 0x00400000 // IDX0 on PG5
#define GPIO_PCTL_PG5_FAULT1 0x00500000 // FAULT1 on PG5
#define GPIO_PCTL_PG5_PWM7 0x00800000 // PWM7 on PG5
#define GPIO_PCTL_PG5_I2S0RXSCK 0x00900000 // I2S0RXSCK on PG5
#define GPIO_PCTL_PG5_U1DTR 0x00A00000 // U1DTR on PG5
#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask
#define GPIO_PCTL_PG6_PHA1 0x01000000 // PHA1 on PG6
#define GPIO_PCTL_PG6_PWM6 0x04000000 // PWM6 on PG6
#define GPIO_PCTL_PG6_FAULT1 0x08000000 // FAULT1 on PG6
#define GPIO_PCTL_PG6_I2S0RXWS 0x09000000 // I2S0RXWS on PG6
#define GPIO_PCTL_PG6_U1RI 0x0A000000 // U1RI on PG6
#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask
#define GPIO_PCTL_PG7_PHB1 0x10000000 // PHB1 on PG7
#define GPIO_PCTL_PG7_PWM7 0x40000000 // PWM7 on PG7
#define GPIO_PCTL_PG7_CCP5 0x80000000 // CCP5 on PG7
#define GPIO_PCTL_PG7_EPI0S31 0x90000000 // EPI0S31 on PG7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port H.
//
//*****************************************************************************
#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask
#define GPIO_PCTL_PH0_CCP6 0x00000001 // CCP6 on PH0
#define GPIO_PCTL_PH0_PWM2 0x00000002 // PWM2 on PH0
#define GPIO_PCTL_PH0_EPI0S6 0x00000008 // EPI0S6 on PH0
#define GPIO_PCTL_PH0_PWM4 0x00000009 // PWM4 on PH0
#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask
#define GPIO_PCTL_PH1_CCP7 0x00000010 // CCP7 on PH1
#define GPIO_PCTL_PH1_PWM3 0x00000020 // PWM3 on PH1
#define GPIO_PCTL_PH1_EPI0S7 0x00000080 // EPI0S7 on PH1
#define GPIO_PCTL_PH1_PWM5 0x00000090 // PWM5 on PH1
#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask
#define GPIO_PCTL_PH2_IDX1 0x00000100 // IDX1 on PH2
#define GPIO_PCTL_PH2_C1O 0x00000200 // C1O on PH2
#define GPIO_PCTL_PH2_FAULT3 0x00000400 // FAULT3 on PH2
#define GPIO_PCTL_PH2_EPI0S1 0x00000800 // EPI0S1 on PH2
#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask
#define GPIO_PCTL_PH3_PHB0 0x00001000 // PHB0 on PH3
#define GPIO_PCTL_PH3_FAULT0 0x00002000 // FAULT0 on PH3
#define GPIO_PCTL_PH3_USB0EPEN 0x00004000 // USB0EPEN on PH3
#define GPIO_PCTL_PH3_EPI0S0 0x00008000 // EPI0S0 on PH3
#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask
#define GPIO_PCTL_PH4_USB0PFLT 0x00040000 // USB0PFLT on PH4
#define GPIO_PCTL_PH4_EPI0S10 0x00080000 // EPI0S10 on PH4
#define GPIO_PCTL_PH4_SSI1CLK 0x000B0000 // SSI1CLK on PH4
#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask
#define GPIO_PCTL_PH5_EPI0S11 0x00800000 // EPI0S11 on PH5
#define GPIO_PCTL_PH5_FAULT2 0x00A00000 // FAULT2 on PH5
#define GPIO_PCTL_PH5_SSI1FSS 0x00B00000 // SSI1FSS on PH5
#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask
#define GPIO_PCTL_PH6_EPI0S26 0x08000000 // EPI0S26 on PH6
#define GPIO_PCTL_PH6_PWM4 0x0A000000 // PWM4 on PH6
#define GPIO_PCTL_PH6_SSI1RX 0x0B000000 // SSI1RX on PH6
#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask
#define GPIO_PCTL_PH7_EPI0S27 0x80000000 // EPI0S27 on PH7
#define GPIO_PCTL_PH7_PWM5 0xA0000000 // PWM5 on PH7
#define GPIO_PCTL_PH7_SSI1TX 0xB0000000 // SSI1TX on PH7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port J.
//
//*****************************************************************************
#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask
#define GPIO_PCTL_PJ0_EPI0S16 0x00000008 // EPI0S16 on PJ0
#define GPIO_PCTL_PJ0_PWM0 0x0000000A // PWM0 on PJ0
#define GPIO_PCTL_PJ0_I2C1SCL 0x0000000B // I2C1SCL on PJ0
#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask
#define GPIO_PCTL_PJ1_EPI0S17 0x00000080 // EPI0S17 on PJ1
#define GPIO_PCTL_PJ1_USB0PFLT 0x00000090 // USB0PFLT on PJ1
#define GPIO_PCTL_PJ1_PWM1 0x000000A0 // PWM1 on PJ1
#define GPIO_PCTL_PJ1_I2C1SDA 0x000000B0 // I2C1SDA on PJ1
#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask
#define GPIO_PCTL_PJ2_EPI0S18 0x00000800 // EPI0S18 on PJ2
#define GPIO_PCTL_PJ2_CCP0 0x00000900 // CCP0 on PJ2
#define GPIO_PCTL_PJ2_FAULT0 0x00000A00 // FAULT0 on PJ2
#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask
#define GPIO_PCTL_PJ3_EPI0S19 0x00008000 // EPI0S19 on PJ3
#define GPIO_PCTL_PJ3_U1CTS 0x00009000 // U1CTS on PJ3
#define GPIO_PCTL_PJ3_CCP6 0x0000A000 // CCP6 on PJ3
#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask
#define GPIO_PCTL_PJ4_EPI0S28 0x00080000 // EPI0S28 on PJ4
#define GPIO_PCTL_PJ4_U1DCD 0x00090000 // U1DCD on PJ4
#define GPIO_PCTL_PJ4_CCP4 0x000A0000 // CCP4 on PJ4
#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask
#define GPIO_PCTL_PJ5_EPI0S29 0x00800000 // EPI0S29 on PJ5
#define GPIO_PCTL_PJ5_U1DSR 0x00900000 // U1DSR on PJ5
#define GPIO_PCTL_PJ5_CCP2 0x00A00000 // CCP2 on PJ5
#define GPIO_PCTL_PJ6_M 0x0F000000 // PJ6 mask
#define GPIO_PCTL_PJ6_EPI0S30 0x08000000 // EPI0S30 on PJ6
#define GPIO_PCTL_PJ6_U1RTS 0x09000000 // U1RTS on PJ6
#define GPIO_PCTL_PJ6_CCP1 0x0A000000 // CCP1 on PJ6
#define GPIO_PCTL_PJ7_M 0xF0000000 // PJ7 mask
#define GPIO_PCTL_PJ7_U1DTR 0x90000000 // U1DTR on PJ7
#define GPIO_PCTL_PJ7_CCP0 0xA0000000 // CCP0 on PJ7
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
//*****************************************************************************
//

View File

@ -2,23 +2,38 @@
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Firmware Development Package.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -54,10 +69,10 @@
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI0 23 // SSI0 Rx and Tx
#define INT_I2C0 24 // I2C0 Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_PWM0_FAULT 25 // PWM0 Fault
#define INT_PWM0_0 26 // PWM0 Generator 0
#define INT_PWM0_1 27 // PWM0 Generator 1
#define INT_PWM0_2 28 // PWM0 Generator 2
#define INT_QEI0 29 // Quadrature Encoder 0
#define INT_ADC0SS0 30 // ADC0 Sequence 0
#define INT_ADC0SS1 31 // ADC0 Sequence 1
@ -90,7 +105,7 @@
#define INT_ETH 58 // Ethernet
#define INT_HIBERNATE 59 // Hibernation module
#define INT_USB0 60 // USB 0 Controller
#define INT_PWM3 61 // PWM Generator 3
#define INT_PWM0_3 61 // PWM0 Generator 3
#define INT_UDMA 62 // uDMA controller
#define INT_UDMAERR 63 // uDMA Error
#define INT_ADC1SS0 64 // ADC1 Sequence 0
@ -100,13 +115,69 @@
#define INT_I2S0 68 // I2S0
#define INT_EPI0 69 // EPI0
#define INT_GPIOJ 70 // GPIO Port J
#define INT_GPIOK 71 // GPIO Port K
#define INT_GPIOL 72 // GPIO Port L
#define INT_SSI2 73 // SSI2
#define INT_SSI3 74 // SSI3
#define INT_UART3 75 // UART3
#define INT_UART4 76 // UART4
#define INT_UART5 77 // UART5
#define INT_UART6 78 // UART6
#define INT_UART7 79 // UART7
#define INT_I2C2 84 // I2C2
#define INT_I2C3 85 // I2C3
#define INT_TIMER4A 86 // Timer 4A
#define INT_TIMER4B 87 // Timer 4B
#define INT_TIMER5A 108 // Timer 5A
#define INT_TIMER5B 109 // Timer 5B
#define INT_WTIMER0A 110 // Wide Timer 0A
#define INT_WTIMER0B 111 // Wide Timer 0B
#define INT_WTIMER1A 112 // Wide Timer 1A
#define INT_WTIMER1B 113 // Wide Timer 1B
#define INT_WTIMER2A 114 // Wide Timer 2A
#define INT_WTIMER2B 115 // Wide Timer 2B
#define INT_WTIMER3A 116 // Wide Timer 3A
#define INT_WTIMER3B 117 // Wide Timer 3B
#define INT_WTIMER4A 118 // Wide Timer 4A
#define INT_WTIMER4B 119 // Wide Timer 4B
#define INT_WTIMER5A 120 // Wide Timer 5A
#define INT_WTIMER5B 121 // Wide Timer 5B
#define INT_SYSEXC 122 // System Exception (imprecise)
#define INT_PECI0 123 // PECI 0
#define INT_LPC0 124 // LPC 0
#define INT_I2C4 125 // I2C4
#define INT_I2C5 126 // I2C5
#define INT_GPIOM 127 // GPIO Port M
#define INT_GPION 128 // GPIO Port N
#define INT_FAN0 130 // FAN 0
#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
#define INT_GPIOP1 133 // GPIO Port P1
#define INT_GPIOP2 134 // GPIO Port P2
#define INT_GPIOP3 135 // GPIO Port P3
#define INT_GPIOP4 136 // GPIO Port P4
#define INT_GPIOP5 137 // GPIO Port P5
#define INT_GPIOP6 138 // GPIO Port P6
#define INT_GPIOP7 139 // GPIO Port P7
#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
#define INT_GPIOQ1 141 // GPIO Port Q1
#define INT_GPIOQ2 142 // GPIO Port Q2
#define INT_GPIOQ3 143 // GPIO Port Q3
#define INT_GPIOQ4 144 // GPIO Port Q4
#define INT_GPIOQ5 145 // GPIO Port Q5
#define INT_GPIOQ6 146 // GPIO Port Q6
#define INT_GPIOQ7 147 // GPIO Port Q7
#define INT_PWM1_0 150 // PWM1 Generator 0
#define INT_PWM1_1 151 // PWM1 Generator 1
#define INT_PWM1_2 152 // PWM1 Generator 2
#define INT_PWM1_3 153 // PWM1 Generator 3
#define INT_PWM1_FAULT 154 // PWM1 Fault
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 71
#define NUM_INTERRUPTS 155
//*****************************************************************************
//
@ -130,11 +201,16 @@
//*****************************************************************************
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI 29 // Quadrature Encoder
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_PWM3 61 // PWM Generator 3
#endif

View File

@ -2,23 +2,38 @@
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Firmware Development Package.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -41,24 +56,40 @@
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI0_BASE 0x40008000 // SSI0
#define SSI1_BASE 0x40009000 // SSI1
#define SSI2_BASE 0x4000A000 // SSI2
#define SSI3_BASE 0x4000B000 // SSI3
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define UART2_BASE 0x4000E000 // UART2
#define UART3_BASE 0x4000F000 // UART3
#define UART4_BASE 0x40010000 // UART4
#define UART5_BASE 0x40011000 // UART5
#define UART6_BASE 0x40012000 // UART6
#define UART7_BASE 0x40013000 // UART7
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master
#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave
#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master
#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
#define PWM_BASE 0x40028000 // PWM
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
#define QEI0_BASE 0x4002C000 // QEI0
#define QEI1_BASE 0x4002D000 // QEI1
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define TIMER3_BASE 0x40033000 // Timer3
#define TIMER4_BASE 0x40034000 // Timer4
#define TIMER5_BASE 0x40035000 // Timer5
#define WTIMER0_BASE 0x40036000 // Wide Timer0
#define WTIMER1_BASE 0x40037000 // Wide Timer1
#define ADC0_BASE 0x40038000 // ADC0
#define ADC1_BASE 0x40039000 // ADC1
#define COMP_BASE 0x4003C000 // Analog comparators
@ -68,6 +99,10 @@
#define CAN2_BASE 0x40042000 // CAN2
#define ETH_BASE 0x40048000 // Ethernet
#define MAC_BASE 0x40048000 // Ethernet
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
#define USB0_BASE 0x40050000 // USB 0 Controller
#define I2S0_BASE 0x40054000 // I2S0
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
@ -79,7 +114,23 @@
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC)
#define FAN0_BASE 0x40084000 // Fan Control (FAN)
#define EEPROM_BASE 0x400AF000 // EEPROM memory
#define PECI0_BASE 0x400B0000 // Platform Environment Control
// Interface (PECI)
#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master
#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave
#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master
#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave
#define EPI0_BASE 0x400D0000 // EPI0
#define SYSEXC_BASE 0x400F9000 // System Exception Module
#define HIB_BASE 0x400FC000 // Hibernation Module
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
@ -107,6 +158,7 @@
#define SSI_BASE 0x40008000 // SSI
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define PWM_BASE 0x40028000 // PWM
#define QEI_BASE 0x4002C000 // QEI
#define ADC_BASE 0x40038000 // ADC

View File

@ -2,23 +2,38 @@
//
// hw_nvic.h - Macros used when accessing the NVIC hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Firmware Development Package.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -39,14 +54,29 @@
#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg
#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable
#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable
#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable
#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable
#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable
#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable
#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable
#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable
#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable
#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending
#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending
#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending
#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending
#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending
#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending
#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending
#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending
#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending
#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending
#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit
#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit
#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit
#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit
#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit
#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority
#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority
#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority
@ -60,7 +90,28 @@
#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority
#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority
#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority
#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority
#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority
#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority
#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority
#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority
#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority
#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority
#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority
#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority
#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority
#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority
#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority
#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority
#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority
#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority
#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority
#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority
#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority
#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority
#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority
#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority
#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority
#define NVIC_PRI34 0xE000E488 // Interrupt 136-138 Priority
#define NVIC_CPUID 0xE000ED00 // CPU ID Base
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset
@ -77,6 +128,7 @@
#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address
#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address
#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control
#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type
#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control
#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number
@ -96,6 +148,10 @@
#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt
#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control
#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address
#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status
// Control
//*****************************************************************************
//
@ -110,6 +166,9 @@
// The following are defines for the bit fields in the NVIC_ACTLR register.
//
//*****************************************************************************
#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating
// Point
#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL
#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
@ -196,7 +255,7 @@
// The following are defines for the bit fields in the NVIC_EN1 register.
//
//*****************************************************************************
#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable
#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable
#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
@ -221,6 +280,27 @@
#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_EN2 register.
//
//*****************************************************************************
#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_EN3 register.
//
//*****************************************************************************
#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_EN4 register.
//
//*****************************************************************************
#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DIS0 register.
@ -265,7 +345,7 @@
// The following are defines for the bit fields in the NVIC_DIS1 register.
//
//*****************************************************************************
#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable
#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable
#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
@ -291,6 +371,27 @@
#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DIS2 register.
//
//*****************************************************************************
#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DIS3 register.
//
//*****************************************************************************
#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_DIS4 register.
//
//*****************************************************************************
#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PEND0 register.
@ -335,7 +436,7 @@
// The following are defines for the bit fields in the NVIC_PEND1 register.
//
//*****************************************************************************
#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending
#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending
#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
@ -361,6 +462,27 @@
#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PEND2 register.
//
//*****************************************************************************
#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PEND3 register.
//
//*****************************************************************************
#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PEND4 register.
//
//*****************************************************************************
#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_UNPEND0 register.
@ -405,7 +527,7 @@
// The following are defines for the bit fields in the NVIC_UNPEND1 register.
//
//*****************************************************************************
#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending
#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending
#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
@ -431,6 +553,27 @@
#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_UNPEND2 register.
//
//*****************************************************************************
#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_UNPEND3 register.
//
//*****************************************************************************
#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_UNPEND4 register.
//
//*****************************************************************************
#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
@ -475,7 +618,7 @@
// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
//
//*****************************************************************************
#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active
#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active
#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
@ -501,6 +644,27 @@
#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
//
//*****************************************************************************
#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
//
//*****************************************************************************
#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
//
//*****************************************************************************
#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI0 register.
@ -697,6 +861,308 @@
#define NVIC_PRI13_INT53_S 13
#define NVIC_PRI13_INT52_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI14 register.
//
//*****************************************************************************
#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask
#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask
#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask
#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask
#define NVIC_PRI14_INTD_S 29
#define NVIC_PRI14_INTC_S 21
#define NVIC_PRI14_INTB_S 13
#define NVIC_PRI14_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI15 register.
//
//*****************************************************************************
#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask
#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask
#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask
#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask
#define NVIC_PRI15_INTD_S 29
#define NVIC_PRI15_INTC_S 21
#define NVIC_PRI15_INTB_S 13
#define NVIC_PRI15_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI16 register.
//
//*****************************************************************************
#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask
#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask
#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask
#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask
#define NVIC_PRI16_INTD_S 29
#define NVIC_PRI16_INTC_S 21
#define NVIC_PRI16_INTB_S 13
#define NVIC_PRI16_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI17 register.
//
//*****************************************************************************
#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask
#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask
#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask
#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask
#define NVIC_PRI17_INTD_S 29
#define NVIC_PRI17_INTC_S 21
#define NVIC_PRI17_INTB_S 13
#define NVIC_PRI17_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI18 register.
//
//*****************************************************************************
#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask
#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask
#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask
#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask
#define NVIC_PRI18_INTD_S 29
#define NVIC_PRI18_INTC_S 21
#define NVIC_PRI18_INTB_S 13
#define NVIC_PRI18_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI19 register.
//
//*****************************************************************************
#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask
#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask
#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask
#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask
#define NVIC_PRI19_INTD_S 29
#define NVIC_PRI19_INTC_S 21
#define NVIC_PRI19_INTB_S 13
#define NVIC_PRI19_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI20 register.
//
//*****************************************************************************
#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask
#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask
#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask
#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask
#define NVIC_PRI20_INTD_S 29
#define NVIC_PRI20_INTC_S 21
#define NVIC_PRI20_INTB_S 13
#define NVIC_PRI20_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI21 register.
//
//*****************************************************************************
#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask
#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask
#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask
#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask
#define NVIC_PRI21_INTD_S 29
#define NVIC_PRI21_INTC_S 21
#define NVIC_PRI21_INTB_S 13
#define NVIC_PRI21_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI22 register.
//
//*****************************************************************************
#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask
#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask
#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask
#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask
#define NVIC_PRI22_INTD_S 29
#define NVIC_PRI22_INTC_S 21
#define NVIC_PRI22_INTB_S 13
#define NVIC_PRI22_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI23 register.
//
//*****************************************************************************
#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask
#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask
#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask
#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask
#define NVIC_PRI23_INTD_S 29
#define NVIC_PRI23_INTC_S 21
#define NVIC_PRI23_INTB_S 13
#define NVIC_PRI23_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI24 register.
//
//*****************************************************************************
#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask
#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask
#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask
#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask
#define NVIC_PRI24_INTD_S 29
#define NVIC_PRI24_INTC_S 21
#define NVIC_PRI24_INTB_S 13
#define NVIC_PRI24_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI25 register.
//
//*****************************************************************************
#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask
#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask
#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask
#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask
#define NVIC_PRI25_INTD_S 29
#define NVIC_PRI25_INTC_S 21
#define NVIC_PRI25_INTB_S 13
#define NVIC_PRI25_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI26 register.
//
//*****************************************************************************
#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask
#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask
#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask
#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask
#define NVIC_PRI26_INTD_S 29
#define NVIC_PRI26_INTC_S 21
#define NVIC_PRI26_INTB_S 13
#define NVIC_PRI26_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI27 register.
//
//*****************************************************************************
#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask
#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask
#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask
#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask
#define NVIC_PRI27_INTD_S 29
#define NVIC_PRI27_INTC_S 21
#define NVIC_PRI27_INTB_S 13
#define NVIC_PRI27_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI28 register.
//
//*****************************************************************************
#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask
#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask
#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask
#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask
#define NVIC_PRI28_INTD_S 29
#define NVIC_PRI28_INTC_S 21
#define NVIC_PRI28_INTB_S 13
#define NVIC_PRI28_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI29 register.
//
//*****************************************************************************
#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask
#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask
#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask
#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask
#define NVIC_PRI29_INTD_S 29
#define NVIC_PRI29_INTC_S 21
#define NVIC_PRI29_INTB_S 13
#define NVIC_PRI29_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI30 register.
//
//*****************************************************************************
#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask
#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask
#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask
#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask
#define NVIC_PRI30_INTD_S 29
#define NVIC_PRI30_INTC_S 21
#define NVIC_PRI30_INTB_S 13
#define NVIC_PRI30_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI31 register.
//
//*****************************************************************************
#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask
#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask
#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask
#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask
#define NVIC_PRI31_INTD_S 29
#define NVIC_PRI31_INTC_S 21
#define NVIC_PRI31_INTB_S 13
#define NVIC_PRI31_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI32 register.
//
//*****************************************************************************
#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask
#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask
#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask
#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask
#define NVIC_PRI32_INTD_S 29
#define NVIC_PRI32_INTC_S 21
#define NVIC_PRI32_INTB_S 13
#define NVIC_PRI32_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI33 register.
//
//*****************************************************************************
#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
// [4n+3]
#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
// [4n+2]
#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
// [4n+1]
#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
// [4n]
#define NVIC_PRI33_INTD_S 29
#define NVIC_PRI33_INTC_S 21
#define NVIC_PRI33_INTB_S 13
#define NVIC_PRI33_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_PRI34 register.
//
//*****************************************************************************
#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
// [4n+3]
#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
// [4n+2]
#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
// [4n+1]
#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
// [4n]
#define NVIC_PRI34_INTD_S 29
#define NVIC_PRI34_INTC_S 21
#define NVIC_PRI34_INTB_S 13
#define NVIC_PRI34_INTA_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_CPUID register.
@ -708,6 +1174,7 @@
#define NVIC_CPUID_CON_M 0x000F0000 // Constant
#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor
#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
//*****************************************************************************
@ -722,7 +1189,7 @@
#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number
#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
#define NVIC_INT_CTRL_VEC_PEN_NMI \
0x00002000 // NMI
#define NVIC_INT_CTRL_VEC_PEN_HARD \
@ -740,7 +1207,7 @@
#define NVIC_INT_CTRL_VEC_PEN_TICK \
0x0000F000 // SysTick
#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number
#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
#define NVIC_INT_CTRL_VEC_PEN_S 12
#define NVIC_INT_CTRL_VEC_ACT_S 0
@ -750,8 +1217,8 @@
//
//*****************************************************************************
#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset
#define NVIC_VTABLE_OFFSET_S 9
#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset
#define NVIC_VTABLE_OFFSET_S 10
//*****************************************************************************
//
@ -865,6 +1332,8 @@
#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
// Fault
#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
// State Preservation
#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
@ -872,6 +1341,9 @@
#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
// Register Valid
#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
// Floating-Point Lazy State
// Preservation
#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
@ -916,6 +1388,22 @@
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
#define NVIC_FAULT_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_CPAC register.
//
//*****************************************************************************
#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access
// Privilege
#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied
#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only
#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access
#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access
// Privilege
#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied
#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only
#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
@ -1183,7 +1671,47 @@
// The following are defines for the bit fields in the NVIC_SW_TRIG register.
//
//*****************************************************************************
#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID
#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID
#define NVIC_SW_TRIG_INTID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_FPCC register.
//
//*****************************************************************************
#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation
// Enable
#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable
#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready
#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready
#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready
#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready
#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode
#define NVIC_FPCC_USER 0x00000002 // User Privilege Level
#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_FPCA register.
//
//*****************************************************************************
#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address
#define NVIC_FPCA_ADDRESS_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the NVIC_FPDSC register.
//
//*****************************************************************************
#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default
#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default
#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default
#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default
#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode
#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP)
// mode
#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity
// (RM) mode
#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode
#endif // __HW_NVIC_H__

View File

@ -0,0 +1,244 @@
//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following are defines for the SSI register offsets.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // SSI Control 0
#define SSI_O_CR1 0x00000004 // SSI Control 1
#define SSI_O_DR 0x00000008 // SSI Data
#define SSI_O_SR 0x0000000C // SSI Status
#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR0 register.
//
//*****************************************************************************
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
// Serial Frame Format
#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
#define SSI_CR0_SCR_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR1 register.
//
//*****************************************************************************
#define SSI_CR1_EOT 0x00000010 // End of Transmission
#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
// Enable
#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DR register.
//
//*****************************************************************************
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
#define SSI_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_SR register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CPSR register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
#define SSI_CPSR_CPSDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_IM register.
//
//*****************************************************************************
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
// Mask
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_RIS register.
//
//*****************************************************************************
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
// Status
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
// Status
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
// Interrupt Status
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_MIS register.
//
//*****************************************************************************
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
// Interrupt Status
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
// Interrupt Status
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
// Interrupt Status
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_ICR register.
//
//*****************************************************************************
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
// Clear
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DMACTL register.
//
//*****************************************************************************
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CC register.
//
//*****************************************************************************
#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
// PLL bypass is in effect) or the
// PLL output (default)
#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SSI_O_CR0
// register.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_DSS 0x0000000F // Data size select
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SSI_O_CPSR
// register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
//*****************************************************************************
//
// The following are deprecated defines for the SSI controller's FIFO size.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the interrupt
// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
// registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif
#endif // __HW_SSI_H__

View File

@ -2,23 +2,38 @@
//
// hw_sysctl.h - Macros used when accessing the system control hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Firmware Development Package.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -77,6 +92,7 @@
#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating
// Control Register 2
#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
#define SYSCTL_SYSPROP 0x400FE14C // System Properties
#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
// Calibration
#define SYSCTL_CLKVCLR 0x400FE150 // Clock Verification Clear
@ -84,6 +100,9 @@
// Statistics
#define SYSCTL_LDOARST 0x400FE160 // Allow Unregulated LDO to Reset
// the Part
#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0
#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1
#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status
#define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration
#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 ADC
// Digital Comparators
@ -110,6 +129,9 @@
#define SYSCTL_DID0_CLASS_TEMPEST \
0x00040000 // Stellaris(R) Tempest-class
// microcontrollers
#define SYSCTL_DID0_CLASS_FIRESTORM \
0x00060000 // Stellaris(R) Firestorm-class
// microcontrollers
#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
@ -179,6 +201,7 @@
#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150
#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162
#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165
#define SYSCTL_DID1_PRTNO_1166 0x00EC0000 // LM3S1166
#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332
#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435
#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439
@ -188,10 +211,12 @@
#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607
#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608
#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620
#define SYSCTL_DID1_PRTNO_1621 0x00CD0000 // LM3S1621
#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625
#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626
#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627
#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635
#define SYSCTL_DID1_PRTNO_1636 0x00EB0000 // LM3S1636
#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637
#define SYSCTL_DID1_PRTNO_1651 0x00B10000 // LM3S1651
#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751
@ -205,14 +230,29 @@
#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958
#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960
#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968
#define SYSCTL_DID1_PRTNO_1969 0x00EA0000 // LM3S1969
#define SYSCTL_DID1_PRTNO_1B21 0x00CE0000 // LM3S1B21
#define SYSCTL_DID1_PRTNO_1C21 0x00CA0000 // LM3S1C21
#define SYSCTL_DID1_PRTNO_1C26 0x00CB0000 // LM3S1C26
#define SYSCTL_DID1_PRTNO_1C58 0x00980000 // LM3S1C58
#define SYSCTL_DID1_PRTNO_1D21 0x00B00000 // LM3S1D21
#define SYSCTL_DID1_PRTNO_1D26 0x00CC0000 // LM3S1D26
#define SYSCTL_DID1_PRTNO_1F11 0x001D0000 // LM3S1F11
#define SYSCTL_DID1_PRTNO_1F16 0x001B0000 // LM3S1F16
#define SYSCTL_DID1_PRTNO_1G21 0x00AF0000 // LM3S1G21
#define SYSCTL_DID1_PRTNO_1G58 0x00950000 // LM3S1G58
#define SYSCTL_DID1_PRTNO_1H11 0x001E0000 // LM3S1H11
#define SYSCTL_DID1_PRTNO_1H16 0x001C0000 // LM3S1H16
#define SYSCTL_DID1_PRTNO_1J11 0x000F0000 // LM3S1J11
#define SYSCTL_DID1_PRTNO_1J16 0x003C0000 // LM3S1J16
#define SYSCTL_DID1_PRTNO_1N11 0x000E0000 // LM3S1N11
#define SYSCTL_DID1_PRTNO_1N16 0x003B0000 // LM3S1N16
#define SYSCTL_DID1_PRTNO_1P51 0x00B20000 // LM3S1P51
#define SYSCTL_DID1_PRTNO_1R21 0x009E0000 // LM3S1R21
#define SYSCTL_DID1_PRTNO_1R26 0x00C90000 // LM3S1R26
#define SYSCTL_DID1_PRTNO_1W16 0x00300000 // LM3S1W16
#define SYSCTL_DID1_PRTNO_1Z16 0x002F0000 // LM3S1Z16
#define SYSCTL_DID1_PRTNO_2016 0x00D40000 // LM3S2016
#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276
@ -234,13 +274,17 @@
#define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793
#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911
#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918
#define SYSCTL_DID1_PRTNO_2919 0x00ED0000 // LM3S2919
#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
#define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93
#define SYSCTL_DID1_PRTNO_2D93 0x00940000 // LM3S2D93
#define SYSCTL_DID1_PRTNO_2U93 0x00930000 // LM3S2U93
#define SYSCTL_DID1_PRTNO_3634 0x00080000 // LM3S3634
#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651
#define SYSCTL_DID1_PRTNO_3654 0x00C80000 // LM3S3654
#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739
#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748
#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749
@ -265,15 +309,28 @@
#define SYSCTL_DID1_PRTNO_5951 0x000B0000 // LM3S5951
#define SYSCTL_DID1_PRTNO_5956 0x004E0000 // LM3S5956
#define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91
#define SYSCTL_DID1_PRTNO_5C31 0x002E0000 // LM3S5C31
#define SYSCTL_DID1_PRTNO_5C36 0x002C0000 // LM3S5C36
#define SYSCTL_DID1_PRTNO_5C51 0x005E0000 // LM3S5C51
#define SYSCTL_DID1_PRTNO_5C56 0x005B0000 // LM3S5C56
#define SYSCTL_DID1_PRTNO_5D51 0x005F0000 // LM3S5D51
#define SYSCTL_DID1_PRTNO_5D56 0x005C0000 // LM3S5D56
#define SYSCTL_DID1_PRTNO_5D91 0x00870000 // LM3S5D91
#define SYSCTL_DID1_PRTNO_5G31 0x002D0000 // LM3S5G31
#define SYSCTL_DID1_PRTNO_5G36 0x001F0000 // LM3S5G36
#define SYSCTL_DID1_PRTNO_5G51 0x005D0000 // LM3S5G51
#define SYSCTL_DID1_PRTNO_5G56 0x004F0000 // LM3S5G56
#define SYSCTL_DID1_PRTNO_5K31 0x00090000 // LM3S5K31
#define SYSCTL_DID1_PRTNO_5K36 0x004A0000 // LM3S5K36
#define SYSCTL_DID1_PRTNO_5P31 0x000A0000 // LM3S5P31
#define SYSCTL_DID1_PRTNO_5P36 0x00480000 // LM3S5P36
#define SYSCTL_DID1_PRTNO_5P3B 0x00B60000 // LM3S5P3B
#define SYSCTL_DID1_PRTNO_5P51 0x000D0000 // LM3S5P51
#define SYSCTL_DID1_PRTNO_5P56 0x004C0000 // LM3S5P56
#define SYSCTL_DID1_PRTNO_5R31 0x00070000 // LM3S5R31
#define SYSCTL_DID1_PRTNO_5R36 0x004B0000 // LM3S5R36
#define SYSCTL_DID1_PRTNO_5T36 0x00470000 // LM3S5T36
#define SYSCTL_DID1_PRTNO_5U91 0x007F0000 // LM3S5U91
#define SYSCTL_DID1_PRTNO_5Y36 0x00460000 // LM3S5Y36
#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
@ -288,12 +345,18 @@
#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753
#define SYSCTL_DID1_PRTNO_6816 0x00D10000 // LM3S6816
#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911
#define SYSCTL_DID1_PRTNO_6916 0x00D30000 // LM3S6916
#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918
#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950
#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
#define SYSCTL_DID1_PRTNO_6C11 0x00AA0000 // LM3S6C11
#define SYSCTL_DID1_PRTNO_6C65 0x00AC0000 // LM3S6C65
#define SYSCTL_DID1_PRTNO_6G11 0x009F0000 // LM3S6G11
#define SYSCTL_DID1_PRTNO_6G65 0x00AB0000 // LM3S6G65
#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530
#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538
#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630
@ -306,16 +369,41 @@
#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971
#define SYSCTL_DID1_PRTNO_8C62 0x00AE0000 // LM3S8C62
#define SYSCTL_DID1_PRTNO_8G62 0x00AD0000 // LM3S8G62
#define SYSCTL_DID1_PRTNO_9781 0x00CF0000 // LM3S9781
#define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790
#define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792
#define SYSCTL_DID1_PRTNO_9971 0x002D0000 // LM3S9971
#define SYSCTL_DID1_PRTNO_9997 0x00200000 // LM3S9997
#define SYSCTL_DID1_PRTNO_9B81 0x00D00000 // LM3S9B81
#define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90
#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92
#define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95
#define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96
#define SYSCTL_DID1_PRTNO_9BN2 0x001D0000 // LM3S9BN2
#define SYSCTL_DID1_PRTNO_9BN5 0x001E0000 // LM3S9BN5
#define SYSCTL_DID1_PRTNO_9BN6 0x001F0000 // LM3S9BN6
#define SYSCTL_DID1_PRTNO_9C97 0x00700000 // LM3S9C97
#define SYSCTL_DID1_PRTNO_9CN5 0x007A0000 // LM3S9CN5
#define SYSCTL_DID1_PRTNO_9D81 0x00A90000 // LM3S9D81
#define SYSCTL_DID1_PRTNO_9D90 0x007E0000 // LM3S9D90
#define SYSCTL_DID1_PRTNO_9D92 0x00920000 // LM3S9D92
#define SYSCTL_DID1_PRTNO_9D95 0x00C80000 // LM3S9D95
#define SYSCTL_DID1_PRTNO_9D96 0x009D0000 // LM3S9D96
#define SYSCTL_DID1_PRTNO_9DN5 0x007B0000 // LM3S9DN5
#define SYSCTL_DID1_PRTNO_9DN6 0x007C0000 // LM3S9DN6
#define SYSCTL_DID1_PRTNO_9G97 0x00600000 // LM3S9G97
#define SYSCTL_DID1_PRTNO_9GN5 0x00790000 // LM3S9GN5
#define SYSCTL_DID1_PRTNO_9L71 0x001B0000 // LM3S9L71
#define SYSCTL_DID1_PRTNO_9L97 0x00180000 // LM3S9L97
#define SYSCTL_DID1_PRTNO_9U81 0x00A80000 // LM3S9U81
#define SYSCTL_DID1_PRTNO_9U90 0x007D0000 // LM3S9U90
#define SYSCTL_DID1_PRTNO_9U92 0x00900000 // LM3S9U92
#define SYSCTL_DID1_PRTNO_9U95 0x00B70000 // LM3S9U95
#define SYSCTL_DID1_PRTNO_9U96 0x009B0000 // LM3S9U96
#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package
#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package
#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package
#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package
@ -353,6 +441,7 @@
#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_48KB 0x00BF0000 // 48 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM
#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
@ -362,7 +451,10 @@
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
#define SYSCTL_DC0_FLASHSZ_384K 0x000000BF // 384 KB of Flash
#define SYSCTL_DC0_FLASHSZ_512K 0x000000FF // 512 KB of Flash
#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
@ -375,7 +467,8 @@
#define SYSCTL_DC1_CAN2 0x04000000 // CAN Module 2 Present
#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present
#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present
#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present
#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
@ -385,18 +478,21 @@
// 6 minimum
#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
// with a PLL divider of 4
#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock
// with a PLL divider of 5
#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
// PLL divider of 8
#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
// PLL divider of 10
#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second
#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second
#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second
#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second
#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second
#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second
#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
@ -421,7 +517,9 @@
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed
#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed
#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
@ -650,7 +748,7 @@
#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control
#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control
#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control
#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
@ -831,6 +929,10 @@
#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz
#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz
#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz
#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz
#define SYSCTL_RCC_PLLVER 0x00000400 // PLL Verification
#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
@ -977,6 +1079,8 @@
// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
//
//*****************************************************************************
#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
//*****************************************************************************
@ -988,7 +1092,7 @@
#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control
#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control
#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
@ -1067,7 +1171,7 @@
#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control
#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control
#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
@ -1146,7 +1250,7 @@
#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control
#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control
#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
@ -1271,9 +1375,18 @@
#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
#define SYSCTL_DSLPCLKCFG_PIOSCPD \
0x00000002 // PIOSC Power Down Request
#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source
#define SYSCTL_DSLPCLKCFG_D_S 23
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
//
//*****************************************************************************
#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
@ -1318,6 +1431,35 @@
//*****************************************************************************
#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
// register.
//
//*****************************************************************************
#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
#define SYSCTL_PLLFREQ0_MFRAC_S 10
#define SYSCTL_PLLFREQ0_MINT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
// register.
//
//*****************************************************************************
#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
#define SYSCTL_PLLFREQ1_Q_S 8
#define SYSCTL_PLLFREQ1_N_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
//
//*****************************************************************************
#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG
@ -1430,9 +1572,15 @@
// register.
//
//*****************************************************************************
#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present
#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present
@ -1485,6 +1633,7 @@
// register.
//
//*****************************************************************************
#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control
#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control
#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control
@ -1561,6 +1710,7 @@
// register.
//
//*****************************************************************************
#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control
#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control
@ -1570,6 +1720,7 @@
// register.
//
//*****************************************************************************
#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control
#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control
@ -1579,6 +1730,7 @@
// register.
//
//*****************************************************************************
#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control
#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control

View File

@ -2,23 +2,38 @@
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Firmware Development Package.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -115,6 +130,12 @@ typedef unsigned char tBoolean;
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
#endif
#ifndef CLASS_IS_FIRESTORM
#define CLASS_IS_FIRESTORM \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
#endif
#ifndef REVISION_IS_A0
#define REVISION_IS_A0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
@ -169,6 +190,12 @@ typedef unsigned char tBoolean;
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
#endif
#ifndef REVISION_IS_C5
#define REVISION_IS_C5 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5))
#endif
//*****************************************************************************
//
// Deprecated silicon class and revision detection macros.

View File

@ -2,23 +2,38 @@
//
// hw_uart.h - Macros and defines used when accessing the UART hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// This is part of revision 6852 of the Stellaris Firmware Development Package.
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 10636 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -49,6 +64,10 @@
#define UART_O_LCTL 0x00000090 // UART LIN Control
#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
#define UART_O_LTIM 0x00000098 // UART LIN Timer
#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
#define UART_O_CC 0x00000FC8 // UART Clock Configuration
//*****************************************************************************
//
@ -185,6 +204,7 @@
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
// Mask
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
@ -215,6 +235,7 @@
// Status
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
// Interrupt Status
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
@ -249,6 +270,8 @@
// Status
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
// Interrupt Status
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
// Status
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
@ -277,10 +300,11 @@
// The following are defines for the bit fields in the UART_O_ICR register.
//
//*****************************************************************************
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
@ -335,6 +359,42 @@
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
#define UART_LTIM_TIMER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITADDR
// register.
//
//*****************************************************************************
#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
#define UART_9BITADDR_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITAMASK
// register.
//
//*****************************************************************************
#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
#define UART_9BITAMASK_MASK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_PP register.
//
//*****************************************************************************
#define UART_PP_NB 0x00000002 // 9-Bit Support
#define UART_PP_SC 0x00000001 // Smart Card Support
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CC register.
//
//*****************************************************************************
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
//*****************************************************************************
//
// The following definitions are deprecated.
@ -418,6 +478,10 @@
// register.
//
//*****************************************************************************
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
UART_RSR_FE)

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