mirror of https://github.com/FOME-Tech/openblt.git
150 lines
7.4 KiB
ArmAsm
150 lines
7.4 KiB
ArmAsm
/************************************************************************************//**
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* \file ARM7_LPC2000\GCC\cstart.s
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* \brief Bootloader C-startup assembly file.
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* \ingroup Target_ARM7_LPC2000
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* \internal
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*----------------------------------------------------------------------------------------
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* C O P Y R I G H T
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*----------------------------------------------------------------------------------------
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* Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
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*
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*----------------------------------------------------------------------------------------
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* L I C E N S E
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*----------------------------------------------------------------------------------------
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* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 3 of the License, or (at your option) any later
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* version.
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*
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* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You have received a copy of the GNU General Public License along with OpenBLT. It
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* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
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*
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* \endinternal
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****************************************************************************************/
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/****************************************************************************************
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* Macro definitions
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****************************************************************************************/
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/* stack Sizes */
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.set UND_STACK_SIZE, 0x00000004 /* stack for "undef" interrupts is 4 bytes */
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.set ABT_STACK_SIZE, 0x00000004 /* stack for "abort" interrupts is 4 bytes */
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.set FIQ_STACK_SIZE, 0x00000004 /* stack for "FIQ" interrupts is 4 bytes */
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.set IRQ_STACK_SIZE, 0X00000004 /* stack for "IRQ" normal interrupts is 4 bytes */
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.set SVC_STACK_SIZE, 0x00000004 /* stack for "SVC" supervisor mode is 4 bytes */
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/* mode bits and Interrupt (I & F) flags in program status registers (PSRs) */
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.set MODE_USR, 0x10 /* Normal User Mode */
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.set MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
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.set MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
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.set MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
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.set MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
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.set MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
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.set MODE_SYS, 0x1F /* System Running Priviledged OS Tasks Mode */
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.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
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.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
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/* microcontroller registers */
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.set MEMMAP, 0xE01FC040 /* MEMMAP register */
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.text
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.arm
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.global Reset_Handler
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.global SetupRAM
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.global _startup
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.func _startup
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_startup:
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/****************************************************************************************
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* Interrupt vector table
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****************************************************************************************/
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_vectors: ldr PC, Reset_Addr /* point to Reset_Handler address */
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ldr PC, Undef_Addr /* point to UNDEF_ISR address */
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ldr PC, Undef_Addr /* point to SWI_ISR address */
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ldr PC, PAbt_Addr /* point to UNDEF_ISR address */
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ldr PC, DAbt_Addr /* point to UNDEF_ISR address */
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nop /* reserved for Philips ISP checksum */
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ldr PC, IRQ_Addr /* point to IRQ_ISR address */
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ldr PC, FIQ_Addr /* point to FIQ_ISR address */
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Reset_Addr: .word Reset_Handler /* defined in this module below */
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Undef_Addr: .word UNDEF_ISR /* defined in vectors.c */
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PAbt_Addr: .word UNDEF_ISR /* defined in vectors.c */
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DAbt_Addr: .word UNDEF_ISR /* defined in vectors.c */
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FIQ_Addr: .word FIQ_ISR /* defined in vectors.c */
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IRQ_Addr: .word IRQ_ISR /* defined in vectors.c */
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.word 0 /* rounds vectors and ISR addresses to */
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/* 64 bytes */
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/************************************************************************************//**
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** \brief Reset interrupt service routine. Configures the stack for each mode,
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** disables the IRQ and FIQ interrupts, initializes RAM and jumps to
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** function main.
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** \return none.
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**
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****************************************************************************************/
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Reset_Handler:
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/* setup a stack and disable interrupts for each mode */
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ldr r0, =_stack_end
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msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
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mov sp, r0
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sub r0, r0, #UND_STACK_SIZE
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msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
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mov sp, r0
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sub r0, r0, #ABT_STACK_SIZE
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msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
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mov sp, r0
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sub r0, r0, #FIQ_STACK_SIZE
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msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
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mov sp, r0
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sub r0, r0, #IRQ_STACK_SIZE
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msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
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mov sp, r0
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sub r0, r0, #SVC_STACK_SIZE
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msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* User Mode */
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mov sp, r0
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/* copy .data section from ROM to RAM and zero out .bss section */
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bl SetupRAM
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/* start bootloader program by jumping to main() */
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b main
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/*** end of Reset_Handler ***/
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/************************************************************************************//**
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** \brief Initializes RAM by copying .data section from ROM to RAM and zero-ing
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** out .bss section.
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** \return none.
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**
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****************************************************************************************/
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SetupRAM:
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/* copy .data section (Copy from ROM to RAM) */
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ldr R1, =_etext
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ldr R2, =_data
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ldr R3, =_edata
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1: cmp R2, R3
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ldrlo R0, [R1], #4
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strlo R0, [R2], #4
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blo 1b
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/* clear .bss section (Zero init) */
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mov R0, #0
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ldr R1, =_bss_start
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ldr R2, =_bss_end
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2: cmp R1, R2
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strlo R0, [R1], #4
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blo 2b
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/* return */
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bx lr
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/*** end of SetupRAM ***/
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.endfunc
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.end
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/*********************************** end of cstart.s ***********************************/
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