315 lines
12 KiB
Plaintext
315 lines
12 KiB
Plaintext
This file specifies the format of USB packets used for in-band data
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transmission and signaling on the USRP. All packets are 512-byte long,
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and are transfered using USB "bulk" transfers.
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IN packets are sent towards the host.
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OUT packets are sent away from the host.
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The layout is 32-bits wide. All data is transmitted in little-endian
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format across the USB.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|O|U|D|S|E| RSSI | Chan | mbz | Tag | Payload Len |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Timestamp |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| |
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+ +
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| Payload |
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. .
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. .
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. .
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+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| ... | .
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+-+-+-+-+-+-+-+ .
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. .
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. Padding .
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. .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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mbz Must be Zero: these bits must be zero in both IN and OUT packets.
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O Overrun Flag: set in an IN packet if an overrun condition was
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detected. Must be zero in OUT packets. Overrun occurs when
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the FPGA has data to transmit to the host and there is no
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buffer space available. This generally indicates a problem on
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the host. Either it is not keeping up, or it has configured
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the FPGA to transmit data at a higher rate than the transport
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(USB) can support.
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U Underrun Flag: set in an IN packet if an underrun condition
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was detected. Must be zero in OUT packets. Underrun occurs
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when the FPGA runs out of samples, and it's not between
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bursts. See the "End of Burst flag" below.
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D Dropped Packet Flag: Set in an IN packet if the FPGA
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discarded an OUT packet because its timestamp had already
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passed.
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S Start of Burst Flag: Set in an OUT packet if the data is the
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first segment of what is logically a continuous burst of data.
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Must be zero in IN packets.
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E End of Burst Flag: Set in an OUT packet if the data is the
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last segment of what is logically a continuous burst of data.
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Must be zero in IN packets. Underruns are not reported
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when the FPGA runs out of samples between bursts.
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RSSI 6-bit Received Strength Signal Indicator: Must be zero in OUT
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packets. In IN packets, indicates RSSI as reported by front end.
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FIXME The format and interpretation are to be determined.
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Chan 5-bit logical channel number. Channel number 0x1f is reserved
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for control information. See "Control Channel" below. Other
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channels are "data channels." Each data channel is logically
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independent of the others. A data channel payload field
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contains a sequence of homogeneous samples. The format of the
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samples is determined by the configuration associated with the
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given channel. It is often the case that the payload field
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contains 32-bit complex samples, each containing 16-bit real
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and imaginary components.
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Tag 4-bit tag for matching IN packets with OUT packets.
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[FIXME, write more...]
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Payload Len: 9-bit field that specifies the length of the payload
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field in bytes. Must be in the range 0 to 504 inclusive.
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Timestamp: 32-bit timestamp.
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On IN packets, the timestamp indicates the time at which the
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first sample of the packet was produced by the A/D converter(s)
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for that channel. On OUT packets, the timestamp specifies the
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time at which the first sample in the packet should go out the
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D/A converter(s) for that channel. If a packet reaches the
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head of the transmit queue, and the current time is later than
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the timestamp, an error is assumed to have occurred and the
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packet is discarded. As a special case, the timestamp
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0xffffffff is interpreted as "Now".
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The time base is a free running 32-bit counter that is
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incremented by the A/D sample-clock.
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Payload: Variable length field. Length is specified by the
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Payload Len field.
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Padding: This field is 504 - Payload Len bytes long, and its content
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is unspecified. This field pads the packet out to a constant
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512 bytes.
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"Data Channel" payload format:
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-------------------------------
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If Chan != 0x1f, the packet is a "data packet" and the payload is a
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sequence of homogeneous samples. The format of the samples is
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determined by the configuration associated with the given channel.
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It is often the case that the payload field contains 32-bit complex
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samples, each containing 16-bit real and imaginary components.
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"Control Channel" payload format:
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---------------------------------
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If Chan == 0x1f, the packet is a "control packet". The control channel
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payload consists of a sequence of 0 or more sub-packets.
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Each sub-packet starts on a 32-bit boundary, and consists of an 8-bit
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Opcode field, an 8-bit Length field, Length bytes of arguments, and 0,
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1, 2 or 3 bytes of padding to align the tail of the sub-packet to
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a 32-bit boundary.
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Control channel packets shall be processed at the head of the queue,
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and shall observe the timestamp semantics described above.
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General sub-packet format:
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--------------------------
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+
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| Opcode | Length | <length bytes> ... |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+
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Specific sub-packet formats:
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----------------------------
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RID: 6-bit Request-ID. Copied from request sub-packet into corresponding
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reply sub-packet. RID allows the host to match requests and replies.
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Reg Number: 10-bit Register Number.
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Ping Fixed Length:
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Opcode: OP_PING_FIXED
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Ping Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Ping Fixed Length Reply:
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Opcode: OP_PING_FIXED_REPLY
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Ping Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Write Register:
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Opcode: OP_WRITE_REG
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 6 | mbz | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Write Register Masked:
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Opcode: OP_WRITE_REG_MASKED
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REG[Num] = (REG[Num] & ~Mask) | (Value & Mask)
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That is, only the register bits that correspond to 1's in the
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mask are written with the new value.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 10 | mbz | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Mask Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Read Register:
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Opcode: OP_READ_REG
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Read Register Reply:
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Opcode: OP_READ_REG_REPLY
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 6 | RID | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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I2C Write:
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Opcode: OP_I2C_WRITE
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I2C Addr: 7-bit I2C address
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Data: The bytes to write to the I2C bus
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Length: Length of Data + 2
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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I2C Read:
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Opcode: OP_I2C_READ
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I2C Addr: 7-bit I2C address
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Nbytes: Number of bytes to read from I2C bus
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 3 | RID | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Nbytes | unspecified padding |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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I2C Read Reply:
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Opcode: OP_I2C_READ_REPLY
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I2C Addr: 7-bit I2C address
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Data: Length - 2 bytes of data read from I2C bus.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | RID | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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SPI Write:
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Opcode: OP_SPI_WRITE
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Enables: Which SPI enables to assert (mask)
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Format: Specifies format of SPI data and Opt Header Bytes
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Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format
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Data: The bytes to write to the SPI bus
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Length: Length of Data + 6
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Enables | Format | Opt Header Bytes |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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SPI Read:
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Opcode: OP_SPI_READ
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Enables: Which SPI enables to assert (mask)
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Format: Specifies format of SPI data and Opt Header Bytes
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Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format
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Nbytes: Number of bytes to read from SPI bus.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 7 | RID | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Enables | Format | Opt Header Bytes |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Nbytes | unspecified padding |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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SPI Read Reply:
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Opcode: OP_SPI_READ_REPLY
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Data: Length - 2 bytes of data read from SPI bus.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | RID | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Delay:
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Opcode: OP_DELAY
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Ticks: 16-bit unsigned delay count
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Delay Ticks clock ticks before executing next operation.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | Ticks |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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