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srsLTE
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ctest: PDCCH test skips 100PRB for non AVX2 machines 

The current 8-bit Viterbi decoder implementation for SSE (non-AVX2)
is not accurate enough to reliably decode all messages with a
code rate ~0.9 or higher, e.g. DCI format 2/2A messages in 100 PRB cell
at aggregation level 0.
This commit is contained in:
Robert Falkenberg 2022-06-09 14:09:05 +02:00
parent 981e682d2e
commit 06f2ab6d7c
1 changed files with 3 additions and 2 deletions
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5
lib/src/phy/phch/test/CMakeLists.txt
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@ -199,8 +199,9 @@ add_executable(pdcch_test pdcch_test.c)
target_link_libraries(pdcch_test srsran_phy)
foreach (nof_prb 6 15 25 50 75 100)
# Currently, the ARM platforms srsRAN has been tested are not capable of running 100PRB. So, skip 100 PRB in ARM
if (HAVE_NEON AND (${nof_prb} EQUAL 100))
# Currently, the ARM and SSE platforms srsRAN has been tested are not capable of running 100PRB. So, skip 100 PRB in
# ARM and SSE.
if ((HAVE_NEON OR NOT HAVE_AVX2) AND (${nof_prb} EQUAL 100))
continue()
endif ()
foreach (nof_ports 1 2)