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srsLTE
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sched,nr: fill remaining DCI fields of RAR in NR scheduler

This commit is contained in:
Francisco Paisana 2021-08-25 17:18:31 +02:00
parent da4b7e4f80
commit 8686a17f69
7 changed files with 55 additions and 25 deletions
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25
srsenb/src/stack/mac/nr/sched_nr_grant_allocator.cc
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@ -129,7 +129,7 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
}
// RAR allocation successful.
bwp_pdcch_slot.dl_prbs |= interv;
// Generate DCI for RAR with given RA-RNTI
pdcch_dl_t& pdcch = bwp_pdcch_slot.dl_pdcchs.back();
if (not fill_dci_rar(interv, ra_rnti, *bwp_grid.cfg, pdcch.dci)) {
@ -137,22 +137,29 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
return alloc_result::invalid_coderate;
}
auto& phy_cfg = (*slot_ues)[pending_rars[0].temp_crnti].cfg->phy();
pdcch.dci_cfg = phy_cfg.get_dci_cfg();
// Generate RAR PDSCH
bwp_pdcch_slot.dl_prbs |= interv;
// TODO: Properly fill Msg3 grants
bwp_pdcch_slot.pdschs.emplace_back();
pdsch_t& pdsch = bwp_pdcch_slot.pdschs.back();
srsran_slot_cfg_t slot_cfg;
slot_cfg.idx = pdcch_slot.slot_idx();
bool success = phy_cfg.get_pdsch_cfg(slot_cfg, pdcch.dci, pdsch.sch);
srsran_assert(success, "Error converting DCI to grant");
// Generate Msg3 grants in PUSCH
uint32_t last_msg3 = msg3_rbs.start();
const int mcs = 0, max_harq_msg3_retx = 4;
int dai = 0;
srsran_slot_cfg_t slot_cfg;
slot_cfg.idx = msg3_slot.slot_idx();
uint32_t last_msg3 = msg3_rbs.start();
const int mcs = 0, max_harq_msg3_retx = 4;
int dai = 0;
slot_cfg.idx = msg3_slot.slot_idx();
for (const dl_sched_rar_info_t& grant : pending_rars) {
slot_ue& ue = (*slot_ues)[grant.temp_crnti];
// Allocate Msg3
prb_interval msg3_interv{last_msg3, last_msg3 + msg3_nof_prbs};
ue.h_ul = ue.harq_ent->find_empty_ul_harq();
bool success = ue.h_ul->new_tx(msg3_slot, msg3_slot, msg3_interv, mcs, 100, max_harq_msg3_retx);
ue.h_ul = ue.harq_ent->find_empty_ul_harq();
success = ue.h_ul->new_tx(msg3_slot, msg3_slot, msg3_interv, mcs, 100, max_harq_msg3_retx);
srsran_assert(success, "Failed to allocate Msg3");
last_msg3 += msg3_nof_prbs;
pdcch_ul_t msg3_pdcch; // dummy PDCCH for retx=0

3
srsenb/test/mac/nr/CMakeLists.txt
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@ -8,9 +8,10 @@
add_library(sched_nr_test_suite sched_nr_common_test.cc sched_nr_ue_ded_test_suite.cc)
add_executable(sched_nr_test sched_nr_test.cc sched_nr_sim_ue.cc sched_nr_ue_ded_test_suite.cc)
add_executable(sched_nr_test sched_nr_test.cc sched_nr_sim_ue.cc)
target_link_libraries(sched_nr_test
srsgnb_mac
sched_nr_test_suite
srsran_common
${CMAKE_THREAD_LIBS_INIT}
${Boost_LIBRARIES})

16
srsenb/test/mac/nr/sched_nr_common_test.cc
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@ -15,13 +15,27 @@
namespace srsenb {
void test_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs)
void test_dl_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs)
{
for (const auto& pdcch : dl_pdcchs) {
if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_ra) {
TESTASSERT_EQ(pdcch.dci.ctx.format, srsran_dci_format_nr_1_0);
TESTASSERT_EQ(pdcch.dci.ctx.ss_type, srsran_search_space_type_common_1);
TESTASSERT(pdcch.dci.ctx.location.L > 0);
} else if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_c) {
TESTASSERT(pdcch.dci.ctx.format == srsran_dci_format_nr_1_0 or pdcch.dci.ctx.format == srsran_dci_format_nr_1_1);
}
}
}
void test_pdsch_consistency(srsran::const_span<mac_interface_phy_nr::pdsch_t> pdschs)
{
for (const mac_interface_phy_nr::pdsch_t& pdsch : pdschs) {
TESTASSERT(pdsch.sch.grant.nof_layers > 0);
if (pdsch.sch.grant.rnti_type == srsran_rnti_type_c) {
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx != nullptr);
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->buffer_b != nullptr);
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->max_cb > 0);
}
}
}

5
srsenb/test/mac/nr/sched_nr_common_test.h
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@ -18,8 +18,9 @@
namespace srsenb {
void test_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcch);
void test_dl_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcch);
void test_pdsch_consistency(srsran::const_span<mac_interface_phy_nr::pdsch_t> dl_pdcch);
}
} // namespace srsenb
#endif // SRSRAN_SCHED_NR_COMMON_TEST_H

16
srsenb/test/mac/nr/sched_nr_rar_test.cc
View File

@ -17,8 +17,7 @@
#include "srsran/support/srsran_test.h"
#include <random>
uint32_t seed = 155556739;
// std::chrono::system_clock::now().time_since_epoch().count();
uint32_t seed = std::chrono::system_clock::now().time_since_epoch().count();
namespace srsenb {
@ -53,6 +52,7 @@ void test_single_prach()
const bwp_slot_grid* result = nullptr;
auto run_slot = [&alloc, &rasched, &pdcch_slot, &slot_ues, &u]() -> const bwp_slot_grid* {
mac_logger.set_context(pdcch_slot.to_uint());
u.carriers[0]->new_slot(pdcch_slot, u.cfg());
slot_ues.clear();
slot_ues.insert(rnti, u.try_reserve(pdcch_slot, 0));
alloc.new_slot(pdcch_slot, slot_ues);
@ -60,7 +60,7 @@ void test_single_prach()
alloc.log_bwp_sched_result();
const bwp_slot_grid* result = &alloc.res_grid()[alloc.get_pdcch_tti()];
test_pdcch_consistency(result->dl_pdcchs);
test_dl_pdcch_consistency(result->dl_pdcchs);
++pdcch_slot;
return result;
};
@ -83,6 +83,7 @@ void test_single_prach()
// RAR is scheduled
const uint32_t prach_duration = 1;
slot_point rar_slot;
while (true) {
slot_point current_slot = pdcch_slot;
result = run_slot();
@ -93,11 +94,18 @@ void test_single_prach()
TESTASSERT_EQ(pdcch.dci.ctx.rnti, ra_rnti);
TESTASSERT_EQ(pdcch.dci.ctx.rnti_type, srsran_rnti_type_ra);
TESTASSERT(current_slot < prach_slot + prach_duration + bwpparams.cfg.rar_window_size);
rar_slot = current_slot;
break;
} else {
TESTASSERT(result->dl_pdcchs.empty());
}
}
slot_point msg3_slot = rar_slot + bwpparams.pusch_ra_list[0].msg3_delay;
while (pdcch_slot <= msg3_slot) {
result = run_slot();
}
TESTASSERT(result->puschs.size() == 1);
}
} // namespace srsenb
@ -111,7 +119,7 @@ int main(int argc, char** argv)
srsran::test_init(argc, argv);
printf("Test seed=%u\n", seed);
printf("Test random seed=%u\n\n", seed);
srsenb::test_single_prach();
}

7
srsenb/test/mac/nr/sched_nr_sim_ue.cc
View File

@ -11,6 +11,7 @@
*/
#include "sched_nr_sim_ue.h"
#include "sched_nr_common_test.h"
#include "sched_nr_ue_ded_test_suite.h"
#include "srsran/common/test_common.h"
@ -157,6 +158,12 @@ void sched_nr_sim_base::update(sched_nr_cc_output_res_t& cc_out)
sim_nr_enb_ctxt_t ctxt;
ctxt = get_enb_ctxt();
// Run common tests
test_dl_pdcch_consistency(cc_out.dl_cc_result->pdcch_dl);
test_pdsch_consistency(cc_out.dl_cc_result->pdsch);
// Run UE-dedicated tests
test_dl_sched_result(ctxt, cc_out);
for (auto& u : ue_db) {

8
srsenb/test/mac/nr/sched_nr_ue_ded_test_suite.cc
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@ -22,7 +22,6 @@ void test_dl_sched_result(const sim_nr_enb_ctxt_t& enb_ctxt, const sched_nr_cc_o
{
slot_point pdcch_slot = cc_out.slot;
const pdcch_dl_list_t& pdcchs = cc_out.dl_cc_result->pdcch_dl;
const pdsch_list_t& pdschs = cc_out.dl_cc_result->pdsch;
// Iterate over UE PDCCH allocations
for (const pdcch_dl_t& pdcch : pdcchs) {
@ -40,7 +39,6 @@ void test_dl_sched_result(const sim_nr_enb_ctxt_t& enb_ctxt, const sched_nr_cc_o
TESTASSERT(ue.ue_cfg.phy_cfg.pdcch.coreset_present[pdcch.dci.ctx.coreset_id]);
const auto& coreset = ue.ue_cfg.phy_cfg.pdcch.coreset[pdcch.dci.ctx.coreset_id];
TESTASSERT(coreset.id == pdcch.dci.ctx.coreset_id);
TESTASSERT(pdcch.dci.ctx.format == srsran_dci_format_nr_1_0 or pdcch.dci.ctx.format == srsran_dci_format_nr_1_1);
// CHECK: UCI
if (pdcch.dci.ctx.format == srsran_dci_format_nr_1_0) {
@ -50,12 +48,6 @@ void test_dl_sched_result(const sim_nr_enb_ctxt_t& enb_ctxt, const sched_nr_cc_o
}
TESTASSERT(ue.cc_list[cc_out.cc].pending_acks[(pdcch_slot + k1).to_uint()] % 4 == pdcch.dci.dai);
}
for (const pdsch_t& pdsch : pdschs) {
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx != nullptr);
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->buffer_b != nullptr);
TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->max_cb > 0);
}
}
} // namespace srsenb