mirror of https://github.com/PentHertz/srsLTE.git
sched,nr: fill remaining DCI fields of RAR in NR scheduler
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da4b7e4f80
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8686a17f69
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@ -129,7 +129,7 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
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}
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// RAR allocation successful.
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bwp_pdcch_slot.dl_prbs |= interv;
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// Generate DCI for RAR with given RA-RNTI
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pdcch_dl_t& pdcch = bwp_pdcch_slot.dl_pdcchs.back();
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if (not fill_dci_rar(interv, ra_rnti, *bwp_grid.cfg, pdcch.dci)) {
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@ -137,14 +137,21 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
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bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
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return alloc_result::invalid_coderate;
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}
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auto& phy_cfg = (*slot_ues)[pending_rars[0].temp_crnti].cfg->phy();
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pdcch.dci_cfg = phy_cfg.get_dci_cfg();
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// Generate RAR PDSCH
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bwp_pdcch_slot.dl_prbs |= interv;
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// TODO: Properly fill Msg3 grants
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bwp_pdcch_slot.pdschs.emplace_back();
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pdsch_t& pdsch = bwp_pdcch_slot.pdschs.back();
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srsran_slot_cfg_t slot_cfg;
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slot_cfg.idx = pdcch_slot.slot_idx();
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bool success = phy_cfg.get_pdsch_cfg(slot_cfg, pdcch.dci, pdsch.sch);
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srsran_assert(success, "Error converting DCI to grant");
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// Generate Msg3 grants in PUSCH
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uint32_t last_msg3 = msg3_rbs.start();
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const int mcs = 0, max_harq_msg3_retx = 4;
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int dai = 0;
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srsran_slot_cfg_t slot_cfg;
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slot_cfg.idx = msg3_slot.slot_idx();
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for (const dl_sched_rar_info_t& grant : pending_rars) {
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slot_ue& ue = (*slot_ues)[grant.temp_crnti];
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@ -152,7 +159,7 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
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// Allocate Msg3
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prb_interval msg3_interv{last_msg3, last_msg3 + msg3_nof_prbs};
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ue.h_ul = ue.harq_ent->find_empty_ul_harq();
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bool success = ue.h_ul->new_tx(msg3_slot, msg3_slot, msg3_interv, mcs, 100, max_harq_msg3_retx);
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success = ue.h_ul->new_tx(msg3_slot, msg3_slot, msg3_interv, mcs, 100, max_harq_msg3_retx);
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srsran_assert(success, "Failed to allocate Msg3");
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last_msg3 += msg3_nof_prbs;
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pdcch_ul_t msg3_pdcch; // dummy PDCCH for retx=0
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@ -8,9 +8,10 @@
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add_library(sched_nr_test_suite sched_nr_common_test.cc sched_nr_ue_ded_test_suite.cc)
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add_executable(sched_nr_test sched_nr_test.cc sched_nr_sim_ue.cc sched_nr_ue_ded_test_suite.cc)
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add_executable(sched_nr_test sched_nr_test.cc sched_nr_sim_ue.cc)
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target_link_libraries(sched_nr_test
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srsgnb_mac
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sched_nr_test_suite
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srsran_common
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${CMAKE_THREAD_LIBS_INIT}
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${Boost_LIBRARIES})
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@ -15,13 +15,27 @@
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namespace srsenb {
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void test_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs)
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void test_dl_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs)
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{
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for (const auto& pdcch : dl_pdcchs) {
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if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_ra) {
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TESTASSERT_EQ(pdcch.dci.ctx.format, srsran_dci_format_nr_1_0);
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TESTASSERT_EQ(pdcch.dci.ctx.ss_type, srsran_search_space_type_common_1);
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TESTASSERT(pdcch.dci.ctx.location.L > 0);
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} else if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_c) {
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TESTASSERT(pdcch.dci.ctx.format == srsran_dci_format_nr_1_0 or pdcch.dci.ctx.format == srsran_dci_format_nr_1_1);
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}
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}
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}
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void test_pdsch_consistency(srsran::const_span<mac_interface_phy_nr::pdsch_t> pdschs)
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{
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for (const mac_interface_phy_nr::pdsch_t& pdsch : pdschs) {
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TESTASSERT(pdsch.sch.grant.nof_layers > 0);
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if (pdsch.sch.grant.rnti_type == srsran_rnti_type_c) {
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TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx != nullptr);
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TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->buffer_b != nullptr);
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TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->max_cb > 0);
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}
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}
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}
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@ -18,8 +18,9 @@
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namespace srsenb {
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void test_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcch);
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void test_dl_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcch);
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void test_pdsch_consistency(srsran::const_span<mac_interface_phy_nr::pdsch_t> dl_pdcch);
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}
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} // namespace srsenb
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#endif // SRSRAN_SCHED_NR_COMMON_TEST_H
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@ -17,8 +17,7 @@
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#include "srsran/support/srsran_test.h"
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#include <random>
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uint32_t seed = 155556739;
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// std::chrono::system_clock::now().time_since_epoch().count();
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uint32_t seed = std::chrono::system_clock::now().time_since_epoch().count();
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namespace srsenb {
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@ -53,6 +52,7 @@ void test_single_prach()
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const bwp_slot_grid* result = nullptr;
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auto run_slot = [&alloc, &rasched, &pdcch_slot, &slot_ues, &u]() -> const bwp_slot_grid* {
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mac_logger.set_context(pdcch_slot.to_uint());
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u.carriers[0]->new_slot(pdcch_slot, u.cfg());
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slot_ues.clear();
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slot_ues.insert(rnti, u.try_reserve(pdcch_slot, 0));
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alloc.new_slot(pdcch_slot, slot_ues);
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@ -60,7 +60,7 @@ void test_single_prach()
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alloc.log_bwp_sched_result();
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const bwp_slot_grid* result = &alloc.res_grid()[alloc.get_pdcch_tti()];
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test_pdcch_consistency(result->dl_pdcchs);
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test_dl_pdcch_consistency(result->dl_pdcchs);
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++pdcch_slot;
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return result;
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};
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@ -83,6 +83,7 @@ void test_single_prach()
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// RAR is scheduled
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const uint32_t prach_duration = 1;
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slot_point rar_slot;
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while (true) {
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slot_point current_slot = pdcch_slot;
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result = run_slot();
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@ -93,11 +94,18 @@ void test_single_prach()
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TESTASSERT_EQ(pdcch.dci.ctx.rnti, ra_rnti);
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TESTASSERT_EQ(pdcch.dci.ctx.rnti_type, srsran_rnti_type_ra);
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TESTASSERT(current_slot < prach_slot + prach_duration + bwpparams.cfg.rar_window_size);
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rar_slot = current_slot;
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break;
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} else {
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TESTASSERT(result->dl_pdcchs.empty());
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}
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}
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slot_point msg3_slot = rar_slot + bwpparams.pusch_ra_list[0].msg3_delay;
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while (pdcch_slot <= msg3_slot) {
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result = run_slot();
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}
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TESTASSERT(result->puschs.size() == 1);
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}
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} // namespace srsenb
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@ -111,7 +119,7 @@ int main(int argc, char** argv)
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srsran::test_init(argc, argv);
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printf("Test seed=%u\n", seed);
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printf("Test random seed=%u\n\n", seed);
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srsenb::test_single_prach();
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}
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@ -11,6 +11,7 @@
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*/
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#include "sched_nr_sim_ue.h"
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#include "sched_nr_common_test.h"
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#include "sched_nr_ue_ded_test_suite.h"
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#include "srsran/common/test_common.h"
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@ -157,6 +158,12 @@ void sched_nr_sim_base::update(sched_nr_cc_output_res_t& cc_out)
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sim_nr_enb_ctxt_t ctxt;
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ctxt = get_enb_ctxt();
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// Run common tests
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test_dl_pdcch_consistency(cc_out.dl_cc_result->pdcch_dl);
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test_pdsch_consistency(cc_out.dl_cc_result->pdsch);
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// Run UE-dedicated tests
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test_dl_sched_result(ctxt, cc_out);
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for (auto& u : ue_db) {
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@ -22,7 +22,6 @@ void test_dl_sched_result(const sim_nr_enb_ctxt_t& enb_ctxt, const sched_nr_cc_o
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{
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slot_point pdcch_slot = cc_out.slot;
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const pdcch_dl_list_t& pdcchs = cc_out.dl_cc_result->pdcch_dl;
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const pdsch_list_t& pdschs = cc_out.dl_cc_result->pdsch;
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// Iterate over UE PDCCH allocations
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for (const pdcch_dl_t& pdcch : pdcchs) {
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@ -40,7 +39,6 @@ void test_dl_sched_result(const sim_nr_enb_ctxt_t& enb_ctxt, const sched_nr_cc_o
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TESTASSERT(ue.ue_cfg.phy_cfg.pdcch.coreset_present[pdcch.dci.ctx.coreset_id]);
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const auto& coreset = ue.ue_cfg.phy_cfg.pdcch.coreset[pdcch.dci.ctx.coreset_id];
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TESTASSERT(coreset.id == pdcch.dci.ctx.coreset_id);
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TESTASSERT(pdcch.dci.ctx.format == srsran_dci_format_nr_1_0 or pdcch.dci.ctx.format == srsran_dci_format_nr_1_1);
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// CHECK: UCI
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if (pdcch.dci.ctx.format == srsran_dci_format_nr_1_0) {
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@ -50,12 +48,6 @@ void test_dl_sched_result(const sim_nr_enb_ctxt_t& enb_ctxt, const sched_nr_cc_o
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}
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TESTASSERT(ue.cc_list[cc_out.cc].pending_acks[(pdcch_slot + k1).to_uint()] % 4 == pdcch.dci.dai);
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}
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for (const pdsch_t& pdsch : pdschs) {
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TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx != nullptr);
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TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->buffer_b != nullptr);
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TESTASSERT(pdsch.sch.grant.tb[0].softbuffer.tx->max_cb > 0);
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}
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}
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} // namespace srsenb
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