mirror of https://github.com/PentHertz/srsLTE.git
Added PDCCH DMRS interleaved mapping
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9c3dd56398
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@ -13,15 +13,18 @@
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#include "srsran/phy/ch_estimation/dmrs_pdcch.h"
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#include "srsran/phy/ch_estimation/chest_common.h"
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#include "srsran/phy/common/sequence.h"
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#include "srsran/phy/phch/pdcch_nr.h"
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#include "srsran/phy/utils/convolution.h"
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#include "srsran/phy/utils/debug.h"
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#include "srsran/phy/utils/vector.h"
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#include <complex.h>
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#include <math.h>
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#define NOF_PILOTS_X_RB 3
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/// @brief Every frequency resource is 6 Resource blocks, every resource block carries 3 pilots. So 18 possible pilots
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/// per frequency resource.
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#define NOF_PILOTS_X_FREQ_RES 18
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#define NOF_PILOTS_X_FREQ_RES (NOF_PILOTS_X_RB * 6)
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///@brief Maximum number of pilots in a PDCCH candidate location
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#define DMRS_PDCCH_MAX_NOF_PILOTS_CANDIDATE \
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@ -51,13 +54,12 @@ static uint32_t dmrs_pdcch_get_cinit(uint32_t slot_idx, uint32_t symbol_idx, uin
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2UL * n_id);
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}
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static void dmrs_pdcch_put_symbol_noninterleaved(const srsran_carrier_nr_t* carrier,
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static void dmrs_pdcch_put_symbol(const srsran_carrier_nr_t* carrier,
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const srsran_coreset_t* coreset,
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const srsran_dci_location_t* dci_location,
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const bool rb_mask[SRSRAN_MAX_PRB_NR],
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uint32_t cinit,
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cf_t* sf_symbol)
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{
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uint32_t L = 1U << dci_location->L;
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uint32_t nof_freq_res = SRSRAN_MIN(carrier->nof_prb / 6, SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE);
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// Initialise sequence for this symbol
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@ -65,67 +67,45 @@ static void dmrs_pdcch_put_symbol_noninterleaved(const srsran_carrier_nr_t* ca
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srsran_sequence_state_init(&sequence_state, cinit);
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uint32_t sequence_skip = 0; // Accumulates pilot locations to skip
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// Calculate Resource block indexes range, every CCE is 6 REG, 1 REG is 6 RE in resource blocks
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uint32_t rb_coreset_idx_begin = (dci_location->ncce * 6) / coreset->duration;
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uint32_t rb_coreset_idx_end = ((dci_location->ncce + L) * 6) / coreset->duration;
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// CORESET Resource Block counter
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uint32_t rb_coreset_idx = 0;
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for (uint32_t i = 0; i < nof_freq_res; i++) {
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// For each frequency resource (6 RB groups)
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for (uint32_t res_idx = 0; res_idx < nof_freq_res; res_idx++) {
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// Skip frequency resource if outside of the CORESET
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if (!coreset->freq_resources[i]) {
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if (!coreset->freq_resources[res_idx]) {
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// Skip possible DMRS locations in this region
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sequence_skip += NOF_PILOTS_X_FREQ_RES;
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continue;
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}
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// Skip if the frequency resource highest RB is lower than the first CCE resource block.
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if ((rb_coreset_idx + 6) <= rb_coreset_idx_begin) {
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// Skip possible DMRS locations in this region
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sequence_skip += NOF_PILOTS_X_FREQ_RES;
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// Since this is part of the CORESET, count the RB as CORESET
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rb_coreset_idx += 6;
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// For each RB in the enabled frequency resource
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for (uint32_t rb = 0; rb < 6; rb++, rb_coreset_idx++) {
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// Skip if mask is disabled
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if (!rb_mask[rb_coreset_idx]) {
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sequence_skip += NOF_PILOTS_X_RB;
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continue;
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}
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// Return if the first RB of the frequency resource is greater than the last CCE resource block
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if (rb_coreset_idx > rb_coreset_idx_end) {
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return;
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}
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// Skip all discarded possible pilot locations
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srsran_sequence_state_advance(&sequence_state, 2 * sequence_skip);
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sequence_skip = 0;
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// Generate pilots
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cf_t rl[NOF_PILOTS_X_FREQ_RES];
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srsran_sequence_state_gen_f(&sequence_state, M_SQRT1_2, (float*)rl, NOF_PILOTS_X_FREQ_RES * 2);
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// Generate pilots for the given RB
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cf_t rl[NOF_PILOTS_X_RB];
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srsran_sequence_state_gen_f(&sequence_state, M_SQRT1_2, (float*)rl, NOF_PILOTS_X_RB * 2);
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// For each RB in the frequency resource
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for (uint32_t j = 0; j < 6; j++) {
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// Calculate absolute RB index
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uint32_t n = i * 6 + j;
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// Skip if lower than begin
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if (rb_coreset_idx < rb_coreset_idx_begin) {
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rb_coreset_idx++;
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continue;
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}
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// Return if greater than end
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if (rb_coreset_idx >= rb_coreset_idx_end) {
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return;
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}
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// Absolute RB index in the resource grid
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uint32_t n = res_idx * 6 + rb;
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// Write pilots in the symbol
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for (uint32_t k_prime = 0; k_prime < 3; k_prime++) {
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// Calculate sub-carrier index
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for (uint32_t k_prime = 0; k_prime < NOF_PILOTS_X_RB; k_prime++) {
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// Calculate absolute sub-carrier index in the resource grid
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uint32_t k = n * SRSRAN_NRE + 4 * k_prime + 1;
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sf_symbol[k] = rl[3 * j + k_prime];
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// Write DMRS
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sf_symbol[k] = rl[k_prime];
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}
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rb_coreset_idx++;
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}
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}
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}
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@ -140,11 +120,6 @@ int srsran_dmrs_pdcch_put(const srsran_carrier_nr_t* carrier,
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return SRSRAN_ERROR_INVALID_INPUTS;
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}
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if (coreset->mapping_type == srsran_coreset_mapping_type_interleaved) {
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ERROR("Error interleaved CORESET mapping is not currently implemented");
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return SRSRAN_ERROR;
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}
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if (coreset->duration < SRSRAN_CORESET_DURATION_MIN || coreset->duration > SRSRAN_CORESET_DURATION_MAX) {
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ERROR("Error CORESET duration %d is out-of-bounds (%d,%d)",
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coreset->duration,
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@ -153,6 +128,13 @@ int srsran_dmrs_pdcch_put(const srsran_carrier_nr_t* carrier,
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return SRSRAN_ERROR;
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}
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// Calculate CCE-to-REG mapping mask
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bool rb_mask[SRSRAN_MAX_PRB_NR] = {};
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if (srsran_pdcch_nr_cce_to_reg_mapping(coreset, dci_location, rb_mask) < SRSRAN_SUCCESS) {
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ERROR("Error in CCE-to-REG mapping");
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return SRSRAN_SUCCESS;
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}
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// Use cell id if the DMR scrambling id is not provided by higher layers
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uint32_t n_id = carrier->pci;
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if (coreset->dmrs_scrambling_id_present) {
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@ -169,8 +151,7 @@ int srsran_dmrs_pdcch_put(const srsran_carrier_nr_t* carrier,
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DMRS_PDCCH_INFO_TX("n=%d; l=%d; cinit=%08x", slot_idx, l, cinit);
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// Put data
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dmrs_pdcch_put_symbol_noninterleaved(
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carrier, coreset, dci_location, cinit, &sf_symbols[carrier->nof_prb * SRSRAN_NRE * l]);
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dmrs_pdcch_put_symbol(carrier, coreset, rb_mask, cinit, &sf_symbols[carrier->nof_prb * SRSRAN_NRE * l]);
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}
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return SRSRAN_SUCCESS;
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@ -301,7 +282,7 @@ srsran_dmrs_pdcch_extract(srsran_dmrs_pdcch_estimator_t* q, uint32_t cinit, cons
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uint32_t sequence_skip = 0;
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// Counts enabled frequency domain resources
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uint32_t rb_coreset_idx = 0;
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uint32_t lse_count = 0;
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// Iterate over all possible frequency resources
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uint32_t freq_domain_res_size = SRSRAN_MIN(q->carrier.nof_prb / 6, SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE);
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@ -321,26 +302,23 @@ srsran_dmrs_pdcch_extract(srsran_dmrs_pdcch_estimator_t* q, uint32_t cinit, cons
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srsran_sequence_state_gen_f(&sequence_state, M_SQRT1_2, (float*)rl, NOF_PILOTS_X_FREQ_RES * 2);
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// Iterate all PRBs in the enabled frequency domain resource
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for (uint32_t j = 0, idx = rb_coreset_idx * NOF_PILOTS_X_FREQ_RES; j < 6; j++) {
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cf_t* lse_ptr = &lse[lse_count];
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for (uint32_t j = 0; j < 6; j++) {
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// Calculate Grid PRB index (n)
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uint32_t n = i * 6 + j;
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// For each pilot in the PRB
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for (uint32_t k_prime = 0; k_prime < 3; k_prime++, idx++) {
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for (uint32_t k_prime = 0; k_prime < 3; k_prime++) {
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// Calculate sub-carrier index
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uint32_t k = n * SRSRAN_NRE + 4 * k_prime + 1;
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// Extract symbol
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lse[idx] = sf_symbol[k + offset_k];
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lse[lse_count++] = sf_symbol[k + offset_k];
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}
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}
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// Calculate least squared estimates
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cf_t* lse_ptr = &lse[rb_coreset_idx * NOF_PILOTS_X_FREQ_RES];
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srsran_vec_prod_conj_ccc(lse_ptr, rl, lse_ptr, NOF_PILOTS_X_FREQ_RES);
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// Increment frequency domain resource counter
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rb_coreset_idx++;
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}
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}
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@ -424,21 +402,18 @@ int srsran_dmrs_pdcch_get_measure(const srsran_dmrs_pdcch_estimator_t* q,
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return SRSRAN_ERROR_INVALID_INPUTS;
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}
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uint32_t L = 1U << dci_location->L;
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if (q->coreset.mapping_type == srsran_coreset_mapping_type_interleaved) {
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ERROR("Error interleaved mapping not implemented");
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return SRSRAN_ERROR;
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}
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// Check that CORESET duration is not less than minimum
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if (q->coreset.duration < SRSRAN_CORESET_DURATION_MIN) {
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ERROR("Invalid CORESET duration");
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return SRSRAN_ERROR;
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}
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// Get base pilot;
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uint32_t pilot_idx = (dci_location->ncce * 18) / q->coreset.duration;
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uint32_t nof_pilots = (L * 18) / q->coreset.duration;
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// Calculate CCE-to-REG mapping mask
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bool rb_mask[SRSRAN_MAX_PRB_NR] = {};
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if (srsran_pdcch_nr_cce_to_reg_mapping(&q->coreset, dci_location, rb_mask) < SRSRAN_SUCCESS) {
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ERROR("Error in CCE-to-REG mapping");
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return SRSRAN_SUCCESS;
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}
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// Initialise measurements
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float rsrp = 0.0f; //< Averages linear RSRP
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@ -447,24 +422,36 @@ int srsran_dmrs_pdcch_get_measure(const srsran_dmrs_pdcch_estimator_t* q,
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float sync_err_avg = 0.0f; //< Averages synchronization
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cf_t corr[SRSRAN_CORESET_DURATION_MAX] = {}; //< Saves correlation for the different symbols
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// Iterate the CORESET duration
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// For each CORESET symbol
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for (uint32_t l = 0; l < q->coreset.duration; l++) {
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// Temporal least square estimates
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cf_t tmp[DMRS_PDCCH_MAX_NOF_PILOTS_CANDIDATE];
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uint32_t nof_pilots = 0;
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// For each RB in the CORESET
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for (uint32_t rb = 0; rb < q->coreset_bw; rb++) {
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// Skip RB if unused
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if (!rb_mask[rb]) {
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continue;
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}
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// Copy LSE
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srsran_vec_cf_copy(&tmp[nof_pilots], &q->lse[l][rb * NOF_PILOTS_X_RB], NOF_PILOTS_X_RB);
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nof_pilots += NOF_PILOTS_X_RB;
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}
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if (SRSRAN_DEBUG_ENABLED && srsran_verbose >= SRSRAN_VERBOSE_DEBUG && !handler_registered) {
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DMRS_PDCCH_DEBUG_RX("Measuring PDCCH l=%d; lse=", l);
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srsran_vec_fprint_c(stdout, &q->lse[l][pilot_idx], nof_pilots);
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srsran_vec_fprint_c(stdout, tmp, nof_pilots);
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}
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// Measure synchronization error and accumulate for average
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float tmp_sync_err = srsran_vec_estimate_frequency(&q->lse[l][pilot_idx], nof_pilots);
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float tmp_sync_err = srsran_vec_estimate_frequency(tmp, nof_pilots);
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sync_err_avg += tmp_sync_err;
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#if DMRS_PDCCH_SYNC_PRECOMPENSATE_MEAS
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cf_t tmp[DMRS_PDCCH_MAX_NOF_PILOTS_CANDIDATE];
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// Pre-compensate synchronization error
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srsran_vec_apply_cfo(&q->lse[l][pilot_idx], tmp_sync_err, tmp, nof_pilots);
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#else // DMRS_PDCCH_SYNC_PRECOMPENSATE_MEAS
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const cf_t* tmp = &q->lse[l][pilot_idx];
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srsran_vec_apply_cfo(tmp, tmp_sync_err, tmp, nof_pilots);
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#endif // DMRS_PDCCH_SYNC_PRECOMPENSATE_MEAS
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// Correlate DMRS
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@ -530,10 +517,6 @@ int srsran_dmrs_pdcch_get_ce(const srsran_dmrs_pdcch_estimator_t* q,
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}
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uint32_t L = 1U << dci_location->L;
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if (q->coreset.mapping_type == srsran_coreset_mapping_type_interleaved) {
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ERROR("Error interleaved mapping not implemented");
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return SRSRAN_ERROR;
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}
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// Check that CORESET duration is not less than minimum
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if (q->coreset.duration < SRSRAN_CORESET_DURATION_MIN) {
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@ -541,19 +524,33 @@ int srsran_dmrs_pdcch_get_ce(const srsran_dmrs_pdcch_estimator_t* q,
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return SRSRAN_ERROR;
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}
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// Calculate begin and end sub-carrier index for the selected candidate
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uint32_t k_begin = (dci_location->ncce * SRSRAN_NRE * 6) / q->coreset.duration;
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uint32_t k_end = k_begin + (L * 6 * SRSRAN_NRE) / q->coreset.duration;
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// Calculate CCE-to-REG mapping mask
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bool rb_mask[SRSRAN_MAX_PRB_NR] = {};
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if (srsran_pdcch_nr_cce_to_reg_mapping(&q->coreset, dci_location, rb_mask) < SRSRAN_SUCCESS) {
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ERROR("Error in CCE-to-REG mapping");
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return SRSRAN_SUCCESS;
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}
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// Extract CE for PDCCH
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uint32_t count = 0;
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// For each PDCCH symbol
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for (uint32_t l = 0; l < q->coreset.duration; l++) {
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for (uint32_t k = k_begin; k < k_end; k++) {
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// For each CORESET RB
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for (uint32_t rb = 0; rb < q->coreset_bw; rb++) {
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// Skip RB if unused
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if (!rb_mask[rb]) {
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continue;
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}
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// Copy RB, skipping DMRS
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for (uint32_t k = rb * SRSRAN_NRE; k < (rb + 1) * SRSRAN_NRE; k++) {
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if (k % 4 != 1) {
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ce->ce[count++] = q->ce[q->coreset_bw * SRSRAN_NRE * l + k];
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}
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}
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}
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}
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// Double check extracted RE match ideal count
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ce->nof_re = (SRSRAN_NRE - 3) * 6 * L;
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@ -87,7 +87,8 @@ add_nr_test(dmrs_pdsch_test dmrs_pdsch_test)
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add_executable(dmrs_pdcch_test dmrs_pdcch_test.c)
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target_link_libraries(dmrs_pdcch_test srsran_phy)
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add_nr_test(dmrs_pdcch_test dmrs_pdcch_test)
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add_nr_test(dmrs_pdcch_test_non_interleaved dmrs_pdcch_test)
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add_nr_test(dmrs_pdcch_test_interleaved dmrs_pdcch_test -I)
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########################################################################
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@ -22,23 +22,22 @@
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static srsran_carrier_nr_t carrier = {};
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static srsran_dmrs_pdcch_ce_t pdcch_ce = {};
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static uint16_t rnti = 0x1234;
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static bool interleaved = false;
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void usage(char* prog)
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{
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printf("Usage: %s [recov]\n", prog);
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printf("Usage: %s [recoIv]\n", prog);
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printf("\t-r nof_prb [Default %d]\n", carrier.nof_prb);
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printf("\t-e extended cyclic prefix [Default normal]\n");
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printf("\t-c cell_id [Default %d]\n", carrier.pci);
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printf("\t-I Enable interleaved CCE-to-REG [Default %s]\n", interleaved ? "Enabled" : "Disabled");
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printf("\t-v increase verbosity\n");
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}
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static void parse_args(int argc, char** argv)
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{
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int opt;
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while ((opt = getopt(argc, argv, "recov")) != -1) {
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while ((opt = getopt(argc, argv, "recoIv")) != -1) {
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switch (opt) {
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case 'r':
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carrier.nof_prb = (uint32_t)strtol(argv[optind], NULL, 10);
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@ -46,6 +45,9 @@ static void parse_args(int argc, char** argv)
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case 'c':
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carrier.pci = (uint32_t)strtol(argv[optind], NULL, 10);
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break;
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case 'I':
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interleaved ^= true;
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break;
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case 'v':
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srsran_verbose++;
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break;
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@ -121,6 +123,17 @@ int main(int argc, char** argv)
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parse_args(argc, argv);
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srsran_coreset_t coreset = {};
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if (interleaved) {
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coreset.mapping_type = srsran_coreset_mapping_type_interleaved;
|
||||
coreset.reg_bundle_size = srsran_coreset_bundle_size_n6;
|
||||
coreset.interleaver_size = srsran_coreset_bundle_size_n2;
|
||||
coreset.precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle;
|
||||
coreset.shift_index = carrier.pci;
|
||||
|
||||
carrier.nof_prb = 52;
|
||||
carrier.pci = 500;
|
||||
}
|
||||
|
||||
srsran_search_space_t search_space = {};
|
||||
srsran_dmrs_pdcch_estimator_t estimator = {};
|
||||
|
||||
|
@ -130,8 +143,6 @@ int main(int argc, char** argv)
|
|||
uint32_t test_counter = 0;
|
||||
uint32_t test_passed = 0;
|
||||
|
||||
coreset.mapping_type = srsran_coreset_mapping_type_non_interleaved;
|
||||
|
||||
uint32_t nof_frequency_resource = SRSRAN_MIN(SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE, carrier.nof_prb / 6);
|
||||
for (uint32_t frequency_resources = 1; frequency_resources < (1U << nof_frequency_resource); frequency_resources++) {
|
||||
uint32_t nof_freq_resources = 0;
|
||||
|
@ -141,7 +152,14 @@ int main(int argc, char** argv)
|
|||
nof_freq_resources += mask;
|
||||
}
|
||||
|
||||
for (coreset.duration = 1; coreset.duration <= 3; coreset.duration++) {
|
||||
for (coreset.duration = SRSRAN_CORESET_DURATION_MIN; coreset.duration <= SRSRAN_CORESET_DURATION_MAX;
|
||||
coreset.duration++) {
|
||||
// Skip case if CORESET bandwidth is not enough
|
||||
uint32_t N = srsran_coreset_get_bw(&coreset) * coreset.duration;
|
||||
if (interleaved && N % 12 != 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
for (search_space.type = srsran_search_space_type_common_0; search_space.type <= srsran_search_space_type_ue;
|
||||
search_space.type++) {
|
||||
for (uint32_t i = 0; i < SRSRAN_SEARCH_SPACE_NOF_AGGREGATION_LEVELS_NR; i++) {
|
||||
|
|
|
@ -11,12 +11,12 @@
|
|||
*/
|
||||
|
||||
#include "srsue/hdr/stack/rrc/rrc_nr.h"
|
||||
#include "srsran/common/band_helper.h"
|
||||
#include "srsran/common/security.h"
|
||||
#include "srsran/common/standard_streams.h"
|
||||
#include "srsran/interfaces/ue_pdcp_interfaces.h"
|
||||
#include "srsran/interfaces/ue_rlc_interfaces.h"
|
||||
#include "srsue/hdr/stack/upper/usim.h"
|
||||
#include "srsran/common/band_helper.h"
|
||||
|
||||
#define Error(fmt, ...) rrc_ptr->logger.error("Proc \"%s\" - " fmt, name(), ##__VA_ARGS__)
|
||||
#define Warning(fmt, ...) rrc_ptr->logger.warning("Proc \"%s\" - " fmt, name(), ##__VA_ARGS__)
|
||||
|
@ -31,7 +31,9 @@ namespace srsue {
|
|||
const char* rrc_nr::rrc_nr_state_text[] = {"IDLE", "CONNECTED", "CONNECTED-INACTIVE"};
|
||||
|
||||
rrc_nr::rrc_nr(srsran::task_sched_handle task_sched_) :
|
||||
logger(srslog::fetch_basic_logger("RRC-NR")), task_sched(task_sched_), conn_recfg_proc(this)
|
||||
logger(srslog::fetch_basic_logger("RRC-NR")),
|
||||
task_sched(task_sched_),
|
||||
conn_recfg_proc(this)
|
||||
{}
|
||||
|
||||
rrc_nr::~rrc_nr() = default;
|
||||
|
@ -809,9 +811,12 @@ bool rrc_nr::apply_dl_common_cfg(const asn1::rrc_nr::dl_cfg_common_s& dl_cfg_com
|
|||
|
||||
// Make CORESET Zero from provided field and given subcarrier spacing
|
||||
srsran_coreset_t coreset0 = {};
|
||||
if (srsran_coreset_zero(
|
||||
ssb_pointA_freq_offset_Hz, ssb_scs, pdcch_scs, pdcch_cfg_common.ctrl_res_set_zero, &coreset0) <
|
||||
SRSASN_SUCCESS) {
|
||||
if (srsran_coreset_zero(phy_cfg.carrier.pci,
|
||||
ssb_pointA_freq_offset_Hz,
|
||||
ssb_scs,
|
||||
pdcch_scs,
|
||||
pdcch_cfg_common.ctrl_res_set_zero,
|
||||
&coreset0) < SRSASN_SUCCESS) {
|
||||
logger.warning("Not possible to create CORESET Zero (ssb_scs=%s, pdcch_scs=%s, idx=%d)",
|
||||
srsran_subcarrier_spacing_to_str(ssb_scs),
|
||||
srsran_subcarrier_spacing_to_str(pdcch_scs),
|
||||
|
|
Loading…
Reference in New Issue