mirror of https://github.com/PentHertz/srsLTE.git
avoid forward declarations
This commit is contained in:
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08e1f01c72
commit
aab989022d
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@ -22,7 +22,7 @@
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#ifndef SRSENB_RRC_H
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#define SRSENB_RRC_H
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#include "rrc_config.h"
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#include "rrc_cell_cfg.h"
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#include "rrc_metrics.h"
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#include "srsenb/hdr/stack/upper/common_enb.h"
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#include "srslte/common/block_queue.h"
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@ -37,11 +37,6 @@
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namespace srsenb {
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class cell_info_common;
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class cell_info_common_list;
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class cell_ctxt_dedicated_list;
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class freq_res_common_list;
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static const char rrc_state_text[RRC_STATE_N_ITEMS][100] = {"IDLE",
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"WAIT FOR CON SETUP COMPLETE",
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"WAIT FOR SECURITY MODE COMPLETE",
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@ -238,7 +233,7 @@ private:
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const static uint32_t UE_PCELL_CC_IDX = 0;
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std::unique_ptr<cell_ctxt_dedicated_list> cell_ded_list;
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cell_ctxt_dedicated_list cell_ded_list;
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int get_drbid_config(asn1::rrc::drb_to_add_mod_s* drb, int drbid);
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@ -41,6 +41,7 @@ public:
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std::array<bool, N_PUCCH_MAX_RES> n_pucch_cs_used = {};
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};
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/** Storage of CQI/SR/PUCCH CS resources across multiple frequencies and for multiple users */
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class freq_res_common_list
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{
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public:
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@ -81,7 +82,7 @@ private:
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std::vector<cell_info_common> cell_list;
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};
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/** Struct to store the cell resources allocated to a user */
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/** Class used to store all the resources specific to a UE's cell */
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struct cell_ctxt_dedicated {
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uint32_t ue_cc_idx;
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const cell_info_common& cell_common;
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@ -102,6 +103,7 @@ struct cell_ctxt_dedicated {
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cell_ctxt_dedicated& operator=(const cell_ctxt_dedicated&) = delete;
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};
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/** Class used to handle the allocation of a UE's resources across its cells */
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class cell_ctxt_dedicated_list
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{
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public:
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@ -985,7 +985,7 @@ rrc::ue::ue(rrc* outer_rrc, uint16_t rnti_, const sched_interface::ue_cfg_t& sch
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pool(srslte::byte_buffer_pool::get_instance()),
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current_sched_ue_cfg(sched_ue_cfg),
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phy_rrc_dedicated_list(sched_ue_cfg.supported_cc_list.size()),
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cell_ded_list(new cell_ctxt_dedicated_list{parent->cfg, *outer_rrc->pucch_res_list, *outer_rrc->cell_common_list})
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cell_ded_list(parent->cfg, *outer_rrc->pucch_res_list, *outer_rrc->cell_common_list)
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{
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if (current_sched_ue_cfg.supported_cc_list.empty() or not current_sched_ue_cfg.supported_cc_list[0].active) {
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parent->rrc_log->warning("No PCell set. Picking eNBccIdx=0 as PCell\n");
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@ -1002,7 +1002,7 @@ rrc::ue::ue(rrc* outer_rrc, uint16_t rnti_, const sched_interface::ue_cfg_t& sch
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apply_setup_phy_common(parent->cfg.sibs[1].sib2().rr_cfg_common);
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// Allocate cell and PUCCH resources
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if (cell_ded_list->add_cell(sched_ue_cfg.supported_cc_list[0].enb_cc_idx) == nullptr) {
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if (cell_ded_list.add_cell(sched_ue_cfg.supported_cc_list[0].enb_cc_idx) == nullptr) {
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return;
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}
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}
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@ -1237,7 +1237,7 @@ void rrc::ue::handle_rrc_reconf_complete(rrc_conn_recfg_complete_s* msg, srslte:
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if (last_rrc_conn_recfg.rrc_transaction_id == msg->rrc_transaction_id) {
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// Finally, add secondary carriers to MAC
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auto& list = current_sched_ue_cfg.supported_cc_list;
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for (const auto& ue_cell : *cell_ded_list) {
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for (const auto& ue_cell : cell_ded_list) {
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uint32_t ue_cc_idx = ue_cell.ue_cc_idx;
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if (ue_cc_idx >= list.size()) {
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@ -1542,8 +1542,8 @@ void rrc::ue::send_connection_setup(bool is_setup)
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}
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phy_cfg->ant_info.explicit_value().ue_tx_ant_sel.set(setup_e::release);
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phy_cfg->sched_request_cfg.setup().sr_cfg_idx = (uint8_t)cell_ded_list->get_sr_res()->sr_I;
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phy_cfg->sched_request_cfg.setup().sr_pucch_res_idx = (uint16_t)cell_ded_list->get_sr_res()->sr_N_pucch;
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phy_cfg->sched_request_cfg.setup().sr_cfg_idx = (uint8_t)cell_ded_list.get_sr_res()->sr_I;
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phy_cfg->sched_request_cfg.setup().sr_pucch_res_idx = (uint16_t)cell_ded_list.get_sr_res()->sr_N_pucch;
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// Power control
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phy_cfg->ul_pwr_ctrl_ded_present = true;
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@ -1598,8 +1598,8 @@ void rrc::ue::send_connection_setup(bool is_setup)
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current_sched_ue_cfg.dl_cfg.cqi_report.periodic_configured = true;
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}
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current_sched_ue_cfg.dl_cfg.tm = SRSLTE_TM1;
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current_sched_ue_cfg.pucch_cfg.I_sr = cell_ded_list->get_sr_res()->sr_I;
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current_sched_ue_cfg.pucch_cfg.n_pucch_sr = cell_ded_list->get_sr_res()->sr_N_pucch;
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current_sched_ue_cfg.pucch_cfg.I_sr = cell_ded_list.get_sr_res()->sr_I;
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current_sched_ue_cfg.pucch_cfg.n_pucch_sr = cell_ded_list.get_sr_res()->sr_N_pucch;
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current_sched_ue_cfg.pucch_cfg.sr_configured = true;
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const sib_type2_s& sib2 = get_ue_cc_cfg(UE_PCELL_CC_IDX)->sib2;
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current_sched_ue_cfg.pucch_cfg.delta_pucch_shift = sib2.rr_cfg_common.pucch_cfg_common.delta_pucch_shift.to_number();
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@ -1712,7 +1712,7 @@ void rrc::ue::send_connection_reconf_upd(srslte::unique_byte_buffer_t pdu)
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phy_cfg->sched_request_cfg.setup().dsr_trans_max = parent->cfg.sr_cfg.dsr_max;
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phy_cfg->cqi_report_cfg_present = true;
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if (cell_ded_list->nof_cells() > 0) {
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if (cell_ded_list.nof_cells() > 0) {
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phy_cfg->cqi_report_cfg.cqi_report_periodic_present = true;
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phy_cfg->cqi_report_cfg.cqi_report_periodic.set_setup().cqi_format_ind_periodic.set(
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cqi_report_periodic_c::setup_s_::cqi_format_ind_periodic_c_::types::wideband_cqi);
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@ -1737,8 +1737,8 @@ void rrc::ue::send_connection_reconf_upd(srslte::unique_byte_buffer_t pdu)
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}
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apply_reconf_phy_config(reconfig_r8);
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phy_cfg->sched_request_cfg.setup().sr_cfg_idx = cell_ded_list->get_sr_res()->sr_I;
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phy_cfg->sched_request_cfg.setup().sr_cfg_idx = cell_ded_list->get_sr_res()->sr_N_pucch;
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phy_cfg->sched_request_cfg.setup().sr_cfg_idx = cell_ded_list.get_sr_res()->sr_I;
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phy_cfg->sched_request_cfg.setup().sr_cfg_idx = cell_ded_list.get_sr_res()->sr_N_pucch;
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pdu->clear();
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@ -1923,9 +1923,9 @@ int rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn_
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// Allocate CQI + PUCCH for SCells.
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for (auto scell_idx : pcell_cfg->cell_cfg.scell_list) {
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uint32_t cell_id = scell_idx.cell_id;
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cell_ded_list->add_cell(parent->cell_common_list->get_cell_id(cell_id)->enb_cc_idx);
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cell_ded_list.add_cell(parent->cell_common_list->get_cell_id(cell_id)->enb_cc_idx);
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}
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if (cell_ded_list->nof_cells() == 1) {
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if (cell_ded_list.nof_cells() == 1) {
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// No SCell could be allocated. Fallback to single cell mode.
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return SRSLTE_SUCCESS;
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}
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@ -1937,7 +1937,7 @@ int rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn_
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auto& list = conn_reconf->non_crit_ext.non_crit_ext.non_crit_ext.scell_to_add_mod_list_r10;
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// Add all SCells configured+allocated for the current PCell
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for (auto& p : *cell_ded_list) {
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for (auto& p : cell_ded_list) {
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if (p.ue_cc_idx == UE_PCELL_CC_IDX) {
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continue;
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}
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@ -2048,8 +2048,8 @@ int rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn_
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// Set DL HARQ Feedback mode
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conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.set_present(true);
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conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.get()->pucch_format_r10_present = true;
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conn_reconf->rr_cfg_ded.phys_cfg_ded.ext = true;
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conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020->pucch_format_r10_present = true;
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conn_reconf->rr_cfg_ded.phys_cfg_ded.ext = true;
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auto pucch_format_r10 = conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.get();
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pucch_format_r10->pucch_format_r10_present = true;
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auto& ch_sel_r10 = pucch_format_r10->pucch_format_r10.set_ch_sel_r10();
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@ -2058,7 +2058,7 @@ int rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn_
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n1_pucch_an_cs_r10_l item0(4);
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// TODO: should we use a different n1PUCCH-AN-CS-List configuration?
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for (auto& it : item0) {
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it = cell_ded_list->is_pucch_cs_allocated() ? *cell_ded_list->get_n_pucch_cs() : 0;
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it = cell_ded_list.is_pucch_cs_allocated() ? *cell_ded_list.get_n_pucch_cs() : 0;
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}
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ch_sel_r10.n1_pucch_an_cs_r10.setup().n1_pucch_an_cs_list_r10.push_back(item0);
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@ -2428,7 +2428,7 @@ void rrc::ue::apply_reconf_phy_config(const asn1::rrc::rrc_conn_recfg_r8_ies_s&
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int rrc::ue::get_cqi(uint16_t* pmi_idx, uint16_t* n_pucch, uint32_t ue_cc_idx)
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{
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cell_ctxt_dedicated* c = cell_ded_list->get_ue_cc_idx(ue_cc_idx);
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cell_ctxt_dedicated* c = cell_ded_list.get_ue_cc_idx(ue_cc_idx);
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if (c != nullptr and c->cqi_res_present) {
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*pmi_idx = c->cqi_res.pmi_idx;
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*n_pucch = c->cqi_res.pucch_res;
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@ -2441,7 +2441,7 @@ int rrc::ue::get_cqi(uint16_t* pmi_idx, uint16_t* n_pucch, uint32_t ue_cc_idx)
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bool rrc::ue::is_allocated() const
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{
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return cell_ded_list->is_allocated();
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return cell_ded_list.is_allocated();
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}
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int rrc::ue::get_ri(uint32_t m_ri, uint16_t* ri_idx)
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