mirror of https://github.com/PentHertz/srsLTE.git
nr,sched,refactor: clear of unused typedefs and renaming of some types
This commit is contained in:
parent
11ee4ab9dd
commit
c08bb6023c
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@ -28,11 +28,11 @@
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namespace srsenb {
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struct mac_nr_args_t {
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srsran::phy_cfg_nr_t phy_base_cfg = {};
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int fixed_dl_mcs = -1;
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int fixed_ul_mcs = -1;
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sched_nr_interface::sched_cfg_t sched_cfg = {};
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srsenb::pcap_args_t pcap;
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srsran::phy_cfg_nr_t phy_base_cfg = {};
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int fixed_dl_mcs = -1;
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int fixed_ul_mcs = -1;
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sched_nr_interface::sched_args_t sched_cfg = {};
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srsenb::pcap_args_t pcap;
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};
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class mac_nr final : public mac_interface_phy_nr, public mac_interface_rrc_nr, public mac_interface_rlc_nr
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@ -87,7 +87,7 @@ private:
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void get_metrics_nolock(srsenb::mac_metrics_t& metrics);
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// Encoding
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srsran::byte_buffer_t* assemble_rar(srsran::const_span<sched_nr_interface::sched_rar_grant_t> grants);
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srsran::byte_buffer_t* assemble_rar(srsran::const_span<sched_nr_interface::msg3_grant_t> grants);
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srsran::unique_byte_buffer_t rar_pdu_buffer = nullptr;
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// Interaction with other components
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@ -30,7 +30,6 @@ class sched_worker_manager;
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class serv_cell_manager;
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} // namespace sched_nr_impl
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class ue_event_manager;
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class ul_sched_result_buffer;
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class sched_nr final : public sched_nr_interface
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@ -38,12 +37,12 @@ class sched_nr final : public sched_nr_interface
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public:
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explicit sched_nr();
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~sched_nr() override;
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int config(const sched_cfg_t& sched_cfg, srsran::const_span<cell_cfg_t> cell_list) override;
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int config(const sched_args_t& sched_cfg, srsran::const_span<cell_cfg_t> cell_list) override;
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void ue_cfg(uint16_t rnti, const ue_cfg_t& cfg) override;
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void ue_rem(uint16_t rnti) override;
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bool ue_exists(uint16_t rnti) override;
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int dl_rach_info(uint32_t cc, const dl_sched_rar_info_t& rar_info);
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int dl_rach_info(uint32_t cc, const rar_info_t& rar_info);
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void dl_ack_info(uint16_t rnti, uint32_t cc, uint32_t pid, uint32_t tb_idx, bool ack) override;
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void ul_crc_info(uint16_t rnti, uint32_t cc, uint32_t pid, bool crc) override;
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@ -25,12 +25,12 @@ namespace sched_nr_impl {
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class si_sched
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{
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public:
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explicit si_sched(const bwp_params& bwp_cfg_);
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explicit si_sched(const bwp_params_t& bwp_cfg_);
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void run_slot(bwp_slot_allocator& slot_alloc);
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private:
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const bwp_params* bwp_cfg = nullptr;
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const bwp_params_t* bwp_cfg = nullptr;
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srslog::basic_logger& logger;
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struct sched_si_t {
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@ -45,13 +45,13 @@ private:
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srsran::bounded_vector<sched_si_t, 10> pending_sis;
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};
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using dl_sched_rar_info_t = sched_nr_interface::dl_sched_rar_info_t;
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using dl_sched_rar_info_t = sched_nr_interface::rar_info_t;
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/// RAR/Msg3 scheduler
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class ra_sched
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{
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public:
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explicit ra_sched(const bwp_params& bwp_cfg_);
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explicit ra_sched(const bwp_params_t& bwp_cfg_);
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/// Addition of detected PRACH into the queue
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int dl_rach_info(const dl_sched_rar_info_t& rar_info);
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@ -73,7 +73,7 @@ private:
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alloc_result
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allocate_pending_rar(bwp_slot_allocator& slot_grid, const pending_rar_t& rar, uint32_t& nof_grants_alloc);
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const bwp_params* bwp_cfg = nullptr;
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const bwp_params_t* bwp_cfg = nullptr;
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srslog::basic_logger& logger;
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srsran::deque<pending_rar_t> pending_rars;
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@ -82,9 +82,9 @@ private:
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class bwp_ctxt
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{
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public:
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explicit bwp_ctxt(const bwp_params& bwp_cfg);
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explicit bwp_ctxt(const bwp_params_t& bwp_cfg);
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const bwp_params* cfg;
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const bwp_params_t* cfg;
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// channel-specific schedulers
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ra_sched ra;
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@ -99,10 +99,10 @@ class serv_cell_manager
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public:
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using feedback_callback_t = srsran::move_callback<void(ue_carrier&)>;
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explicit serv_cell_manager(const sched_cell_params& cell_cfg_);
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explicit serv_cell_manager(const cell_params_t& cell_cfg_);
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srsran::bounded_vector<bwp_ctxt, SCHED_NR_MAX_BWP_PER_CELL> bwps;
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const sched_cell_params& cfg;
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const cell_params_t& cfg;
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private:
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srslog::basic_logger& logger;
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@ -26,27 +26,32 @@ static const size_t MAX_NOF_AGGR_LEVELS = 5;
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namespace sched_nr_impl {
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const static size_t MAX_GRANTS = sched_nr_interface::MAX_GRANTS;
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using pdcch_dl_t = mac_interface_phy_nr::pdcch_dl_t;
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using pdcch_ul_t = mac_interface_phy_nr::pdcch_ul_t;
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using pdsch_t = mac_interface_phy_nr::pdsch_t;
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using pusch_t = mac_interface_phy_nr::pusch_t;
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using pucch_t = mac_interface_phy_nr::pucch_t;
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using pdcch_dl_list_t = srsran::bounded_vector<pdcch_dl_t, MAX_GRANTS>;
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using pdcch_ul_list_t = srsran::bounded_vector<pdcch_ul_t, MAX_GRANTS>;
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using pucch_list_t = srsran::bounded_vector<pucch_t, MAX_GRANTS>;
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using pusch_list_t = srsran::bounded_vector<pusch_t, MAX_GRANTS>;
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using nzp_csi_rs_list = srsran::bounded_vector<srsran_csi_rs_nzp_resource_t, mac_interface_phy_nr::MAX_NZP_CSI_RS>;
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using ssb_t = mac_interface_phy_nr::ssb_t;
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using ssb_list = srsran::bounded_vector<ssb_t, mac_interface_phy_nr::MAX_SSB>;
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using sched_cfg_t = sched_nr_interface::sched_cfg_t;
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using cell_cfg_t = sched_nr_interface::cell_cfg_t;
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using bwp_cfg_t = sched_nr_interface::bwp_cfg_t;
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constexpr static size_t MAX_GRANTS = sched_nr_interface::MAX_GRANTS;
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using pdcch_dl_t = mac_interface_phy_nr::pdcch_dl_t;
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using pdcch_ul_t = mac_interface_phy_nr::pdcch_ul_t;
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using pdsch_t = mac_interface_phy_nr::pdsch_t;
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using pusch_t = mac_interface_phy_nr::pusch_t;
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using pucch_t = mac_interface_phy_nr::pucch_t;
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using pdcch_dl_list_t = srsran::bounded_vector<pdcch_dl_t, MAX_GRANTS>;
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using pdcch_ul_list_t = srsran::bounded_vector<pdcch_ul_t, MAX_GRANTS>;
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using pucch_list_t = srsran::bounded_vector<pucch_t, MAX_GRANTS>;
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using pusch_list_t = srsran::bounded_vector<pusch_t, MAX_GRANTS>;
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using nzp_csi_rs_list = srsran::bounded_vector<srsran_csi_rs_nzp_resource_t, mac_interface_phy_nr::MAX_NZP_CSI_RS>;
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using ssb_t = mac_interface_phy_nr::ssb_t;
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using ssb_list = srsran::bounded_vector<ssb_t, mac_interface_phy_nr::MAX_SSB>;
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using sched_args_t = sched_nr_interface::sched_args_t;
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using cell_cfg_t = sched_nr_interface::cell_cfg_t;
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using bwp_cfg_t = sched_nr_interface::bwp_cfg_t;
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using ue_cfg_t = sched_nr_interface::ue_cfg_t;
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using ue_cc_cfg_t = sched_nr_interface::ue_cc_cfg_t;
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using pdcch_cce_pos_list = srsran::bounded_vector<uint32_t, SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR>;
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using bwp_cce_pos_list = std::array<std::array<pdcch_cce_pos_list, MAX_NOF_AGGR_LEVELS>, SRSRAN_NOF_SF_X_FRAME>;
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using dl_sched_t = sched_nr_interface::dl_sched_t;
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using ul_sched_t = sched_nr_interface::ul_sched_t;
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using dl_sched_res_t = sched_nr_interface::dl_sched_res_t;
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/// Generate list of CCE locations for UE based on coreset and search space configurations
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void get_dci_locs(const srsran_coreset_t& coreset,
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const srsran_search_space_t& search_space,
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uint16_t rnti,
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@ -54,18 +59,22 @@ void get_dci_locs(const srsran_coreset_t& coreset,
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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struct bwp_params {
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const uint32_t bwp_id;
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const uint32_t cc;
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const bwp_cfg_t& cfg;
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const cell_cfg_t& cell_cfg;
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const sched_cfg_t& sched_cfg;
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/// Structure that extends the sched_nr_interface::bwp_cfg_t passed by upper layers with other
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/// derived BWP-specific params
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struct bwp_params_t {
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const uint32_t bwp_id;
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const uint32_t cc;
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const bwp_cfg_t& cfg;
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const cell_cfg_t& cell_cfg;
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const sched_args_t& sched_cfg;
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// derived params
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srslog::basic_logger& logger;
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uint32_t P;
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uint32_t N_rbg;
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uint32_t nof_prb() const { return cell_cfg.carrier.nof_prb; }
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/// Table specifying if a slot has DL or UL enabled
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struct slot_cfg {
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bool is_dl;
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bool is_ul;
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@ -82,48 +91,42 @@ struct bwp_params {
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bwp_cce_pos_list rar_cce_list;
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bwp_params(const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_, uint32_t cc, uint32_t bwp_id);
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bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg_, uint32_t cc, uint32_t bwp_id);
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};
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struct sched_cell_params {
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const uint32_t cc;
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const cell_cfg_t cell_cfg;
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const sched_cfg_t& sched_cfg;
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std::vector<bwp_params> bwps;
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/// Structure packing a single cell config params, and sched args
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struct cell_params_t {
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const uint32_t cc;
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const cell_cfg_t cfg;
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const sched_args_t& sched_args;
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std::vector<bwp_params_t> bwps;
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sched_cell_params(uint32_t cc_, const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_);
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cell_params_t(uint32_t cc_, const cell_cfg_t& cell, const sched_args_t& sched_cfg_);
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uint32_t nof_prb() const { return cell_cfg.carrier.nof_prb; }
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uint32_t nof_prb() const { return cfg.carrier.nof_prb; }
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};
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/// Structure packing both the sched args and all gNB NR cell configurations
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struct sched_params {
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sched_cfg_t sched_cfg;
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std::vector<sched_cell_params> cells;
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sched_args_t sched_cfg;
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std::vector<cell_params_t> cells;
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sched_params() = default;
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explicit sched_params(const sched_cfg_t& sched_cfg_);
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explicit sched_params(const sched_args_t& sched_cfg_);
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};
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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using prb_bitmap = srsran::bounded_bitset<SRSRAN_MAX_PRB_NR, true>;
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using pdcchmask_t = srsran::bounded_bitset<SCHED_NR_MAX_NOF_RBGS, true>;
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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using ue_cfg_t = sched_nr_interface::ue_cfg_t;
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using ue_cc_cfg_t = sched_nr_interface::ue_cc_cfg_t;
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/// Configuration of a UE for a given BWP
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class bwp_ue_cfg
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{
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public:
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bwp_ue_cfg() = default;
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explicit bwp_ue_cfg(uint16_t rnti, const bwp_params& bwp_cfg, const ue_cfg_t& uecfg_);
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explicit bwp_ue_cfg(uint16_t rnti, const bwp_params_t& bwp_cfg, const ue_cfg_t& uecfg_);
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const ue_cfg_t* ue_cfg() const { return cfg_; }
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const srsran::phy_cfg_nr_t& phy() const { return cfg_->phy_cfg; }
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const bwp_params& active_bwp() const { return *bwp_cfg; }
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const bwp_params_t& active_bwp() const { return *bwp_cfg; }
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const bwp_cce_pos_list& cce_pos_list(uint32_t search_id) const
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{
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return cce_positions_list[ss_id_to_cce_idx[search_id]];
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}
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private:
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uint16_t rnti = SRSRAN_INVALID_RNTI;
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const ue_cfg_t* cfg_ = nullptr;
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const bwp_params* bwp_cfg = nullptr;
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uint16_t rnti = SRSRAN_INVALID_RNTI;
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const ue_cfg_t* cfg_ = nullptr;
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const bwp_params_t* bwp_cfg = nullptr;
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std::vector<bwp_cce_pos_list> cce_positions_list;
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std::array<uint32_t, SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE> ss_id_to_cce_idx;
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@ -24,7 +24,7 @@ namespace srsenb {
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namespace sched_nr_impl {
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// typedefs
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using dl_sched_rar_info_t = sched_nr_interface::dl_sched_rar_info_t;
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using dl_sched_rar_info_t = sched_nr_interface::rar_info_t;
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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/// save data for scheduler to keep track of previous allocations
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/// This only contains information about a given slot
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struct bwp_slot_grid {
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uint32_t slot_idx = 0;
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const bwp_params* cfg = nullptr;
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uint32_t slot_idx = 0;
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const bwp_params_t* cfg = nullptr;
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bwp_rb_bitmap dl_prbs;
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bwp_rb_bitmap ul_prbs;
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srsran::unique_pool_ptr<tx_harq_softbuffer> rar_softbuffer;
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bwp_slot_grid() = default;
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explicit bwp_slot_grid(const bwp_params& bwp_params, uint32_t slot_idx_);
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explicit bwp_slot_grid(const bwp_params_t& bwp_params, uint32_t slot_idx_);
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void reset();
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bool is_dl() const { return cfg->slots[slot_idx].is_dl; }
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};
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struct bwp_res_grid {
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explicit bwp_res_grid(const bwp_params& bwp_cfg_);
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explicit bwp_res_grid(const bwp_params_t& bwp_cfg_);
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bwp_slot_grid& operator[](slot_point tti) { return slots[tti.to_uint() % slots.capacity()]; };
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const bwp_slot_grid& operator[](slot_point tti) const { return slots[tti.to_uint() % slots.capacity()]; };
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uint32_t id() const { return cfg->bwp_id; }
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uint32_t nof_prbs() const { return cfg->cfg.rb_width; }
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const bwp_params* cfg = nullptr;
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const bwp_params_t* cfg = nullptr;
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private:
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// TTIMOD_SZ is the longest allocation in the future
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slot_point get_tti_rx() const { return pdcch_slot - TX_ENB_DELAY; }
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const bwp_res_grid& res_grid() const { return bwp_grid; }
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const bwp_params& cfg;
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const bwp_params_t& cfg;
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private:
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alloc_result verify_pdsch_space(bwp_slot_grid& pdsch_grid, bwp_slot_grid& pdcch_grid) const;
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params& bwp_cfg, srsran_dci_dl_nr_t& dci);
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bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params& bwp_cfg, srsran_dci_ul_nr_t& dci);
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul_nr_t& dci);
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/// Generate PDCCH DL DCI fields
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void fill_dl_dci_ue_fields(const slot_ue& ue,
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const bwp_params& bwp_cfg,
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const bwp_params_t& bwp_cfg,
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uint32_t ss_id,
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srsran_dci_location_t dci_pos,
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srsran_dci_dl_nr_t& dci);
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/// Generate PDCCH UL DCI fields
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void fill_ul_dci_ue_fields(const slot_ue& ue,
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const bwp_params& bwp_cfg,
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const bwp_params_t& bwp_cfg,
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uint32_t ss_id,
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srsran_dci_location_t dci_pos,
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srsran_dci_ul_nr_t& dci);
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@ -67,7 +67,7 @@ public:
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srsran::bounded_vector<bwp_cfg_t, SCHED_NR_MAX_BWP_PER_CELL> bwps{1}; // idx0 for BWP-common
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};
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struct sched_cfg_t {
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struct sched_args_t {
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bool pdsch_enabled = true;
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bool pusch_enabled = true;
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bool auto_refill_buffer = false;
|
||||
|
@ -88,9 +88,9 @@ public:
|
|||
srsran::phy_cfg_nr_t phy_cfg = {};
|
||||
};
|
||||
|
||||
////// RACH //////
|
||||
////// RA procedure //////
|
||||
|
||||
struct dl_sched_rar_info_t {
|
||||
struct rar_info_t {
|
||||
uint32_t preamble_idx; // is this the RAPID?
|
||||
uint32_t ofdm_symbol_idx;
|
||||
uint32_t freq_idx;
|
||||
|
@ -99,32 +99,32 @@ public:
|
|||
uint32_t msg3_size = 7;
|
||||
slot_point prach_slot;
|
||||
};
|
||||
struct msg3_grant_t {
|
||||
rar_info_t data;
|
||||
srsran_dci_ul_nr_t msg3_dci = {};
|
||||
};
|
||||
struct rar_t {
|
||||
srsran::bounded_vector<msg3_grant_t, MAX_GRANTS> grants;
|
||||
};
|
||||
|
||||
///// Sched Result /////
|
||||
|
||||
using dl_sched_t = mac_interface_phy_nr::dl_sched_t;
|
||||
using ul_sched_t = mac_interface_phy_nr::ul_sched_t;
|
||||
|
||||
struct sched_rar_grant_t {
|
||||
dl_sched_rar_info_t data;
|
||||
srsran_dci_ul_nr_t msg3_dci = {};
|
||||
};
|
||||
struct sched_rar_t {
|
||||
srsran::bounded_vector<sched_rar_grant_t, MAX_GRANTS> grants;
|
||||
};
|
||||
using sched_rar_list_t = srsran::bounded_vector<sched_rar_t, MAX_GRANTS>;
|
||||
using sched_rar_list_t = srsran::bounded_vector<rar_t, MAX_GRANTS>;
|
||||
struct dl_sched_res_t {
|
||||
sched_rar_list_t rar;
|
||||
dl_sched_t dl_sched;
|
||||
};
|
||||
|
||||
virtual ~sched_nr_interface() = default;
|
||||
virtual int config(const sched_cfg_t& sched_cfg, srsran::const_span<sched_nr_interface::cell_cfg_t> ue_cfg) = 0;
|
||||
virtual void ue_cfg(uint16_t rnti, const ue_cfg_t& ue_cfg) = 0;
|
||||
virtual void ue_rem(uint16_t rnti) = 0;
|
||||
virtual bool ue_exists(uint16_t rnti) = 0;
|
||||
virtual int run_slot(slot_point slot_rx, uint32_t cc, dl_sched_res_t& result) = 0;
|
||||
virtual int get_ul_sched(slot_point slot_rx, uint32_t cc, ul_sched_t& result) = 0;
|
||||
virtual int config(const sched_args_t& sched_cfg, srsran::const_span<sched_nr_interface::cell_cfg_t> ue_cfg) = 0;
|
||||
virtual void ue_cfg(uint16_t rnti, const ue_cfg_t& ue_cfg) = 0;
|
||||
virtual void ue_rem(uint16_t rnti) = 0;
|
||||
virtual bool ue_exists(uint16_t rnti) = 0;
|
||||
virtual int run_slot(slot_point slot_rx, uint32_t cc, dl_sched_res_t& result) = 0;
|
||||
virtual int get_ul_sched(slot_point slot_rx, uint32_t cc, ul_sched_t& result) = 0;
|
||||
|
||||
virtual void dl_ack_info(uint16_t rnti, uint32_t cc, uint32_t pid, uint32_t tb_idx, bool ack) = 0;
|
||||
virtual void ul_crc_info(uint16_t rnti, uint32_t cc, uint32_t pid, bool crc) = 0;
|
||||
|
|
|
@ -34,11 +34,11 @@ using bwp_cfg_t = sched_nr_interface::bwp_cfg_t;
|
|||
class coreset_region
|
||||
{
|
||||
public:
|
||||
coreset_region(const bwp_params& bwp_cfg_,
|
||||
uint32_t coreset_id_,
|
||||
uint32_t slot_idx,
|
||||
pdcch_dl_list_t& pdcch_dl_list,
|
||||
pdcch_ul_list_t& pdcch_ul_list);
|
||||
coreset_region(const bwp_params_t& bwp_cfg_,
|
||||
uint32_t coreset_id_,
|
||||
uint32_t slot_idx,
|
||||
pdcch_dl_list_t& pdcch_dl_list,
|
||||
pdcch_ul_list_t& pdcch_ul_list);
|
||||
void reset();
|
||||
|
||||
/**
|
||||
|
|
|
@ -42,10 +42,10 @@ void sched_nzp_csi_rs(srsran::const_span<srsran_csi_rs_nzp_set_t> nzp_csi_rs_set
|
|||
void sched_ssb_basic(const slot_point& sl_point, uint32_t ssb_periodicity, ssb_list& ssb_list);
|
||||
|
||||
/// For a given BWP and slot, schedule SSB, NZP CSI RS and SIBs
|
||||
void sched_dl_signalling(const bwp_params& bwp_params,
|
||||
slot_point sl_pdcch,
|
||||
ssb_list& ssb_list,
|
||||
nzp_csi_rs_list& nzp_csi_rs);
|
||||
void sched_dl_signalling(const bwp_params_t& bwp_params,
|
||||
slot_point sl_pdcch,
|
||||
ssb_list& ssb_list,
|
||||
nzp_csi_rs_list& nzp_csi_rs);
|
||||
|
||||
} // namespace sched_nr_impl
|
||||
} // namespace srsenb
|
||||
|
|
|
@ -62,7 +62,7 @@ public:
|
|||
class ue_carrier
|
||||
{
|
||||
public:
|
||||
ue_carrier(uint16_t rnti, const ue_cfg_t& cfg, const sched_cell_params& cell_params_);
|
||||
ue_carrier(uint16_t rnti, const ue_cfg_t& cfg, const cell_params_t& cell_params_);
|
||||
slot_ue try_reserve(slot_point pdcch_slot, const ue_cfg_t& uecfg_, uint32_t dl_harq_bytes, uint32_t ul_harq_bytes);
|
||||
|
||||
const uint16_t rnti;
|
||||
|
@ -78,8 +78,8 @@ public:
|
|||
mac_ue_metrics_t metrics = {};
|
||||
|
||||
private:
|
||||
bwp_ue_cfg bwp_cfg;
|
||||
const sched_cell_params& cell_params;
|
||||
bwp_ue_cfg bwp_cfg;
|
||||
const cell_params_t& cell_params;
|
||||
};
|
||||
|
||||
class ue
|
||||
|
|
|
@ -30,10 +30,6 @@ struct mac_metrics_t;
|
|||
|
||||
namespace sched_nr_impl {
|
||||
|
||||
using dl_sched_t = sched_nr_interface::dl_sched_t;
|
||||
using ul_sched_t = sched_nr_interface::ul_sched_t;
|
||||
using dl_sched_res_t = sched_nr_interface::dl_sched_res_t;
|
||||
|
||||
class slot_cc_worker
|
||||
{
|
||||
public:
|
||||
|
@ -57,9 +53,9 @@ private:
|
|||
void alloc_ul_ues();
|
||||
void postprocess_decisions();
|
||||
|
||||
const sched_cell_params& cfg;
|
||||
serv_cell_manager& cell;
|
||||
srslog::basic_logger& logger;
|
||||
const cell_params_t& cfg;
|
||||
serv_cell_manager& cell;
|
||||
srslog::basic_logger& logger;
|
||||
|
||||
slot_point slot_rx;
|
||||
bwp_slot_allocator bwp_alloc;
|
||||
|
|
|
@ -165,11 +165,11 @@ void mac_nr::rach_detected(const rach_info_t& rach_info)
|
|||
++detected_rachs[enb_cc_idx];
|
||||
|
||||
// Trigger scheduler RACH
|
||||
srsenb::sched_nr_interface::dl_sched_rar_info_t rar_info = {};
|
||||
rar_info.preamble_idx = rach_info.preamble;
|
||||
rar_info.temp_crnti = rnti;
|
||||
rar_info.ta_cmd = rach_info.time_adv;
|
||||
rar_info.prach_slot = slot_point{NUMEROLOGY_IDX, rach_info.slot_index};
|
||||
srsenb::sched_nr_interface::rar_info_t rar_info = {};
|
||||
rar_info.preamble_idx = rach_info.preamble;
|
||||
rar_info.temp_crnti = rnti;
|
||||
rar_info.ta_cmd = rach_info.time_adv;
|
||||
rar_info.prach_slot = slot_point{NUMEROLOGY_IDX, rach_info.slot_index};
|
||||
// TODO: fill remaining fields as required
|
||||
sched.dl_rach_info(enb_cc_idx, rar_info);
|
||||
rrc->add_user(rnti);
|
||||
|
@ -312,7 +312,7 @@ int mac_nr::get_dl_sched(const srsran_slot_cfg_t& slot_cfg, dl_sched_t& dl_sched
|
|||
}
|
||||
}
|
||||
} else if (pdsch.sch.grant.rnti_type == srsran_rnti_type_ra) {
|
||||
sched_nr_interface::sched_rar_t& rar = dl_res.rar[rar_count++];
|
||||
sched_nr_interface::rar_t& rar = dl_res.rar[rar_count++];
|
||||
// for RARs we could actually move the byte_buffer to the PHY, as there are no retx
|
||||
pdsch.data[0] = assemble_rar(rar.grants);
|
||||
}
|
||||
|
@ -372,6 +372,7 @@ int mac_nr::pusch_info(const srsran_slot_cfg_t& slot_cfg, mac_interface_phy_nr::
|
|||
{
|
||||
uint16_t rnti = pusch_info.rnti;
|
||||
uint32_t nof_bytes = pusch_info.pdu->N_bytes;
|
||||
|
||||
// Handle UCI data
|
||||
if (not handle_uci_data(rnti, pusch_info.uci_cfg, pusch_info.pusch_data.uci)) {
|
||||
logger.error("Error handling UCI data from PUCCH reception");
|
||||
|
@ -405,7 +406,7 @@ int mac_nr::pusch_info(const srsran_slot_cfg_t& slot_cfg, mac_interface_phy_nr::
|
|||
return SRSRAN_SUCCESS;
|
||||
}
|
||||
|
||||
srsran::byte_buffer_t* mac_nr::assemble_rar(srsran::const_span<sched_nr_interface::sched_rar_grant_t> grants)
|
||||
srsran::byte_buffer_t* mac_nr::assemble_rar(srsran::const_span<sched_nr_interface::msg3_grant_t> grants)
|
||||
{
|
||||
srsran::mac_rar_pdu_nr rar_pdu;
|
||||
|
||||
|
|
|
@ -70,7 +70,7 @@ sched_nr::sched_nr() : logger(&srslog::fetch_basic_logger("MAC-NR")) {}
|
|||
|
||||
sched_nr::~sched_nr() {}
|
||||
|
||||
int sched_nr::config(const sched_cfg_t& sched_cfg, srsran::const_span<cell_cfg_t> cell_list)
|
||||
int sched_nr::config(const sched_args_t& sched_cfg, srsran::const_span<cell_cfg_t> cell_list)
|
||||
{
|
||||
cfg = sched_params{sched_cfg};
|
||||
logger = &srslog::fetch_basic_logger(sched_cfg.logger_name);
|
||||
|
@ -153,7 +153,7 @@ void sched_nr::get_metrics(mac_metrics_t& metrics)
|
|||
sched_workers->get_metrics(metrics);
|
||||
}
|
||||
|
||||
int sched_nr::dl_rach_info(uint32_t cc, const dl_sched_rar_info_t& rar_info)
|
||||
int sched_nr::dl_rach_info(uint32_t cc, const rar_info_t& rar_info)
|
||||
{
|
||||
sched_workers->enqueue_cc_event(cc, [this, cc, rar_info]() { cells[cc]->bwps[0].ra.dl_rach_info(rar_info); });
|
||||
return SRSRAN_SUCCESS;
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
namespace srsenb {
|
||||
namespace sched_nr_impl {
|
||||
|
||||
si_sched::si_sched(const bwp_params& bwp_cfg_) :
|
||||
si_sched::si_sched(const bwp_params_t& bwp_cfg_) :
|
||||
bwp_cfg(&bwp_cfg_), logger(srslog::fetch_basic_logger(bwp_cfg_.sched_cfg.logger_name))
|
||||
{}
|
||||
|
||||
|
@ -77,7 +77,7 @@ void si_sched::run_slot(bwp_slot_allocator& slot_alloc)
|
|||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
ra_sched::ra_sched(const bwp_params& bwp_cfg_) :
|
||||
ra_sched::ra_sched(const bwp_params_t& bwp_cfg_) :
|
||||
bwp_cfg(&bwp_cfg_), logger(srslog::fetch_basic_logger(bwp_cfg_.sched_cfg.logger_name))
|
||||
{}
|
||||
|
||||
|
@ -220,16 +220,16 @@ int ra_sched::dl_rach_info(const dl_sched_rar_info_t& rar_info)
|
|||
return SRSRAN_SUCCESS;
|
||||
}
|
||||
|
||||
bwp_ctxt::bwp_ctxt(const bwp_params& bwp_cfg) :
|
||||
bwp_ctxt::bwp_ctxt(const bwp_params_t& bwp_cfg) :
|
||||
cfg(&bwp_cfg), ra(bwp_cfg), grid(bwp_cfg), data_sched(new sched_nr_time_rr())
|
||||
{}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
serv_cell_manager::serv_cell_manager(const sched_cell_params& cell_cfg_) :
|
||||
cfg(cell_cfg_), logger(srslog::fetch_basic_logger(cell_cfg_.sched_cfg.logger_name))
|
||||
serv_cell_manager::serv_cell_manager(const cell_params_t& cell_cfg_) :
|
||||
cfg(cell_cfg_), logger(srslog::fetch_basic_logger(cell_cfg_.sched_args.logger_name))
|
||||
{
|
||||
for (uint32_t bwp_id = 0; bwp_id < cfg.cell_cfg.bwps.size(); ++bwp_id) {
|
||||
for (uint32_t bwp_id = 0; bwp_id < cfg.cfg.bwps.size(); ++bwp_id) {
|
||||
bwps.emplace_back(cell_cfg_.bwps[bwp_id]);
|
||||
}
|
||||
|
||||
|
|
|
@ -20,7 +20,25 @@ extern "C" {
|
|||
namespace srsenb {
|
||||
namespace sched_nr_impl {
|
||||
|
||||
bwp_params::bwp_params(const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_, uint32_t cc_, uint32_t bwp_id_) :
|
||||
void get_dci_locs(const srsran_coreset_t& coreset,
|
||||
const srsran_search_space_t& search_space,
|
||||
uint16_t rnti,
|
||||
bwp_cce_pos_list& cce_locs)
|
||||
{
|
||||
for (uint32_t sl = 0; sl < SRSRAN_NOF_SF_X_FRAME; ++sl) {
|
||||
for (uint32_t agg_idx = 0; agg_idx < MAX_NOF_AGGR_LEVELS; ++agg_idx) {
|
||||
pdcch_cce_pos_list pdcch_locs;
|
||||
cce_locs[sl][agg_idx].resize(pdcch_locs.capacity());
|
||||
uint32_t n =
|
||||
srsran_pdcch_nr_locations_coreset(&coreset, &search_space, rnti, agg_idx, sl, cce_locs[sl][agg_idx].data());
|
||||
cce_locs[sl][agg_idx].resize(n);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
bwp_params_t::bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg_, uint32_t cc_, uint32_t bwp_id_) :
|
||||
cell_cfg(cell),
|
||||
sched_cfg(sched_cfg_),
|
||||
cc(cc_),
|
||||
|
@ -73,39 +91,21 @@ bwp_params::bwp_params(const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_, ui
|
|||
}
|
||||
}
|
||||
|
||||
sched_cell_params::sched_cell_params(uint32_t cc_, const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_) :
|
||||
cc(cc_), cell_cfg(cell), sched_cfg(sched_cfg_)
|
||||
cell_params_t::cell_params_t(uint32_t cc_, const cell_cfg_t& cell, const sched_args_t& sched_cfg_) :
|
||||
cc(cc_), cfg(cell), sched_args(sched_cfg_)
|
||||
{
|
||||
bwps.reserve(cell.bwps.size());
|
||||
for (uint32_t i = 0; i < cell_cfg.bwps.size(); ++i) {
|
||||
bwps.emplace_back(cell_cfg, sched_cfg_, cc, i);
|
||||
for (uint32_t i = 0; i < cfg.bwps.size(); ++i) {
|
||||
bwps.emplace_back(cfg, sched_cfg_, cc, i);
|
||||
}
|
||||
srsran_assert(not bwps.empty(), "No BWPs were configured");
|
||||
}
|
||||
|
||||
sched_params::sched_params(const sched_cfg_t& sched_cfg_) : sched_cfg(sched_cfg_) {}
|
||||
sched_params::sched_params(const sched_args_t& sched_cfg_) : sched_cfg(sched_cfg_) {}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void get_dci_locs(const srsran_coreset_t& coreset,
|
||||
const srsran_search_space_t& search_space,
|
||||
uint16_t rnti,
|
||||
bwp_cce_pos_list& cce_locs)
|
||||
{
|
||||
for (uint32_t sl = 0; sl < SRSRAN_NOF_SF_X_FRAME; ++sl) {
|
||||
for (uint32_t agg_idx = 0; agg_idx < MAX_NOF_AGGR_LEVELS; ++agg_idx) {
|
||||
pdcch_cce_pos_list pdcch_locs;
|
||||
cce_locs[sl][agg_idx].resize(pdcch_locs.capacity());
|
||||
uint32_t n =
|
||||
srsran_pdcch_nr_locations_coreset(&coreset, &search_space, rnti, agg_idx, sl, cce_locs[sl][agg_idx].data());
|
||||
cce_locs[sl][agg_idx].resize(n);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
bwp_ue_cfg::bwp_ue_cfg(uint16_t rnti_, const bwp_params& bwp_cfg_, const ue_cfg_t& uecfg_) :
|
||||
bwp_ue_cfg::bwp_ue_cfg(uint16_t rnti_, const bwp_params_t& bwp_cfg_, const ue_cfg_t& uecfg_) :
|
||||
rnti(rnti_), cfg_(&uecfg_), bwp_cfg(&bwp_cfg_)
|
||||
{
|
||||
std::fill(ss_id_to_cce_idx.begin(), ss_id_to_cce_idx.end(), SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE);
|
||||
|
|
|
@ -17,7 +17,7 @@
|
|||
namespace srsenb {
|
||||
namespace sched_nr_impl {
|
||||
|
||||
bwp_slot_grid::bwp_slot_grid(const bwp_params& bwp_cfg_, uint32_t slot_idx_) :
|
||||
bwp_slot_grid::bwp_slot_grid(const bwp_params_t& bwp_cfg_, uint32_t slot_idx_) :
|
||||
dl_prbs(bwp_cfg_.cfg.rb_width, bwp_cfg_.cfg.start_rb, bwp_cfg_.cfg.pdsch.rbg_size_cfg_1),
|
||||
ul_prbs(bwp_cfg_.cfg.rb_width, bwp_cfg_.cfg.start_rb, bwp_cfg_.cfg.pdsch.rbg_size_cfg_1),
|
||||
slot_idx(slot_idx_),
|
||||
|
@ -52,7 +52,7 @@ void bwp_slot_grid::reset()
|
|||
rar.clear();
|
||||
}
|
||||
|
||||
bwp_res_grid::bwp_res_grid(const bwp_params& bwp_cfg_) : cfg(&bwp_cfg_)
|
||||
bwp_res_grid::bwp_res_grid(const bwp_params_t& bwp_cfg_) : cfg(&bwp_cfg_)
|
||||
{
|
||||
for (uint32_t sl = 0; sl < slots.capacity(); ++sl) {
|
||||
slots.emplace_back(*cfg, sl % static_cast<uint32_t>(SRSRAN_NSLOTS_PER_FRAME_NR(0u)));
|
||||
|
@ -161,7 +161,7 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
|
|||
const int mcs = 0, max_harq_msg3_retx = 4;
|
||||
slot_cfg.idx = msg3_slot.to_uint();
|
||||
bwp_pdcch_slot.rar.emplace_back();
|
||||
sched_nr_interface::sched_rar_t& rar_out = bwp_pdcch_slot.rar.back();
|
||||
sched_nr_interface::rar_t& rar_out = bwp_pdcch_slot.rar.back();
|
||||
for (const dl_sched_rar_info_t& grant : pending_rars) {
|
||||
slot_ue& ue = (*slot_ues)[grant.temp_crnti];
|
||||
|
||||
|
|
|
@ -22,7 +22,7 @@ namespace sched_nr_impl {
|
|||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
template <typename DciDlOrUl>
|
||||
void fill_dci_common(const slot_ue& ue, const bwp_params& bwp_cfg, DciDlOrUl& dci)
|
||||
void fill_dci_common(const slot_ue& ue, const bwp_params_t& bwp_cfg, DciDlOrUl& dci)
|
||||
{
|
||||
const static uint32_t rv_idx[4] = {0, 2, 3, 1};
|
||||
|
||||
|
@ -47,7 +47,7 @@ void fill_dci_common(const slot_ue& ue, const bwp_params& bwp_cfg, DciDlOrUl& dc
|
|||
dci.time_domain_assigment = 0;
|
||||
}
|
||||
|
||||
bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params& bwp_cfg, srsran_dci_dl_nr_t& dci)
|
||||
bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci)
|
||||
{
|
||||
dci.mcs = 5;
|
||||
dci.ctx.format = srsran_dci_format_nr_1_0;
|
||||
|
@ -65,7 +65,7 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params& bwp_c
|
|||
return true;
|
||||
}
|
||||
|
||||
bool fill_dci_msg3(const slot_ue& ue, const bwp_params& bwp_cfg, srsran_dci_ul_nr_t& msg3_dci)
|
||||
bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul_nr_t& msg3_dci)
|
||||
{
|
||||
fill_dci_common(ue, bwp_cfg, msg3_dci);
|
||||
msg3_dci.ctx.coreset_id = ue.cfg->phy().pdcch.ra_search_space.coreset_id;
|
||||
|
@ -82,7 +82,7 @@ bool fill_dci_msg3(const slot_ue& ue, const bwp_params& bwp_cfg, srsran_dci_ul_n
|
|||
}
|
||||
|
||||
void fill_dl_dci_ue_fields(const slot_ue& ue,
|
||||
const bwp_params& bwp_cfg,
|
||||
const bwp_params_t& bwp_cfg,
|
||||
uint32_t ss_id,
|
||||
srsran_dci_location_t dci_pos,
|
||||
srsran_dci_dl_nr_t& dci)
|
||||
|
@ -101,7 +101,7 @@ void fill_dl_dci_ue_fields(const slot_ue& ue,
|
|||
}
|
||||
|
||||
void fill_ul_dci_ue_fields(const slot_ue& ue,
|
||||
const bwp_params& bwp_cfg,
|
||||
const bwp_params_t& bwp_cfg,
|
||||
uint32_t ss_id,
|
||||
srsran_dci_location_t dci_pos,
|
||||
srsran_dci_ul_nr_t& dci)
|
||||
|
|
|
@ -16,11 +16,11 @@
|
|||
namespace srsenb {
|
||||
namespace sched_nr_impl {
|
||||
|
||||
coreset_region::coreset_region(const bwp_params& bwp_cfg_,
|
||||
uint32_t coreset_id_,
|
||||
uint32_t slot_idx_,
|
||||
pdcch_dl_list_t& dl_list_,
|
||||
pdcch_ul_list_t& ul_list_) :
|
||||
coreset_region::coreset_region(const bwp_params_t& bwp_cfg_,
|
||||
uint32_t coreset_id_,
|
||||
uint32_t slot_idx_,
|
||||
pdcch_dl_list_t& dl_list_,
|
||||
pdcch_ul_list_t& ul_list_) :
|
||||
coreset_cfg(&bwp_cfg_.cfg.pdcch.coreset[coreset_id_]),
|
||||
coreset_id(coreset_id_),
|
||||
slot_idx(slot_idx_),
|
||||
|
|
|
@ -75,10 +75,10 @@ void sched_ssb_basic(const slot_point& sl_point, uint32_t ssb_periodicity, ssb_l
|
|||
}
|
||||
}
|
||||
|
||||
void sched_dl_signalling(const bwp_params& bwp_params,
|
||||
slot_point sl_pdcch,
|
||||
ssb_list& ssb_list,
|
||||
nzp_csi_rs_list& nzp_csi_rs)
|
||||
void sched_dl_signalling(const bwp_params_t& bwp_params,
|
||||
slot_point sl_pdcch,
|
||||
ssb_list& ssb_list,
|
||||
nzp_csi_rs_list& nzp_csi_rs)
|
||||
{
|
||||
srsran_slot_cfg_t cfg;
|
||||
cfg.idx = sl_pdcch.to_uint();
|
||||
|
|
|
@ -21,7 +21,7 @@ slot_ue::slot_ue(uint16_t rnti_, slot_point slot_rx_, uint32_t cc_) : rnti(rnti_
|
|||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
ue_carrier::ue_carrier(uint16_t rnti_, const ue_cfg_t& uecfg_, const sched_cell_params& cell_params_) :
|
||||
ue_carrier::ue_carrier(uint16_t rnti_, const ue_cfg_t& uecfg_, const cell_params_t& cell_params_) :
|
||||
rnti(rnti_),
|
||||
cc(cell_params_.cc),
|
||||
bwp_cfg(rnti_, cell_params_.bwps[0], uecfg_),
|
||||
|
@ -59,7 +59,7 @@ slot_ue ue_carrier::try_reserve(slot_point pdcch_slot,
|
|||
sfu.dl_pending_bytes = dl_pending_bytes;
|
||||
sfu.ul_pending_bytes = ul_pending_bytes;
|
||||
|
||||
const srsran_duplex_config_nr_t& tdd_cfg = cell_params.cell_cfg.duplex;
|
||||
const srsran_duplex_config_nr_t& tdd_cfg = cell_params.cfg.duplex;
|
||||
if (srsran_duplex_nr_is_dl(&tdd_cfg, 0, sfu.pdsch_slot.slot_idx())) {
|
||||
// If DL enabled
|
||||
sfu.h_dl = harq_ent.find_pending_dl_retx();
|
||||
|
|
|
@ -22,7 +22,7 @@ slot_cc_worker::slot_cc_worker(serv_cell_manager& cc_sched) :
|
|||
cell(cc_sched),
|
||||
cfg(cc_sched.cfg),
|
||||
bwp_alloc(cc_sched.bwps[0].grid),
|
||||
logger(srslog::fetch_basic_logger(cc_sched.cfg.sched_cfg.logger_name))
|
||||
logger(srslog::fetch_basic_logger(cc_sched.cfg.sched_args.logger_name))
|
||||
{}
|
||||
|
||||
void slot_cc_worker::enqueue_cc_event(srsran::move_callback<void()> ev)
|
||||
|
@ -116,7 +116,7 @@ void slot_cc_worker::run(slot_point pdcch_slot, ue_map_t& ue_db)
|
|||
|
||||
void slot_cc_worker::alloc_dl_ues()
|
||||
{
|
||||
if (not cfg.sched_cfg.pdsch_enabled) {
|
||||
if (not cfg.sched_args.pdsch_enabled) {
|
||||
return;
|
||||
}
|
||||
cell.bwps[0].data_sched->sched_dl_users(slot_ues, bwp_alloc);
|
||||
|
@ -124,7 +124,7 @@ void slot_cc_worker::alloc_dl_ues()
|
|||
|
||||
void slot_cc_worker::alloc_ul_ues()
|
||||
{
|
||||
if (not cfg.sched_cfg.pusch_enabled) {
|
||||
if (not cfg.sched_args.pusch_enabled) {
|
||||
return;
|
||||
}
|
||||
cell.bwps[0].data_sched->sched_ul_users(slot_ues, bwp_alloc);
|
||||
|
|
|
@ -30,15 +30,15 @@ void test_single_prach()
|
|||
std::default_random_engine rgen(rand_gen());
|
||||
|
||||
// Set scheduler configuration
|
||||
sched_nr_interface::sched_cfg_t sched_cfg{};
|
||||
sched_nr_interface::sched_args_t sched_cfg{};
|
||||
sched_cfg.auto_refill_buffer = std::uniform_int_distribution<uint32_t>{0, 1}(rgen) > 0;
|
||||
|
||||
// Set cells configuration
|
||||
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(1);
|
||||
sched_params schedparams{sched_cfg};
|
||||
schedparams.cells.emplace_back(0, cells_cfg[0], sched_cfg);
|
||||
const bwp_params& bwpparams = schedparams.cells[0].bwps[0];
|
||||
slot_ue_map_t slot_ues;
|
||||
const bwp_params_t& bwpparams = schedparams.cells[0].bwps[0];
|
||||
slot_ue_map_t slot_ues;
|
||||
|
||||
ra_sched rasched(bwpparams);
|
||||
TESTASSERT(rasched.empty());
|
||||
|
@ -81,7 +81,7 @@ void test_single_prach()
|
|||
}
|
||||
|
||||
// A PRACH arrives...
|
||||
sched_nr_interface::dl_sched_rar_info_t rainfo{};
|
||||
sched_nr_interface::rar_info_t rainfo{};
|
||||
rainfo.preamble_idx = 10;
|
||||
rainfo.temp_crnti = rnti;
|
||||
rainfo.prach_slot = prach_slot;
|
||||
|
|
|
@ -90,7 +90,7 @@ void sched_nr_ue_sim::update_dl_harqs(const sched_nr_cc_output_res_t& cc_out)
|
|||
}
|
||||
}
|
||||
|
||||
sched_nr_sim_base::sched_nr_sim_base(const sched_nr_interface::sched_cfg_t& sched_args,
|
||||
sched_nr_sim_base::sched_nr_sim_base(const sched_nr_interface::sched_args_t& sched_args,
|
||||
const std::vector<sched_nr_interface::cell_cfg_t>& cell_cfg_list,
|
||||
std::string test_name_) :
|
||||
logger(srslog::fetch_basic_logger("TEST")),
|
||||
|
@ -123,7 +123,7 @@ int sched_nr_sim_base::add_user(uint16_t rnti,
|
|||
sched_ptr->ue_cfg(rnti, ue_cfg_);
|
||||
ue_db.insert(std::make_pair(rnti, sched_nr_ue_sim(rnti, ue_cfg_, current_slot_tx, preamble_idx)));
|
||||
|
||||
sched_nr_interface::dl_sched_rar_info_t rach_info{};
|
||||
sched_nr_interface::rar_info_t rach_info{};
|
||||
rach_info.temp_crnti = rnti;
|
||||
rach_info.prach_slot = tti_rx;
|
||||
rach_info.preamble_idx = preamble_idx;
|
||||
|
@ -162,7 +162,7 @@ void sched_nr_sim_base::update(sched_nr_cc_output_res_t& cc_out)
|
|||
// Run common tests
|
||||
test_dl_pdcch_consistency(cc_out.dl_cc_result->dl_sched.pdcch_dl);
|
||||
test_pdsch_consistency(cc_out.dl_cc_result->dl_sched.pdsch);
|
||||
test_ssb_scheduled_grant(cc_out.slot, ctxt.cell_params[cc_out.cc].cell_cfg, cc_out.dl_cc_result->dl_sched.ssb);
|
||||
test_ssb_scheduled_grant(cc_out.slot, ctxt.cell_params[cc_out.cc].cfg, cc_out.dl_cc_result->dl_sched.ssb);
|
||||
|
||||
// Run UE-dedicated tests
|
||||
test_dl_sched_result(ctxt, cc_out);
|
||||
|
|
|
@ -74,8 +74,8 @@ struct sim_nr_ue_ctxt_t {
|
|||
}
|
||||
};
|
||||
struct sim_nr_enb_ctxt_t {
|
||||
srsran::span<const sched_nr_impl::sched_cell_params> cell_params;
|
||||
std::map<uint16_t, const sim_nr_ue_ctxt_t*> ue_db;
|
||||
srsran::span<const sched_nr_impl::cell_params_t> cell_params;
|
||||
std::map<uint16_t, const sim_nr_ue_ctxt_t*> ue_db;
|
||||
};
|
||||
|
||||
class sched_nr_ue_sim
|
||||
|
@ -101,7 +101,7 @@ private:
|
|||
class sched_nr_sim_base
|
||||
{
|
||||
public:
|
||||
sched_nr_sim_base(const sched_nr_interface::sched_cfg_t& sched_args,
|
||||
sched_nr_sim_base(const sched_nr_interface::sched_args_t& sched_args,
|
||||
const std::vector<sched_nr_interface::cell_cfg_t>& cell_params_,
|
||||
std::string test_name);
|
||||
virtual ~sched_nr_sim_base();
|
||||
|
@ -129,9 +129,9 @@ public:
|
|||
const sched_nr_ue_sim* ret = find_rnti(rnti);
|
||||
return ret == nullptr ? nullptr : &ret->get_ctxt().ue_cfg;
|
||||
}
|
||||
sched_nr* get_sched() { return sched_ptr.get(); }
|
||||
srsran::const_span<sched_nr_impl::sched_cell_params> get_cell_params() { return cell_params; }
|
||||
slot_point get_slot_rx() const
|
||||
sched_nr* get_sched() { return sched_ptr.get(); }
|
||||
srsran::const_span<sched_nr_impl::cell_params_t> get_cell_params() { return cell_params; }
|
||||
slot_point get_slot_rx() const
|
||||
{
|
||||
std::lock_guard<std::mutex> lock(mutex);
|
||||
return current_slot_tx;
|
||||
|
@ -149,11 +149,11 @@ private:
|
|||
int set_default_slot_events(const sim_nr_ue_ctxt_t& ue_ctxt, ue_nr_slot_events& pending_events);
|
||||
int apply_slot_events(sim_nr_ue_ctxt_t& ue_ctxt, const ue_nr_slot_events& events);
|
||||
|
||||
std::string test_name;
|
||||
srslog::basic_logger& logger;
|
||||
srslog::basic_logger& mac_logger;
|
||||
std::unique_ptr<sched_nr> sched_ptr;
|
||||
std::vector<sched_nr_impl::sched_cell_params> cell_params;
|
||||
std::string test_name;
|
||||
srslog::basic_logger& logger;
|
||||
srslog::basic_logger& mac_logger;
|
||||
std::unique_ptr<sched_nr> sched_ptr;
|
||||
std::vector<sched_nr_impl::cell_params_t> cell_params;
|
||||
|
||||
slot_point current_slot_tx;
|
||||
int cc_finished = 0;
|
||||
|
|
|
@ -81,7 +81,7 @@ void sched_nr_cfg_serialized_test()
|
|||
uint32_t max_nof_ttis = 1000, nof_sectors = 4;
|
||||
task_job_manager tasks;
|
||||
|
||||
sched_nr_interface::sched_cfg_t cfg;
|
||||
sched_nr_interface::sched_args_t cfg;
|
||||
cfg.auto_refill_buffer = true;
|
||||
|
||||
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
|
||||
|
@ -132,7 +132,7 @@ void sched_nr_cfg_parallel_cc_test()
|
|||
uint32_t max_nof_ttis = 1000;
|
||||
task_job_manager tasks;
|
||||
|
||||
sched_nr_interface::sched_cfg_t cfg;
|
||||
sched_nr_interface::sched_args_t cfg;
|
||||
cfg.auto_refill_buffer = true;
|
||||
|
||||
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
|
||||
|
|
Loading…
Reference in New Issue