mirror of https://github.com/PentHertz/srsLTE.git
Fix CORESET0 related PDSCH resource allocation procedure
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@ -114,6 +114,7 @@ typedef struct SRSRAN_API {
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srsran_dci_location_t location; ///< DCI location
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srsran_search_space_type_t ss_type; ///< Search space type
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uint32_t coreset_id; ///< CORESET identifier
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uint32_t coreset_start_rb; ///< CORESET lowest RB index in the resource grid
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srsran_rnti_type_t rnti_type; ///< RNTI type
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srsran_dci_format_nr_t format; ///< DCI format
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uint16_t rnti; ///< UE temporal RNTI
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@ -182,6 +183,9 @@ typedef struct SRSRAN_API {
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uint32_t cbg_flush; ///< CBG flushing out information (CBGFI)
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uint32_t dmrs_id; ///< DMRS sequence initialization
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// DL context from unpacking. Required for resource allocation
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uint32_t coreset0_bw; ///< CORESET0 size used for frequency resource allocation
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} srsran_dci_dl_nr_t;
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/**
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@ -226,6 +226,7 @@ bool phy_cfg_nr_t::get_dci_ctx_pdsch_rnti_c(uint32_t ss_id,
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ctx.location = location;
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ctx.ss_type = ss.type;
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ctx.coreset_id = ss.coreset_id;
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ctx.coreset_start_rb = srsran_coreset_start_rb(&pdcch.coreset[ss.coreset_id]);
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ctx.rnti_type = srsran_rnti_type_c;
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ctx.format = format;
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ctx.rnti = rnti;
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@ -251,6 +252,7 @@ bool phy_cfg_nr_t::get_dci_ctx_pusch_rnti_c(uint32_t ss_id,
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ctx.location = location;
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ctx.ss_type = ss.type;
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ctx.coreset_id = ss.coreset_id;
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ctx.coreset_start_rb = srsran_coreset_start_rb(&pdcch.coreset[ss.coreset_id]);
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ctx.rnti_type = srsran_rnti_type_c;
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ctx.format = format;
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ctx.rnti = rnti;
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@ -1991,6 +1991,7 @@ int srsran_dci_nr_dl_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_t* msg,
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// Copy DCI MSG fields
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dci->ctx = msg->ctx;
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dci->coreset0_bw = q->cfg.coreset0_bw;
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// Pack DCI
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switch (msg->ctx.format) {
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@ -292,10 +292,26 @@ int srsran_ra_dl_nr_freq(const srsran_carrier_nr_t* carrier,
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return SRSRAN_ERROR_INVALID_INPUTS;
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}
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// For a PDSCH scheduled with a DCI format 1_0 in any type of PDCCH common search space, regardless of which
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// bandwidth part is the active bandwidth part, RB numbering starts from the lowest RB of the CORESET in which the
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// DCI was received; otherwise RB numbering starts from the lowest RB in the determined downlink bandwidth part.
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uint32_t start_rb = 0;
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if (dci_dl->ctx.format == srsran_dci_format_nr_1_0 && SRSRAN_SEARCH_SPACE_IS_COMMON(dci_dl->ctx.ss_type)) {
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start_rb = dci_dl->ctx.coreset_start_rb;
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}
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// when DCI format 1_0 is decoded in any common search space in which case the size of CORESET 0 shall be used if
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// CORESET 0 is configured for the cell and the size of initial DL bandwidth part shall be used if CORESET 0 is not
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// configured for the cell.
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uint32_t type1_bwp_sz = carrier->nof_prb;
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if (SRSRAN_SEARCH_SPACE_IS_COMMON(dci_dl->ctx.ss_type) && dci_dl->coreset0_bw != 0) {
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type1_bwp_sz = dci_dl->coreset0_bw;
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}
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// The UE shall assume that when the scheduling grant is received with DCI format 1_0 , then downlink resource
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// allocation type 1 is used.
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if (dci_dl->ctx.format == srsran_dci_format_nr_1_0) {
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return ra_helper_freq_type1(carrier->nof_prb, dci_dl->freq_domain_assigment, grant);
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return ra_helper_freq_type1(type1_bwp_sz, start_rb, dci_dl->freq_domain_assigment, grant);
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}
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// If the scheduling DCI is configured to indicate the downlink resource allocation type as part of the Frequency
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@ -309,7 +325,7 @@ int srsran_ra_dl_nr_freq(const srsran_carrier_nr_t* carrier,
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// Otherwise the UE shall use the downlink frequency resource allocation type as defined by the higher layer parameter
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// resourceAllocation.
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if (cfg->alloc == srsran_resource_alloc_type1) {
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return ra_helper_freq_type1(carrier->nof_prb, dci_dl->freq_domain_assigment, grant);
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return ra_helper_freq_type1(type1_bwp_sz, start_rb, dci_dl->freq_domain_assigment, grant);
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}
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if (cfg->alloc == srsran_resource_alloc_type0) {
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@ -61,7 +61,7 @@ static int ra_helper_freq_type0(const srsran_carrier_nr_t* carrier,
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return 0;
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}
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static int ra_helper_freq_type1(uint32_t N_bwp_size, uint32_t riv, srsran_sch_grant_nr_t* grant)
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static int ra_helper_freq_type1(uint32_t N_bwp_size, uint32_t start_rb, uint32_t riv, srsran_sch_grant_nr_t* grant)
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{
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uint32_t start = 0;
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uint32_t len = 0;
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@ -72,6 +72,9 @@ static int ra_helper_freq_type1(uint32_t N_bwp_size, uint32_t riv, srsran_sch_gr
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return SRSRAN_ERROR;
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}
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// Apply numbering start
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start += start_rb;
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for (uint32_t i = 0; i < start; i++) {
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grant->prb_idx[i] = false;
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}
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@ -440,13 +440,13 @@ int srsran_ra_ul_nr_freq(const srsran_carrier_nr_t* carrier,
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// TS 38.213 PUSCH scheduled by RAR UL grant
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if (dci_ul->ctx.format == srsran_dci_format_nr_rar) {
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return ra_helper_freq_type1(carrier->nof_prb, dci_ul->freq_domain_assigment, grant);
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return ra_helper_freq_type1(carrier->nof_prb, 0, dci_ul->freq_domain_assigment, grant);
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}
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// The UE shall assume that when the scheduling PDCCH is received with DCI format 0_0, then uplink resource
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// allocation type 1 is used.
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if (dci_ul->ctx.format == srsran_dci_format_nr_0_0) {
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return ra_helper_freq_type1(carrier->nof_prb, dci_ul->freq_domain_assigment, grant);
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return ra_helper_freq_type1(carrier->nof_prb, 0, dci_ul->freq_domain_assigment, grant);
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}
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// If the scheduling DCI is configured to indicate the uplink resource allocation type as part of the Frequency domain
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@ -459,7 +459,7 @@ int srsran_ra_ul_nr_freq(const srsran_carrier_nr_t* carrier,
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// Otherwise the UE shall use the uplink frequency resource allocation type as defined by the higher layer parameter
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// resourceAllocation.
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if (cfg->alloc == srsran_resource_alloc_type1) {
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return ra_helper_freq_type1(carrier->nof_prb, dci_ul->freq_domain_assigment, grant);
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return ra_helper_freq_type1(carrier->nof_prb, 0, dci_ul->freq_domain_assigment, grant);
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}
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if (cfg->alloc == srsran_resource_alloc_type0) {
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@ -387,6 +387,7 @@ static int ue_dl_nr_find_dci_ss(srsran_ue_dl_nr_t* q,
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ctx.location.ncce = candidates[ncce_idx];
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ctx.ss_type = search_space->type;
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ctx.coreset_id = search_space->coreset_id;
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ctx.coreset_start_rb = srsran_coreset_start_rb(&q->cfg.coreset[search_space->coreset_id]);
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ctx.rnti_type = rnti_type;
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ctx.rnti = rnti;
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ctx.format = dci_format;
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@ -168,6 +168,7 @@ static int work_gnb_dl(srsran_gnb_dl_t* gnb_dl,
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dci_dl.ctx.location = *dci_location;
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dci_dl.ctx.ss_type = search_space->type;
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dci_dl.ctx.coreset_id = 1;
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dci_dl.ctx.coreset_start_rb = 0;
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dci_dl.freq_domain_assigment = 0;
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dci_dl.time_domain_assigment = 0;
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dci_dl.vrb_to_prb_mapping = 0;
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