mirror of https://github.com/PentHertz/srsLTE.git
Improved float XOR readability
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751b6858b3
commit
eef3fac863
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@ -211,10 +211,17 @@ void srsran_sequence_state_init(srsran_sequence_state_t* s, uint32_t seed)
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s->x2 = sequence_get_x2_init(seed);
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}
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#define FLOAT_U32_XOR(DST, SRC, U32_MASK) \
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do { \
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uint32_t temp_u32; \
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memcpy(&temp_u32, &(SRC), 4); \
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temp_u32 ^= (U32_MASK); \
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memcpy(&(DST), &temp_u32, 4); \
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} while (false)
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void srsran_sequence_state_gen_f(srsran_sequence_state_t* s, float value, float* out, uint32_t length)
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{
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uint32_t i = 0;
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const float xor [2] = {+0.0F, -0.0F};
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if (length >= SEQUENCE_PAR_BITS) {
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for (; i < length - (SEQUENCE_PAR_BITS - 1); i += SEQUENCE_PAR_BITS) {
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@ -246,7 +253,7 @@ void srsran_sequence_state_gen_f(srsran_sequence_state_t* s, float value, float*
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#endif
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// Finish the parallel bits with generic code
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for (; j < SEQUENCE_PAR_BITS; j++) {
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*((uint32_t*)&out[i + j]) = *((uint32_t*)&value) ^ *((uint32_t*)&xor[(c >> j) & 1U]);
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FLOAT_U32_XOR(out[i + j], value, (c << (31U - j)) & 0x80000000);
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}
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// Step sequences
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@ -256,7 +263,7 @@ void srsran_sequence_state_gen_f(srsran_sequence_state_t* s, float value, float*
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}
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for (; i < length; i++) {
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*((uint32_t*)&out[i]) = *((uint32_t*)&value) ^ *((uint32_t*)&xor[(s->x1 ^ s->x2) & 1U]);
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FLOAT_U32_XOR(out[i], value, (s->x1 ^ s->x2) << 31U);
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// Step sequences
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s->x1 = sequence_gen_LTE_pr_memless_step_x1(s->x1);
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@ -267,7 +274,6 @@ void srsran_sequence_state_gen_f(srsran_sequence_state_t* s, float value, float*
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void srsran_sequence_state_apply_f(srsran_sequence_state_t* s, const float* in, float* out, uint32_t length)
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{
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uint32_t i = 0;
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const float xor [2] = {+0.0F, -0.0F};
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if (length >= SEQUENCE_PAR_BITS) {
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for (; i < length - (SEQUENCE_PAR_BITS - 1); i += SEQUENCE_PAR_BITS) {
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@ -289,17 +295,17 @@ void srsran_sequence_state_apply_f(srsran_sequence_state_t* s, const float* in,
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mask = _mm_and_si128(mask, (__m128i)_mm_set1_ps(-0.0F));
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// Load input
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__m128 v = _mm_load_ps(in + i + j);
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__m128 v = _mm_loadu_ps(in + i + j);
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// Loads input and perform sign XOR
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v = _mm_xor_ps((__m128)mask, v);
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_mm_storeu_ps(out + i + j, v);
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}
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#endif
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#endif // LV_HAVE_SSE
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// Finish the parallel bits with generic code
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for (; j < SEQUENCE_PAR_BITS; j++) {
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*((uint32_t*)&out[i + j]) = *((uint32_t*)&in[i + j]) ^ *((uint32_t*)&xor[(c >> j) & 1U]);
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FLOAT_U32_XOR(out[i + j], in[i + j], (c << (31U - j)) & 0x80000000);
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}
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// Step sequences
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@ -309,7 +315,7 @@ void srsran_sequence_state_apply_f(srsran_sequence_state_t* s, const float* in,
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}
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for (; i < length; i++) {
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*((uint32_t*)&out[i]) = *((uint32_t*)&in[i]) ^ *((uint32_t*)&xor[(s->x1 ^ s->x2) & 1U]);
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FLOAT_U32_XOR(out[i], in[i], (s->x1 ^ s->x2) << 31U);
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// Step sequences
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s->x1 = sequence_gen_LTE_pr_memless_step_x1(s->x1);
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