From f7016633d24e3956412b294bebe28410a63f49ee Mon Sep 17 00:00:00 2001 From: Francisco Date: Fri, 30 Apr 2021 15:53:03 +0100 Subject: [PATCH] sched, fix - avoid tpc commands when target pusch and pucch snr are not specified --- srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h | 14 +++++--------- srsenb/test/mac/sched_tpc_test.cc | 9 ++++----- 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h b/srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h index e65b86149..99dc58270 100644 --- a/srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h +++ b/srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h @@ -110,14 +110,14 @@ public: * @remark See TS 36.213 Section 5.1.1 * @return accumulated TPC value {-1, 0, 1, 3} */ - uint8_t encode_pusch_tpc() { return enconde_tpc(PUSCH_CODE); } + uint8_t encode_pusch_tpc() { return encode_tpc(PUSCH_CODE); } /** * Called during DCI format1/2A/A encoding to set PUCCH TPC command * @remark See TS 36.213 Section 5.1.2 * @return accumulated TPC value {-1, 0, 1, 3} */ - uint8_t encode_pucch_tpc() { return enconde_tpc(PUCCH_CODE); } + uint8_t encode_pucch_tpc() { return encode_tpc(PUCCH_CODE); } uint32_t max_ul_prbs() const { return max_prbs_cached; } @@ -138,18 +138,14 @@ private: return 1; } } - uint8_t enconde_tpc(uint32_t cc) + uint8_t encode_tpc(uint32_t cc) { float target_snr_dB = cc == PUSCH_CODE ? target_pusch_snr_dB : target_pucch_snr_dB; auto& ch_snr = snr_estim_list[cc]; assert(ch_snr.pending_delta == 0); // ensure called once per {cc,tti} if (target_snr_dB < 0) { - // undefined target SINR case. Increase Tx power once per PHR, considering the number of allocable PRBs remains - // unchanged - if (not ch_snr.phr_flag) { - ch_snr.pending_delta = (max_prbs_cached == nof_prb) ? 1 : (last_phr < 0 ? -1 : 0); - ch_snr.phr_flag = true; - } + // undefined target sinr case. + ch_snr.pending_delta = 0; } else { // target SINR is finite and there is power headroom float diff = target_snr_dB - ch_snr.snr_avg.value(); diff --git a/srsenb/test/mac/sched_tpc_test.cc b/srsenb/test/mac/sched_tpc_test.cc index f928fcaa0..acfe07ea4 100644 --- a/srsenb/test/mac/sched_tpc_test.cc +++ b/srsenb/test/mac/sched_tpc_test.cc @@ -100,7 +100,7 @@ int test_undefined_target_snr() TESTASSERT(sum_pusch == 0); TESTASSERT(sum_pucch == 0); - // TEST: If the PHR allows full utilization of available PRBs, the TPC slightly increments UL Tx power + // TEST: Check that high PHR allows full utilization of available PRBs, TPC remains at zero (no target SINR) int phr = 30; tpcfsm.set_phr(phr); TESTASSERT(tpcfsm.max_ul_prbs() == 50); @@ -111,8 +111,7 @@ int test_undefined_target_snr() sum_pusch += decode_tpc(tpcfsm.encode_pusch_tpc()); sum_pucch += decode_tpc(tpcfsm.encode_pucch_tpc()); } - TESTASSERT(sum_pusch > 0 and sum_pusch <= 3); - TESTASSERT(sum_pucch > 0 and sum_pucch <= 3); + TESTASSERT(sum_pusch == 0 and sum_pucch == 0); // TEST: PHR is too low to allow all PRBs to be allocated. This event should not affect TPC commands phr = 5; @@ -135,8 +134,8 @@ int test_undefined_target_snr() sum_pusch += decode_tpc(tpcfsm.encode_pusch_tpc()); sum_pucch += decode_tpc(tpcfsm.encode_pucch_tpc()); } - TESTASSERT(sum_pusch <= 0 and sum_pusch >= -1); - TESTASSERT(sum_pucch <= 0 and sum_pucch >= -1); + TESTASSERT(sum_pusch == 0); + TESTASSERT(sum_pucch == 0); return SRSRAN_SUCCESS; }