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srsLTE
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5,748 Commits 3 Branches 23 Tags 67 MiB
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26 Commits

Author SHA1 Message Date
Xavier Arteaga d94078d543 Minor changes 
Fix UE sequence generation

minor change
 2020-05-01 21:07:33 +02:00
Xavier Arteaga 9d0a3268e8 Added DL channel estimator algorithm options 2020-04-28 17:26:01 +02:00
Andre Puschmann ba4d0aa860 remove blacklisted ARM PHY tests 
issue causing decoding failure for QAM256 are fixed now so blacklist can go away
 2020-04-15 21:58:55 +02:00
Xavier Arteaga 71476d1079 Minor phy_dl_test modification 2020-04-15 11:39:57 +02:00
Xavier Arteaga 9a2b0b7cc7 Standard vector allocation uses vector library 2020-04-02 20:49:58 +02:00
Xavier Arteaga e832769ae6 Updated copyright 2020-03-16 11:26:06 +01:00
Xavier Arteaga f261365c91 Initial EVM calculation commit and other easthetic changes 2020-02-28 12:10:32 +01:00
Xavier Arteaga d66fdefbb3 Added more docs to PUCCH 1b CS resource selection 2020-02-13 10:29:00 +01:00
Xavier Arteaga 1f762844ee Initial PUCCH format 3 decoder 2020-02-13 10:29:00 +01:00
Xavier Arteaga 35f4e5d69a Initial PUCCH 1B with channel selection 2020-02-13 10:29:00 +01:00
Andre Puschmann c54fa568be fixing typo in CMake for PHY DL test 2019-12-24 10:51:48 +01:00
Xavier Arteaga 11eafa8ab4 srsLTE: FFTW wisdom gets loaded and saved by default 2019-12-23 22:57:37 +01:00
Andre Puschmann 9e1b8bc95e disabling certain PHY DL tests that aren't working on ARM due to Turbo issues 2019-12-20 18:54:41 +01:00
Pedro Alvarez c5979f59eb Clang format UE, eNB and lib (#850) 
* Clang-formated UE, eNB and lib.
* Fixed compiling errors from clang-format.
* Fix linking issues introduced by clang-format
* Fix poor formating in initializing arrays of arrays.
* Fix mistake in conflict resolution on rm_turbo.c
* Re-apply clang format to gtpc_ies.h
 2019-12-16 16:04:22 +01:00
Ismael Gomez bfddc55148
RRC-PHY interface (#639) 
RRC-PHY interface refactor. Moved RRC-MAC interface to rrc_asn1_utils and created RRC-PHY interface also in rrc_asn1_utils. All ASN1 includes should be made from rrc_asn1_utils only keeping ue_interfaces clean of ASN1

Tested with different common and dedicated configurations (64QAM UL, 256QAM, CA, SRS enabled/disabled, etc)
 2019-09-04 16:59:10 +02:00
Guillem Foreman 2a8ec5c9b9 More fixes 256QAM 2019-07-12 15:35:27 +02:00
Guillem Foreman eab73829f6 Changes requested 2019-07-12 14:11:26 +02:00
Guillem Foreman 46724c336d Fixed errors for phy_dl_test and pdsch test 2019-07-04 15:49:43 +02:00
Guillem Foreman db4127ca64 Fixes 256QAM, added pdsch table 2, fixed warnings 2019-07-04 15:49:43 +02:00
Xavier Arteaga c18a59730c Solved PHY unit test memory leaks 2019-04-30 15:56:47 +02:00
Andre Puschmann 4b01a2e4a0 update copyright notice 2019-04-29 09:20:02 +02:00
Ismael Gomez 7780b1aba5 add tdd/ca support 2019-04-25 20:57:58 +02:00
Francisco Paisana 0204db2e12 new asn1 rrc library 2019-01-17 17:43:13 +01:00
Andre Puschmann d19eb28a16 fix various variable initializations that gcc-4.8 complained about 2018-09-05 12:34:40 +02:00
Xavier Arteaga c1a0b17c40 Improved phy_dl_test 2018-07-17 15:37:57 +02:00
Xavier Arteaga e837788ad4 Added initial Generic DL Phy test 2018-07-02 10:20:40 +02:00