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srsLTE
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103 Commits

Author SHA1 Message Date
Francisco Paisana fad897cb35 DL scheduler metric now takes into account the min and max of RBGs possible. This is to forbid segmentation of SRB0 allocations 2020-03-10 22:06:07 +00:00
Francisco Paisana 639f473042 fixed unsigned signed comparison 2020-03-10 14:17:49 +01:00
Francisco Paisana 1e63fa41cf made ue_cc_idx int to set to -1 for rar and bc allocs 2020-03-10 14:17:49 +01:00
Francisco Paisana f3c3c52fcd added ue_cc_idx to dci allocation 2020-03-10 14:17:49 +01:00
Xavier Arteaga 002a68e183 SRSENB: hard-coded parametrized PUCCH DMRS correlation threshold 2020-03-10 09:19:54 +01:00
Xavier Arteaga 64caa4321b Fix UL control decoding. Some minor aesthetic changes. 2020-03-10 09:19:54 +01:00
Xavier Arteaga a968fb02d3 Increase PUCCH correlatiion threasholds 2020-03-06 13:58:49 +01:00
Xavier Arteaga da701cd82b SRSENB: Added PUSCH TA and EVM measurement. Some more PHY cleanup. 2020-03-06 13:58:49 +01:00
Xavier Arteaga 47cbbcbd57 Improve PUSCH UCI decoder 2020-03-06 13:58:49 +01:00
Francisco Paisana a6320f93b8 remove remaining const_casts 2020-03-05 20:23:07 +00:00
Francisco Paisana ec1f1cc677 remove const_casts from scheduler. Fix ODR issue 2020-03-05 20:23:07 +00:00
Andre Puschmann e4b5fa122f add set_cell() call to PSCCH and allocate for max PRB in pscch_init() 2020-03-03 16:22:51 +01:00
Andre Puschmann 09f7355870 use srslte_cell_sl_t in PSCCH 2020-03-03 16:22:51 +01:00
Andre Puschmann 14000f7ae7 adding phy_common_sl.{c,h} 2020-03-03 16:22:51 +01:00
Tiago Alves cabd9ae742 baseline implementation of pscch 2020-03-03 16:22:51 +01:00
Xavier Arteaga a4135e41a5 Added PUCCH collision checker 2020-03-02 12:19:09 +01:00
Xavier Arteaga 2fc0832f05 Addition of DL HARQ-ACK generation procedure for eNb DL and minor aesthetic changes 2020-03-02 12:19:09 +01:00
Xavier Arteaga e621853566 Minor aesthetics changes 2020-02-28 12:10:32 +01:00
Xavier Arteaga f261365c91 Initial EVM calculation commit and other easthetic changes 2020-02-28 12:10:32 +01:00
Pedro Alvarez aecfb151ce Apply clang-format to the lib in preperation for PR. 2020-02-20 20:53:27 +01:00
Ismael Gomez d8d10daebe
Fix bug in SRS using the previous grant to compute collision with PUSCH (#958) 2020-02-16 21:30:04 +01:00
Xavier Arteaga 67c07dfb56 Moved UL/DL PUCCH procedures into pucch_proc 2020-02-13 10:29:00 +01:00
Xavier Arteaga 5dbc96458a Sets PUCCH decode threshold as macro 2020-02-13 10:29:00 +01:00
Xavier Arteaga bc10943a2b Added get max TB from DCI format 2020-02-13 10:29:00 +01:00
Xavier Arteaga 231431f569 SRSENB: enabled CA PUCCH decode in eNb 2020-02-13 10:29:00 +01:00
Xavier Arteaga d66fdefbb3 Added more docs to PUCCH 1b CS resource selection 2020-02-13 10:29:00 +01:00
Xavier Arteaga 1f762844ee Initial PUCCH format 3 decoder 2020-02-13 10:29:00 +01:00
Xavier Arteaga 35f4e5d69a Initial PUCCH 1B with channel selection 2020-02-13 10:29:00 +01:00
Andre Puschmann 81b46723f6 adding NPDCCH 2020-01-28 17:46:54 +01:00
Andre Puschmann d98bc71057 fix PSBCH and use UL-SCH interleaver 2020-01-14 21:23:43 +01:00
Andre Puschmann 2e7a357226 expose UL-SCH interleaver to use in Sidelink 2020-01-14 21:23:43 +01:00
Xavier Arteaga 0912701cb0 srsLTE: sidelink minor corrections 2019-12-23 23:08:32 +01:00
Andre Puschmann 7de51c8236 refactor Sidelink PSBCH and DMRS code 2019-12-23 23:08:32 +01:00
Tiago Ferreira Alves 3fed21ce3e PSSS and SSSS implementation 2019-12-18 11:27:10 +01:00
Andre Puschmann 476f970ee1 replace FIXME with TODO 2019-12-18 11:25:56 +01:00
Pedro Alvarez c5979f59eb Clang format UE, eNB and lib (#850) 
* Clang-formated UE, eNB and lib.
* Fixed compiling errors from clang-format.
* Fix linking issues introduced by clang-format
* Fix poor formating in initializing arrays of arrays.
* Fix mistake in conflict resolution on rm_turbo.c
* Re-apply clang format to gtpc_ies.h
 2019-12-16 16:04:22 +01:00
Andre Puschmann 40bacb80b1 fixing comments from Xavier's review 2019-11-17 18:51:24 +01:00
Andre Puschmann e05ecdb139 adding NB-IoT DL channel estamiation and NPBCH code 2019-11-17 18:51:24 +01:00
Ismael Gomez 3828e03f33
Refactor in eNodeB, add channel emulator and fixes in OFDM 
* Added channel emulator to srsENB. Added support for fixed delay

* Bug in OFDM when using nonguru mode

* A few changes and refactor in eNodeB
 2019-10-23 11:09:39 -05:00
Ismael Gomez 1d83bb08e2 Changes in ACK procedure to support CA. Tested 1 cell in SISO/MIMO 2019-10-14 11:20:35 +02:00
Ismael Gomez bfddc55148
RRC-PHY interface (#639) 
RRC-PHY interface refactor. Moved RRC-MAC interface to rrc_asn1_utils and created RRC-PHY interface also in rrc_asn1_utils. All ASN1 includes should be made from rrc_asn1_utils only keeping ue_interfaces clean of ASN1

Tested with different common and dedicated configurations (64QAM UL, 256QAM, CA, SRS enabled/disabled, etc)
 2019-09-04 16:59:10 +02:00
Ismael Gomez 19066c49ab Ad Rel10 info to dci logs 2019-07-30 18:18:44 +02:00
Guillem Foreman 535325bc37 srsLTE: added resource allocation extended tables for 256QAM and integration with PDSCH test 2019-07-04 15:49:43 +02:00
Ismael Gomez 786830daf3 Fix minor issues for TDD 2019-05-02 19:31:46 +02:00
Andre Puschmann 4b01a2e4a0 update copyright notice 2019-04-29 09:20:02 +02:00
Ismael Gomez 7780b1aba5 add tdd/ca support 2019-04-25 20:57:58 +02:00
Francisco Paisana 0204db2e12 new asn1 rrc library 2019-01-17 17:43:13 +01:00
Ismael Gomez 197d855d3f Fix issue #240 2018-09-19 16:41:59 +02:00
Ismael Gomez bc9d342959
New optimization on the PHY for both UE and eNodeB (#251) 
* New parallel Turbodecoder implementation in SSE/AVX 16-bit and 8-bit

* Optimised UL Interleaver

* Include TB CRC calculation in FEC encoder

* New threading priorities
 2018-09-04 17:51:35 +02:00
Ismael Gomez 8c92f3fddc
Improvements and fixes on srsENB scheduler (#228) 2018-06-29 11:25:22 +02:00