PentHertz
/
srsLTE
mirror of https://github.com/PentHertz/srsLTE.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,901 Commits 3 Branches 23 Tags 67 MiB
Commit Graph

1958 Commits

Author SHA1 Message Date
Francisco Paisana 883c2900c8 fix issue with future clear 2020-01-24 10:10:27 +00:00
Francisco Paisana 91d83fc20d different way to retrieve a proc future 2020-01-24 10:10:27 +00:00
Ismael Gomez 171e26ee68 Add checks more checks for UL grants 2020-01-24 10:40:39 +01:00
Xavier Arteaga dcb3bc0135 srsLTE: apply CLang Format in sch.c 2020-01-24 10:40:39 +01:00
Xavier Arteaga 905273b36a srsLTE: more memory corruption counter measures in ul_sch_encode 2020-01-24 10:40:39 +01:00
Xavier Arteaga 3b138b25c6 srsLTE: UL SCH Beta offset access fortification 2020-01-24 10:40:39 +01:00
Xavier Arteaga 8b6ba1aacf srsLTE: removed overlap bytes check in RLC AM 2020-01-24 10:36:41 +01:00
Xavier Arteaga 5872e763bf SRSLTE: RLC AM remove completely overlapped segments 2020-01-24 10:36:41 +01:00
Xavier Arteaga 39bec9aab1 SRSLTE: fix RLC reordering and segment overlaping 2020-01-24 10:36:41 +01:00
Xavier Arteaga d3537fc340 srsLTE: expanded RLC stress test with the addition of multiple PDU per TTI in reverse order 2020-01-24 10:36:41 +01:00
Francisco Paisana 5ae3afd2b8 created cbit_ref for unpacking const buffers 2020-01-23 12:22:19 +00:00
Francisco Paisana 58e555e86c update all asn1 files 2020-01-23 12:22:19 +00:00
Francisco Paisana 5468189cd9 fix some variables' naming (e.g. x2_ap -> x2ap, e_rab -> erab) 2020-01-21 00:58:19 +00:00
Francisco Paisana 2a83eee0ee fix security key setup 2020-01-21 00:58:19 +00:00
Francisco Paisana ee24b59924 converted s1ap to new s1ap asn1 lib. Cleaned up bitstring packing/unpacking and bitstring types 2020-01-21 00:58:19 +00:00
Francisco Paisana 25bb36cdc3 converted ho preparation to new s1ap asn1 lib. Extended s1ap test 2020-01-21 00:58:19 +00:00
Francisco Paisana 3066b404ac fix integer ext asn1 generation 2020-01-21 00:58:19 +00:00
Francisco Paisana c87de9d889 added s1ap_asn1_test 2020-01-21 00:58:19 +00:00
Francisco Paisana b6c53d786b updated s1ap rrc interface with new asn1 lib types 2020-01-21 00:58:19 +00:00
Francisco Paisana 61b3e6b57e imported new s1ap asn1 lib 2020-01-21 00:58:19 +00:00
Andre Puschmann b43c531c15 adding CMW500 SLSS capture and enable PSBCH test 2020-01-14 21:23:43 +01:00
Andre Puschmann d98bc71057 fix PSBCH and use UL-SCH interleaver 2020-01-14 21:23:43 +01:00
Andre Puschmann 9012ca5faa fix PSBCH tests 2020-01-14 21:23:43 +01:00
Andre Puschmann 2e7a357226 expose UL-SCH interleaver to use in Sidelink 2020-01-14 21:23:43 +01:00
Andre Puschmann b0bfc7956d use const& in metrics interface 2020-01-14 20:52:09 +01:00
Xavier Arteaga bca5d1a95a srsLTE: extend viterbi test 2020-01-13 16:20:31 +01:00
Francisco Paisana 182a721329 fix some integer printf potential warnings 2020-01-07 21:33:31 +01:00
Xavier Arteaga 8a666ee455 srsLTE: Increase UHD default sampling rate. Enables warning if USB2 is used. 2020-01-07 11:16:37 +01:00
Andre Puschmann be4ba504bd fix another bunch of uninit memory in tests, and one in srsENB 2020-01-07 11:12:34 +01:00
Andre Puschmann 0554064bf0 refactor NPBCH init, fix memset with zero length 2020-01-07 11:12:34 +01:00
Andre Puschmann 0394d21dd2 fix uninit memory in chest sl test when not test is executed 2020-01-07 11:12:34 +01:00
Andre Puschmann 06afe74bef add virtual dtor in sched_interface base class 2019-12-30 22:15:31 +01:00
Andre Puschmann 6ec573987a remove default value for 'blocking' param from pdcp::write_sdu() 
there were two defaults and one was shadowing the other. This
commit removes both defaults and uses blocking-mode for RRC
calls to PDCP in the UE. The eNB write_sdu() uses the non-blocking
mode by default. We have to review the eNB's RRC perhaps and use blocking
there too and non-blocking only for data plane
 2019-12-29 23:45:37 +01:00
Andre Puschmann 1155adf007 fixing printfs in asn1_utils 2019-12-29 23:37:49 +01:00
Andre Puschmann 0bd493b567 call byte_buffer cleanup in two enb tests and fix typo 2019-12-26 22:06:34 +01:00
Andre Puschmann c54fa568be fixing typo in CMake for PHY DL test 2019-12-24 10:51:48 +01:00
Andre Puschmann 03512547f5 add test for Sidelink channel estimator 2019-12-23 23:08:32 +01:00
Xavier Arteaga 0912701cb0 srsLTE: sidelink minor corrections 2019-12-23 23:08:32 +01:00
Andre Puschmann 7de51c8236 refactor Sidelink PSBCH and DMRS code 2019-12-23 23:08:32 +01:00
Xavier Arteaga 36b2102de8 SRSUE: avoid testing ue_phy_test 2019-12-23 22:57:37 +01:00
Xavier Arteaga 307c27dc30 srsLTE: ZMQ renamed struct field 2019-12-23 22:57:37 +01:00
Xavier Arteaga 2d98f92823 srsLTE: upgraded ZMQ for supporting frequency selection 2019-12-23 22:57:37 +01:00
Xavier Arteaga 11eafa8ab4 srsLTE: FFTW wisdom gets loaded and saved by default 2019-12-23 22:57:37 +01:00
Xavier Arteaga 892ece8cdd srsLTE: reduce number of SF for rf_zmq_test 2019-12-23 22:57:37 +01:00
Xavier Arteaga c92dce71b7 srsLTE: AGC only uses boundaries for requesting gain to Radio 2019-12-23 22:57:37 +01:00
Xavier Arteaga 097f492430 srsLTE: fix ZMQ RF module gain 2019-12-23 22:57:37 +01:00
Andre Puschmann 9e1b8bc95e disabling certain PHY DL tests that aren't working on ARM due to Turbo issues 2019-12-20 18:54:41 +01:00
Pedro Alvarez 6d4303cd94 Added option to force 32bit compilation (useful for debug). Fixed various warnings when compiling in a 32 bit arch. 2019-12-20 17:33:55 +01:00
Xavier Arteaga a96a7fe20a Removed srsue_phy from thread_test 2019-12-19 13:01:05 +01:00
Xavier Arteaga 089a5e21dc Label test that memcheck is excessively long 2019-12-19 13:01:05 +01:00