Ismael Gomez
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e18ba937dc
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Limit uplink signal normalization to avoid clipping
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2018-06-27 16:29:40 +02:00 |
Xavier Arteaga
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681b98ae50
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Added vector CFO
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2018-05-25 16:06:32 +02:00 |
Ismael Gomez
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384e0f8649
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Fixed UL interleaver (missing SIMD deinterleaver)
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2018-04-17 19:16:55 +02:00 |
David Rupprecht
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9d71bec7b6
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Unified include guards
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2018-03-31 19:04:04 +02:00 |
Andre Puschmann
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57e0c01fc4
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check max buffer length in hex print
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2018-03-07 21:23:57 +01:00 |
Ismael Gomez
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e16839d7a7
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Merge branch 'next' into 16bit_avx_viterbi
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2018-01-10 16:06:49 +01:00 |
yagoda
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d749ee66f4
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introducing 16 bit viterbi support
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2018-01-08 17:05:23 +00:00 |
Xavier Arteaga
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a01c5ea08f
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Fixes #119: channel estimation subframe averaging
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2018-01-08 12:05:31 +01:00 |
Ismael Gomez
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a3a1d268b7
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Improved CFO estimation/correction by filtering central 6 PRB. Cleaned ue_sync/sync/pss objects. Used const attr in vector and other objects
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2017-11-29 18:30:21 +01:00 |
yagoda
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38903de07c
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adding simd xor functionality
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2017-11-27 11:10:50 +00:00 |
Ismael Gomez
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dbae016b00
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Removed unused vector functions
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2017-10-02 18:16:03 +01:00 |
Xavier Arteaga
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9e5f999666
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Added more functions
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2017-09-28 11:04:26 +02:00 |
Xavier Arteaga
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c9f6bfccd4
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Refactored vector library with SIMD independent architecture inline functions test-benchmark
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2017-09-25 13:19:34 +02:00 |
Xavier Arteaga
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0947173fc1
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Merge branch 'next' into next_mimo
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2017-08-29 17:30:40 +02:00 |
Ismael Gomez
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616e18c570
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fixed PUCCH correlation estimator
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2017-08-24 15:16:13 +02:00 |
Xavier Arteaga
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48d508aeba
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Added srs_lte_cpy for aligned copy which improves a bit performance for aligned data
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2017-08-17 10:19:19 +02:00 |
Andre Puschmann
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d079d25b2c
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rename srslte folder and src subfolder
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2017-05-30 13:05:04 +02:00 |