2013-02-04 05:26:08 -08:00
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/*
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* Licensed under ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* SPC56ELxx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 1...15 Lowest...Highest.
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*/
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#define SPC56ELxx_MCUCONF
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/*
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* HAL driver system settings.
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*/
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2013-02-12 04:56:05 -08:00
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#define SPC5_NO_INIT FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC
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#define SPC5_FMPLL0_IDF_VALUE 5
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#define SPC5_FMPLL0_NDIV_VALUE 60
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC
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#define SPC5_FMPLL1_IDF_VALUE 5
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#define SPC5_FMPLL1_NDIV_VALUE 60
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#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_SYSCLK_DIVIDER_VALUE 1
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#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
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#define SPC5_MCONTROL_DIVIDER_VALUE 2
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#define SPC5_SWG_DIVIDER_VALUE 2
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#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1
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#define SPC5_FLEXRAY_DIVIDER_VALUE 2
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#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
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#define SPC5_FLEXCAN_DIVIDER_VALUE 2
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#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
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SPC5_ME_ME_RUN2 | \
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SPC5_ME_ME_RUN3 | \
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SPC5_ME_ME_HALT0 | \
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SPC5_ME_ME_STOP0)
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#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
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#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_FLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_FLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_FLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_FLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_FLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_FLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_FLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN_PC0_BITS 0
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#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_SAFE | \
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SPC5_ME_RUN_PC_DRUN | \
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SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
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SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_LP_PC0_BITS 0
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#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
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#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
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2013-02-04 05:26:08 -08:00
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/*
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* SERIAL driver system settings.
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*/
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