git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3097 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
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@ -2,15 +2,31 @@
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******************************************************************************
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* @file stm32f10x.h
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* @author MCD Application Team
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* @version V3.4.0
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* @date 10/15/2010
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* @version V3.5.0
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* @date 11-March-2011
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F10x Connectivity line,
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* High density, High density value line, Medium density,
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* Medium density Value line, Low density, Low density Value line
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* and XL-density devices.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The device used in the target application
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* - To use or not the peripheral’s drivers in application code(i.e.
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* code will be based on direct access to peripheral’s registers
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* rather than drivers API), this option is controlled by
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* "#define USE_STDPERIPH_DRIVER"
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* - To change few application-specific parameters such as the HSE
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* crystal frequency
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral’s registers hardware
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*
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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@ -19,7 +35,7 @@
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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@ -116,12 +132,14 @@
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/**
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* @brief STM32F10x Standard Peripheral Library version number
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*/
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
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#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
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| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
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| __STM32F10X_STDPERIPH_VERSION_SUB2)
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
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|(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
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|(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
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|(__STM32F10X_STDPERIPH_VERSION_RC))
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/**
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* @}
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@ -346,7 +364,6 @@ typedef enum IRQn
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TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
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TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
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TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
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FSMC_IRQn = 48, /*!< FSMC global Interrupt */
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TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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UART4_IRQn = 52, /*!< UART4 global Interrupt */
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@ -358,7 +375,7 @@ typedef enum IRQn
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DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
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DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
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DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
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mapped at postion 60 only if the MISC_REMAP bit in
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mapped at position 60 only if the MISC_REMAP bit in
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the AFIO_MAPR2 register is set) */
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#endif /* STM32F10X_HD_VL */
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@ -1006,7 +1023,7 @@ typedef struct
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__IO uint32_t MAPR2;
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} AFIO_TypeDef;
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/**
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* @brief Inter-integrated Circuit Interface
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* @brief Inter Integrated Circuit Interface
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*/
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typedef struct
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@ -1954,7 +1971,7 @@ typedef struct
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
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#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
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#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
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#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
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#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
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#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
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#endif /* STM32F10X_LD && STM32F10X_LD_VL */
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@ -2670,7 +2687,7 @@ typedef struct
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#define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
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/*!< PTP_PPS_REMAP configuration */
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#define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
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#define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
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#endif
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/***************** Bit definition for AFIO_EXTICR1 register *****************/
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@ -3217,7 +3234,7 @@ typedef struct
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#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
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#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
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/*!< UFSR */
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#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
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#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
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#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
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#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
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#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
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#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
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/******************* Bit definition for SCB_HFSR register *******************/
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#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
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#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
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#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
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#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
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#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
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/******************* Bit definition for DMA_IFCR register *******************/
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#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
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#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
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#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
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#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
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#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
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@ -3475,7 +3492,7 @@ typedef struct
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/******************* Bit definition for DMA_CCR2 register *******************/
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#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
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#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
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#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
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#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
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#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
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#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
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#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
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#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
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#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
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#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
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#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
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#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
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@ -4153,7 +4170,7 @@ typedef struct
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#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
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#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
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#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
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#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */
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#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */
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/******************** Bit definition for CEC_CSR register ******************/
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#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
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#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
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#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
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#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
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#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
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#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
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#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
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#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
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#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
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#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
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#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
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#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
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#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
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#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */
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/******************* Bit definition for CAN_MSR register ********************/
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#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
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@ -8323,4 +8340,4 @@ typedef struct
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* @}
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*/
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/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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