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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4206 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2012-05-18 15:29:20 +00:00
parent c4a3d44d53
commit 01a811d27f
17 changed files with 710 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
boards/ST_STM32F0_DISCOVERY/board.h
View File

@ -129,8 +129,8 @@
PIN_PUDR_PULLUP(10) | \
PIN_PUDR_PULLUP(11) | \
PIN_PUDR_PULLUP(12) | \
PIN_PUDR_PULLUP(13) | \
PIN_PUDR_PULLUP(14) | \
PIN_PUDR_FLOATING(13) | \
PIN_PUDR_FLOATING(14) | \
PIN_PUDR_PULLUP(15))
#define VAL_GPIOA_ODR 0xFFFFFFFF
#define VAL_GPIOA_AFRL 0x00000000

2
boards/ST_STM32L_DISCOVERY/board.h
View File

@ -202,7 +202,7 @@
PIN_PUDR_PULLUP(12) | \
PIN_PUDR_PULLUP(13) | \
PIN_PUDR_FLOATING(14) | \
PIN_PUDR_FLOATING(15)))
PIN_PUDR_FLOATING(15))
#define VAL_GPIOC_ODR 0xFFFFFFFF
#define VAL_GPIOC_AFRL 0x00000000
#define VAL_GPIOC_AFRH 0x00000000

2
demos/ARMCM0-STM32F051-DISCOVERY/halconf.h
View File

@ -45,7 +45,7 @@
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL FALSE
#define HAL_USE_PAL TRUE
#endif
/**

33
demos/ARMCM0-STM32F051-DISCOVERY/main.c
View File

@ -23,18 +23,34 @@
#include "test.h"
/*
* This is a periodic thread that does absolutely nothing except increasing
* a seconds counter.
* Blue LED blinker thread, times are in milliseconds.
*/
static WORKING_AREA(waThread1, 128);
static msg_t Thread1(void *arg) {
static uint32_t seconds_counter;
(void)arg;
chRegSetThreadName("counter");
chRegSetThreadName("blinker1");
while (TRUE) {
chThdSleepMilliseconds(1000);
seconds_counter++;
palClearPad(GPIOC, GPIOC_LED4);
chThdSleepMilliseconds(500);
palSetPad(GPIOC, GPIOC_LED4);
chThdSleepMilliseconds(500);
}
}
/*
* Green LED blinker thread, times are in milliseconds.
*/
static WORKING_AREA(waThread2, 128);
static msg_t Thread2(void *arg) {
(void)arg;
chRegSetThreadName("blinker2");
while (TRUE) {
palClearPad(GPIOC, GPIOC_LED3);
chThdSleepMilliseconds(250);
palSetPad(GPIOC, GPIOC_LED3);
chThdSleepMilliseconds(250);
}
}
@ -54,9 +70,10 @@ int main(void) {
chSysInit();
/*
* Creates the example thread.
* Creates the blinker threads.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL);
/*
* Normal main() thread activity, in this demo it does nothing except
@ -65,7 +82,7 @@ int main(void) {
* driver 1.
*/
while (TRUE) {
/* if (palReadPad(GPIOA, GPIOA_BUTTON))
/*if (palReadPad(GPIOA, GPIOA_BUTTON))
TestThread(&SD1);*/
chThdSleepMilliseconds(500);
}

5
demos/ARMCM0-STM32F051-DISCOVERY/mcuconf.h
View File

@ -52,4 +52,9 @@
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_ADCSW STM32_ADCSW_HSI14
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI

8
os/hal/platforms/STM32/GPIOv2/pal_lld.c
View File

@ -35,6 +35,11 @@
#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
#define AHB_LPEN_MASK AHB_EN_MASK
#elif defined(STM32F0XX)
#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
RCC_AHBENR_GPIOFEN)
#elif defined(STM32F2XX)
#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
@ -99,6 +104,9 @@ void _pal_lld_init(const PALConfig *config) {
*/
#if defined(STM32L1XX_MD)
rccEnableAHB(AHB_EN_MASK, TRUE);
RCC->AHBLPENR |= AHB_LPEN_MASK;
#elif defined(STM32F0XX)
rccEnableAHB(AHB_EN_MASK, TRUE);
#elif defined(STM32F2XX) || defined(STM32F4XX)
RCC->AHB1ENR |= AHB1_EN_MASK;
RCC->AHB1LPENR |= AHB1_LPEN_MASK;

30
os/hal/platforms/STM32F0xx/hal_lld.c
View File

@ -95,7 +95,7 @@ void hal_lld_init(void) {
/* Reset of all peripherals.*/
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
rccResetAPB2(!RCC_APB2RSTR_DBGMCURST);
/* SysTick initialization using the system clock.*/
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
@ -104,13 +104,8 @@ void hal_lld_init(void) {
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
/* DWT cycle counter enable.*/
SCS_DEMCR |= SCS_DEMCR_TRCENA;
DWT_CTRL |= DWT_CTRL_CYCCNTENA;
/* PWR and BD clocks enabled.*/
rccEnablePWRInterface(FALSE);
rccEnableBKPInterface(FALSE);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
@ -152,6 +147,13 @@ void stm32_clock_init(void) {
; /* Waits until HSE is stable. */
#endif
#if STM32_HSE14_ENABLED
/* HSI14 activation.*/
RCC->CR2 |= RCC_CR2_HSI14ON;
while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
; /* Waits until HSI14 is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
@ -168,15 +170,9 @@ void stm32_clock_init(void) {
#endif
/* Clock settings.*/
#if STM32_HAS_USB
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE |
STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#else
RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#endif
RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW;
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS;
@ -188,6 +184,10 @@ void stm32_clock_init(void) {
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
; /* Waits selection complete. */
#endif
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
#endif /* !STM32_NO_INIT */
}

94
os/hal/platforms/STM32F0xx/hal_lld.h
View File

@ -527,10 +527,10 @@
#endif
/**
* @brief ADC clock source.
* @brief MCO pin setting.
*/
#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
#define STM32_ADCSW STM32_ADCSW_HSI14
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#endif
/**
@ -541,10 +541,31 @@
#endif
/**
* @brief MCO pin setting.
* @brief ADC clock source.
*/
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
#define STM32_ADCSW STM32_ADCSW_HSI14
#endif
/**
* @brief CEC clock source.
*/
#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
#define STM32_CECSW STM32_CECSW_HSI
#endif
/**
* @brief I2C1 clock source.
*/
#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
#define STM32_I2C1SW STM32_I2C1SW_HSI
#endif
/**
* @brief USART1 clock source.
*/
#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
#define STM32_USART1SW STM32_USART1SW_PCLK
#endif
/**
@ -569,6 +590,18 @@
#error "HSI not enabled, required by STM32_SW"
#endif
#if STM32_CECSW == STM32_CECSW_HSI
#error "HSI not enabled, required by STM32_CECSW"
#endif
#if STM32_I2C1SW == STM32_I2C1SW_HSI
#error "HSI not enabled, required by STM32_I2C1SW"
#endif
#if STM32_USART1SW == STM32_USART1SW_HSI
#error "HSI not enabled, required by STM32_USART1SW"
#endif
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
#endif
@ -651,6 +684,14 @@
#error "LSE frequency not defined"
#endif
#if STM32_CECSW == STM32_CECSW_LSE
#error "LSE not enabled, required by STM32_CECSW"
#endif
#if STM32_USART1SW == STM32_USART1SW_LSE
#error "LSE not enabled, required by STM32_USART1SW"
#endif
#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
#endif
@ -828,6 +869,43 @@
#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
#endif
/**
* @brief CEC frequency.
*/
#if STM32_CECSW == STM32_CECSW_HSI
#define STM32_CECCLK STM32_HSICLK
#elif STM32_CECSW == STM32_CECSW_LSE
#define STM32_CECCLK STM32_LSECLK
#else
#error "invalid source selected for CEC clock"
#endif
/**
* @brief I2C1 frequency.
*/
#if STM32_I2CSW == STM32_I2C1SW_HSI
#define STM32_I2C1CLK STM32_HSICLK
#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK
#define STM32_I2C1CLK STM32_SYSCLK
#else
#error "invalid source selected for I2C1 clock"
#endif
/**
* @brief USART1 frequency.
*/
#if STM32_USART1SW == STM32_USART1SW_PCLK
#define STM32_USART1CLK STM32_PCLK
#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
#define STM32_USART1CLK STM32_SYSCLK
#elif STM32_USART1SW == STM32_USART1SW_LSECLK
#define STM32_USART1CLK STM32_LSECLK
#elif STM32_USART1SW == STM32_USART1SW_HSICLK
#define STM32_USART1CLK STM32_HSICLK
#else
#error "invalid source selected for USART1 clock"
#endif
/**
* @brief Timers clock.
*/
@ -861,8 +939,8 @@
/*===========================================================================*/
/* STM32 DMA and RCC helpers.*/
/*#include "stm32_dma.h"
#include "stm32_rcc.h"*/
/*#include "stm32_dma.h"*/
#include "stm32_rcc.h"
#ifdef __cplusplus
extern "C" {

6
os/hal/platforms/STM32F0xx/platform.mk
View File

@ -1,5 +1,7 @@
# List of all the STM32F1xx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2

546
os/hal/platforms/STM32F0xx/stm32_rcc.h Normal file
View File

@ -0,0 +1,546 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file STM32F0xx/stm32_rcc.h
* @brief RCC helper driver header.
* @note This file requires definitions from the ST header file
* @p stm32f0xx.h.
*
* @addtogroup STM32F0xx_RCC
* @{
*/
#ifndef _STM32_RCC_
#define _STM32_RCC_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Generic RCC operations
* @{
*/
/**
* @brief Enables the clock of one or more peripheral on the APB1 bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask APB1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB1(mask, lp) { \
RCC->APB1ENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB1 bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask APB1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAPB1(mask, lp) { \
RCC->APB1ENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
*
* @api
*/
#define rccResetAPB1(mask) { \
RCC->APB1RSTR |= (mask); \
RCC->APB1RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB2 bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask APB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB2(mask, lp) { \
RCC->APB2ENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB2 bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask APB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAPB2(mask, lp) { \
RCC->APB2ENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccResetAPB2(mask) { \
RCC->APB2RSTR |= (mask); \
RCC->APB2RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask AHB peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAHB(mask, lp) { \
RCC->AHBENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask AHB peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAHB(mask, lp) { \
RCC->AHBENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define rccResetAHB(mask) { \
RCC->AHBRSTR |= (mask); \
RCC->AHBRSTR = 0; \
}
/** @} */
/**
* @name ADC peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the ADC1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
/**
* @brief Disables the ADC1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
/**
* @brief Resets the ADC1 peripheral.
*
* @api
*/
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */
/**
* @name PWR interface specific RCC operations
* @{
*/
/**
* @brief Enables the PWR interface clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Disables PWR interface clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Resets the PWR interface.
*
* @api
*/
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
/**
* @name DMA peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the DMA1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
/**
* @brief Disables the DMA1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
/**
* @brief Resets the DMA1 peripheral.
* @note Not supported in this family, does nothing.
*
* @api
*/
#define rccResetDMA1()
/** @} */
/**
* @name I2C peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the I2C1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
* @brief Disables the I2C1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
* @brief Resets the I2C1 peripheral.
*
* @api
*/
#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
/**
* @brief Enables the I2C2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
/**
* @brief Disables the I2C2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
/**
* @brief Resets the I2C2 peripheral.
*
* @api
*/
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
/** @} */
/**
* @name SPI peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the SPI1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
* @brief Disables the SPI1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
* @brief Resets the SPI1 peripheral.
*
* @api
*/
#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
/**
* @brief Enables the SPI2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
/**
* @brief Disables the SPI2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
/**
* @brief Resets the SPI2 peripheral.
*
* @api
*/
#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
/** @} */
/**
* @name TIM peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the TIM1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
/**
* @brief Disables the TIM1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
/**
* @brief Resets the TIM1 peripheral.
*
* @api
*/
#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
/**
* @brief Enables the TIM2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
* @brief Disables the TIM2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
* @brief Resets the TIM2 peripheral.
*
* @api
*/
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
/**
* @brief Enables the TIM3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
* @brief Disables the TIM3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
* @brief Resets the TIM3 peripheral.
*
* @api
*/
#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
/** @} */
/**
* @name USART/UART peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the USART1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
* @brief Disables the USART1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
* @brief Resets the USART1 peripheral.
*
* @api
*/
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
/**
* @brief Enables the USART2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
/**
* @brief Disables the USART2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
/**
* @brief Resets the USART2 peripheral.
*
* @api
*/
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _STM32_RCC_ */
/** @} */

4
os/hal/platforms/STM32F0xx/stm32f0xx.h
View File

@ -393,7 +393,8 @@ typedef struct
/**
* @brief General Purpose IO
*/
/* CHIBIOS FIX */
#if 0
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
@ -411,6 +412,7 @@ typedef struct
__IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
uint16_t RESERVED3; /*!< Reserved, 0x2A */
}GPIO_TypeDef;
#endif
/**
* @brief SysTem Configuration

3
os/hal/platforms/STM32F1xx/hal_lld.c
View File

@ -94,7 +94,8 @@ static void hal_lld_backup_domain_init(void) {
void hal_lld_init(void) {
/* Reset of all peripherals.*/
rccResetAPB(0xFFFFFFFF);
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
/* SysTick initialization using the system clock.*/
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;

10
os/hal/platforms/STM32F1xx/stm32_rcc.h
View File

@ -214,8 +214,7 @@
*
* @api
*/
#define rccEnableBKPInterface(lp) \
rccEnableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp)
#define rccEnableBKPInterface(lp) rccEnableAPB1((RCC_APB1ENR_BKPEN), lp)
/**
* @brief Disables BKP interface clock.
@ -225,8 +224,7 @@
*
* @api
*/
#define rccDisableBKPInterface(lp) \
rccDisableAPB1((RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN), lp)
#define rccDisableBKPInterface(lp) rccDisableAPB1((RCC_APB1ENR_BKPEN), lp)
/**
* @brief Resets the Backup Domain interface.
@ -265,14 +263,14 @@
*
* @api
*/
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Resets the PWR interface.
*
* @api
*/
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
/**

4
os/hal/platforms/STM32F2xx/stm32_rcc.h
View File

@ -412,14 +412,14 @@
*
* @api
*/
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Resets the PWR interface.
*
* @api
*/
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
/**

4
os/hal/platforms/STM32F4xx/stm32_rcc.h
View File

@ -412,14 +412,14 @@
*
* @api
*/
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Resets the PWR interface.
*
* @api
*/
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
/**

4
os/hal/platforms/STM32L1xx/stm32_rcc.h
View File

@ -258,14 +258,14 @@
*
* @api
*/
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Resets the PWR interface.
*
* @api
*/
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
/**

3
todo.txt
View File

@ -19,11 +19,12 @@ Within 2.5.x:
* FatFs 0.9x integration.
- CAN2 support and CAN driver test on STM32F2/F4.
X Streaming DAC/I2S driver model and STM32 implementation.
X STM32F0 support.
- Unified LPC1xxx HAL.
- LPC11xx and LPC13xx HALs merged in the unified one.
- LPC17xx support.
- NUC120 support.
- STM32F0 support.
- Create a null device driver implementing a stream interface.
- Add USARTs support to the STM32 SPI driver.
- Add option to use another counter instead of the systick counter into the
trace buffer.