diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
index 2c5d0448d..71357a46e 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc
@@ -168,15 +168,6 @@
 /* P output, if present.                                                     */
 /*---------------------------------------------------------------------------*/
 #if STM32_PLL_HAS_P || defined(__DOXYGEN__)
-/**
- * @brief   PLL P output clock frequency.
- */
-#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
-#define STM32_PLL_P_CLKOUT          (STM32_PLLVCO / STM32_PLLP_VALUE)
-#else
-#define STM32_PLL_P_CLKOUT          (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
-#endif
-
 /**
  * @brief   STM32_PLLP field.
  */
@@ -202,6 +193,15 @@
 #error "invalid STM32_PLLPDIV_VALUE value specified"
 #endif
 
+/**
+ * @brief   PLL P output clock frequency.
+ */
+#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
+#define STM32_PLL_P_CLKOUT          (STM32_PLLVCO / STM32_PLLP_VALUE)
+#else
+#define STM32_PLL_P_CLKOUT          (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
+#endif
+
 /*
  * PLL-P output frequency range check.
  */
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
index c2fcc5d7a..2fa09fa2f 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc
@@ -169,15 +169,6 @@
 /* P output, if present.                                                     */
 /*---------------------------------------------------------------------------*/
 #if STM32_PLLSAI1_HAS_P || defined(__DOXYGEN__)
-/**
- * @brief   PLLSAI1 P output clock frequency.
- */
-#if (STM32_PLLSAI1PDIV_VALUE == 0) || defined(__DOXYGEN__)
-#define STM32_PLLSAI1_P_CLKOUT      (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
-#else
-#define STM32_PLLSAI1_P_CLKOUT      (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE)
-#endif
-
 /**
  * @brief   STM32_PLLSAI1P field.
  */
@@ -191,6 +182,25 @@
 #error "invalid STM32_PLLSAI1P_VALUE value specified"
 #endif
 
+/**
+ * @brief   STM32_PLLSAI1PDIV field.
+ */
+#if ((STM32_PLLSAI1PDIV_VALUE != 1) && (STM32_PLLSAI1PDIV_VALUE <= 31)) ||  \
+    defined(__DOXYGEN__)
+#define STM32_PLLSAI1PDIV           (STM32_PLLSAI1PDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLSAI1PDIV_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLLSAI1 P output clock frequency.
+ */
+#if (STM32_PLLSAI1PDIV_VALUE == 0) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1_P_CLKOUT      (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
+#else
+#define STM32_PLLSAI1_P_CLKOUT      (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE)
+#endif
+
 /*
  * PLLSAI1-P output frequency range check.
  */
@@ -306,7 +316,7 @@ static inline void pllsai1_init(void) {
                      STM32_PLLSAI1REN  | STM32_PLLSAI1Q   |
                      STM32_PLLSAI1QEN  | STM32_PLLSAI1P   |
                      STM32_PLLSAI1PEN  | STM32_PLLSAI1N   |
-                     STM32_PLLSAI1M    | STM32_PLLSAI1SRC;
+                     STM32_PLLSAI1M;
   RCC->CR |= RCC_CR_PLLSAI1ON;
 
   /* Waiting for PLL lock.*/
diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
index 727389c49..d4ad04c5c 100644
--- a/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
+++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc
@@ -169,15 +169,6 @@
 /* P output, if present.                                                     */
 /*---------------------------------------------------------------------------*/
 #if STM32_PLLSAI2_HAS_P || defined(__DOXYGEN__)
-/**
- * @brief   PLLSAI2 P output clock frequency.
- */
-#if (STM32_PLLSAI2PDIV_VALUE == 0) || defined(__DOXYGEN__)
-#define STM32_PLLSAI2_P_CLKOUT      (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
-#else
-#define STM32_PLLSAI2_P_CLKOUT      (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE)
-#endif
-
 /**
  * @brief   STM32_PLLSAI2P field.
  */
@@ -191,6 +182,25 @@
 #error "invalid STM32_PLLSAI2P_VALUE value specified"
 #endif
 
+/**
+ * @brief   STM32_PLLSAI2PDIV field.
+ */
+#if ((STM32_PLLSAI2PDIV_VALUE != 1) && (STM32_PLLSAI2PDIV_VALUE <= 31)) ||  \
+    defined(__DOXYGEN__)
+#define STM32_PLLSAI2PDIV           (STM32_PLLSAI2PDIV_VALUE << 27)
+#else
+#error "invalid STM32_PLLSAI2PDIV_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLLSAI2 P output clock frequency.
+ */
+#if (STM32_PLLSAI2PDIV_VALUE == 0) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2_P_CLKOUT      (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
+#else
+#define STM32_PLLSAI2_P_CLKOUT      (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE)
+#endif
+
 /*
  * PLLSAI2-P output frequency range check.
  */
@@ -306,7 +316,7 @@ static inline void pllsai2_init(void) {
                      STM32_PLLSAI2REN  | STM32_PLLSAI2Q   |
                      STM32_PLLSAI2QEN  | STM32_PLLSAI2P   |
                      STM32_PLLSAI2PEN  | STM32_PLLSAI2N   |
-                     STM32_PLLSAI2M    | STM32_PLLSAI2SRC;
+                     STM32_PLLSAI2M;
   RCC->CR |= RCC_CR_PLLSAI2ON;
 
   /* Waiting for PLL lock.*/