git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5765 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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c16062e326
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036f60f497
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@ -47,8 +47,12 @@
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#define SPC5_DSPI2_RX_DMA_DEV_ID 15
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#define SPC5_DSPI1_EOQF_HANDLER vector132
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#define SPC5_DSPI1_EOQF_NUMBER 132
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#define SPC5_DSPI1_TFFF_HANDLER vector133
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#define SPC5_DSPI1_TFFF_NUMBER 133
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#define SPC5_DSPI2_EOQF_HANDLER vector137
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#define SPC5_DSPI2_EOQF_NUMBER 137
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#define SPC5_DSPI2_TFFF_HANDLER vector138
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#define SPC5_DSPI2_TFFF_NUMBER 138
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#define SPC5_DSPI1_ENABLE_CLOCK()
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#define SPC5_DSPI1_DISABLE_CLOCK()
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#define SPC5_DSPI2_ENABLE_CLOCK()
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@ -29,6 +29,7 @@
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/* Some forward declarations.*/
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static void spi_serve_rx_irq(edma_channel_t channel, void *p);
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static void spi_serve_tx_irq(edma_channel_t channel, void *p);
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static void spi_serve_dma_error_irq(edma_channel_t channel,
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void *p,
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uint32_t esr);
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@ -109,7 +110,7 @@ static const edma_channel_config_t spi_dspi0_tx1_dma_config = {
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*/
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static const edma_channel_config_t spi_dspi0_tx2_dma_config = {
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SPC5_DSPI0_TX2_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
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NULL, spi_serve_dma_error_irq, &SPID1
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spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1
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};
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/**
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@ -135,7 +136,7 @@ static const edma_channel_config_t spi_dspi1_tx1_dma_config = {
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*/
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static const edma_channel_config_t spi_dspi1_tx2_dma_config = {
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SPC5_DSPI1_TX2_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
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NULL, spi_serve_dma_error_irq, &SPID2
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spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2
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};
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/**
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@ -161,7 +162,7 @@ static const edma_channel_config_t spi_dspi2_tx1_dma_config = {
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*/
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static const edma_channel_config_t spi_dspi2_tx2_dma_config = {
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SPC5_DSPI2_TX2_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
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NULL, spi_serve_dma_error_irq, &SPID3
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spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3
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};
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/**
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@ -187,7 +188,7 @@ static const edma_channel_config_t spi_dspi3_tx1_dma_config = {
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*/
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static const edma_channel_config_t spi_dspi3_tx2_dma_config = {
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SPC5_DSPI3_TX2_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
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NULL, spi_serve_dma_error_irq, &SPID4
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spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4
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};
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/**
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@ -256,7 +257,7 @@ static void spi_start_dma_rx16(SPIDriver *spip,
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n, /* iter. */
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0, /* slast, no source adjust. */
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0, /* dlast. */
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EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
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EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
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edmaChannelStart(spip->rx_channel);
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}
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@ -275,25 +276,25 @@ static void spi_start_dma_tx8(SPIDriver *spip,
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const uint8_t *txbuf) {
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/* Preparing the TX intermediate buffer with the fixed part.*/
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spip->tx_intbuf = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
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spip->tx_intbuf = spip->config->pushr;
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/* The first frame is pushed by the CPU, then the DMA is activated to
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send the following frames. This should reduce latency on the operation
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start.*/
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spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf++;
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spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf;
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/* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
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edmaChannelSetupLinked(
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spip->tx1_channel, /* channel. */
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spip->tx2_channel, /* linkch. */
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txbuf, /* src. */
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txbuf + 1, /* src. */
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((const uint8_t *)&spip->tx_intbuf) + 3, /* dst. */
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1, /* soff, advance by 1. */
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0, /* doff, do not advance. */
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0, /* ssize, 8 bits transfers. */
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0, /* dsize, 8 bits transfers. */
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1, /* nbytes, always one. */
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n - 1, /* iter. */
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n - 2, /* iter. */
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0, /* slast, no source adjust. */
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0, /* dlast, no dest.adjust. */
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EDMA_TCD_MODE_DREQ); /* mode. */
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@ -307,13 +308,18 @@ static void spi_start_dma_tx8(SPIDriver *spip,
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2, /* ssize, 32 bits transfers.*/
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2, /* dsize, 32 bits transfers.*/
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4, /* nbytes, always four. */
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n - 1, /* iter. */
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n - 2, /* iter. */
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0, /* slast, no source adjust. */
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0, /* dlast, no dest.adjust. */
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EDMA_TCD_MODE_DREQ); /* mode. */
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EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
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edmaChannelStart(spip->tx1_channel);
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/* The last frame will be pushed by the TX DMA operation completion
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callback.*/
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spip->tx_last = txbuf[n - 1];
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/* Starting TX DMA channels.*/
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edmaChannelStart(spip->tx2_channel);
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edmaChannelStart(spip->tx1_channel);
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}
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/**
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@ -330,28 +336,28 @@ static void spi_start_dma_tx16(SPIDriver *spip,
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const uint16_t *txbuf) {
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/* Preparing the TX intermediate buffer with the fixed part.*/
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spip->tx_intbuf = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
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spip->tx_intbuf = spip->config->pushr;
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/* The first frame is pushed by the CPU, then the DMA is activated to
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send the following frames. This should reduce latency on the operation
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start.*/
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spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf++;
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spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf;
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/* Setting up TX1 DMA TCD parameters for 16 bits transfers.*/
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edmaChannelSetup(spip->tx1_channel, /* channel. */
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txbuf, /* src. */
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/* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
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edmaChannelSetupLinked(
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spip->tx1_channel, /* channel. */
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spip->tx2_channel, /* linkch. */
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txbuf + 1, /* src. */
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((const uint8_t *)&spip->tx_intbuf) + 2, /* dst. */
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1, /* soff, advance by 1. */
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0, /* doff, do not advance. */
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1, /* ssize, 16 bits transfers.*/
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1, /* dsize, 16 bits transfers.*/
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2, /* nbytes, always two. */
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n - 1, /* iter. */
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1, /* nbytes, always one. */
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n - 2, /* iter. */
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0, /* slast, no source adjust. */
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0, /* dlast, no dest.adjust. */
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EDMA_TCD_MODE_DREQ |
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EDMA_TCD_MODE_MELINK |
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EDMA_TCD_MODE_MLINKCH(spip->tx2_channel)); /* mode. */
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EDMA_TCD_MODE_DREQ); /* mode. */
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/* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
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edmaChannelSetup(spip->tx2_channel, /* channel. */
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@ -362,13 +368,18 @@ static void spi_start_dma_tx16(SPIDriver *spip,
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2, /* ssize, 32 bits transfers.*/
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2, /* dsize, 32 bits transfers.*/
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4, /* nbytes, always four. */
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n - 1, /* iter. */
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n - 2, /* iter. */
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0, /* slast, no source adjust. */
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0, /* dlast, no dest.adjust. */
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EDMA_TCD_MODE_DREQ); /* mode. */
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EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
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edmaChannelStart(spip->tx1_channel);
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/* The last frame will be pushed by the TX DMA operation completion
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callback.*/
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spip->tx_last = txbuf[n - 1];
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/* Starting TX DMA channels.*/
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edmaChannelStart(spip->tx2_channel);
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edmaChannelStart(spip->tx1_channel);
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}
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/**
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@ -383,11 +394,12 @@ static void spi_start_dma_tx16(SPIDriver *spip,
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static void spi_tx_prefill8(SPIDriver *spip,
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size_t n,
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const uint8_t *txbuf) {
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uint32_t cmd = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
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uint32_t cmd = spip->config->pushr;
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do {
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if (--n == 0) {
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spip->dspi->PUSHR.R = SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf;
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spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf) &
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~SPC5_PUSHR_CONT;
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break;
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}
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spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
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@ -407,7 +419,7 @@ static void spi_tx_prefill8(SPIDriver *spip,
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static void spi_tx_prefill16(SPIDriver *spip,
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size_t n,
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const uint16_t *txbuf) {
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uint32_t cmd = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
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uint32_t cmd = spip->config->pushr;
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do {
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if (--n == 0) {
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@ -419,6 +431,14 @@ static void spi_tx_prefill16(SPIDriver *spip,
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} while (TRUE);
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}
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/**
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* @brief Shared RX DMA events service routine.
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*
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* @param[in] channel the channel number
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* @param[in] p parameter for the registered function
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*
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* @notapi
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*/
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static void spi_serve_rx_irq(edma_channel_t channel, void *p) {
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SPIDriver *spip = (SPIDriver *)p;
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@ -426,13 +446,48 @@ static void spi_serve_rx_irq(edma_channel_t channel, void *p) {
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/* Stops the DSPI and clears the queues.*/
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spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT |
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SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
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SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF |
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spip->config->mcr;
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/* Portable SPI ISR code defined in the high level driver, note, it is
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a macro.*/
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_spi_isr_code(spip);
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}
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/**
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* @brief Shared TX2 DMA events service routine.
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*
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* @param[in] channel the channel number
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* @param[in] p parameter for the registered function
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*
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* @notapi
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*/
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static void spi_serve_tx_irq(edma_channel_t channel, void *p) {
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SPIDriver *spip = (SPIDriver *)p;
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(void)channel;
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/* If the TX FIFO is full then the push of the last frame is delagated to
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an interrupt handler else it is performed immediately. Both conditions
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can be true depending on the SPI speed and ISR latency.*/
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if (spip->dspi->SR.B.TFFF) {
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spip->dspi->PUSHR.R = (spip->config->pushr | spip->tx_last | SPC5_PUSHR_EOQ) &
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~SPC5_PUSHR_CONT;
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}
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else {
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spip->dspi->RSER.B.TFFFDIRS = 0;
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}
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}
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/**
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* @brief Shared ISR for DMA error events.
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*
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* @param[in] channel the channel number
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* @param[in] p parameter for the registered function
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* @param[in] esr content of the ESR register
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*
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* @notapi
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*/
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static void spi_serve_dma_error_irq(edma_channel_t channel,
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void *p,
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uint32_t esr) {
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@ -456,6 +511,122 @@ static void spi_serve_dma_error_irq(edma_channel_t channel,
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
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#if !defined(SPC5_DSPI0_TFFF_HANDLER)
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#error "SPC5_DSPI0_TFFF_HANDLER not defined"
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#endif
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/**
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* @brief DSPI0 TFFF interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(SPC5_DSPI0_TFFF_HANDLER) {
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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/* Interrupt served and back to DMA mode.*/
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SPC5_DSPI0.RSER.B.TFFFDIRS = 1;
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SPC5_DSPI0.SR.B.TFFF = 1;
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/* Pushing last frame.*/
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SPC5_DSPI0.PUSHR.R = (SPID1.config->pushr | SPID1.tx_last | SPC5_PUSHR_EOQ) &
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~SPC5_PUSHR_CONT;
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chSysUnlockFromIsr();
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CH_IRQ_EPILOGUE();
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}
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#endif /* SPC5_SPI_USE_DSPI0 */
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#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
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#if !defined(SPC5_DSPI1_TFFF_HANDLER)
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#error "SPC5_DSPI1_TFFF_HANDLER not defined"
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#endif
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/**
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* @brief DSPI1 TFFF interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(SPC5_DSPI1_TFFF_HANDLER) {
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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/* Interrupt served and back to DMA mode.*/
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SPC5_DSPI1.RSER.B.TFFFDIRS = 1;
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SPC5_DSPI1.SR.B.TFFF = 1;
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/* Pushing last frame.*/
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SPC5_DSPI1.PUSHR.R = (SPID2.config->pushr | SPID2.tx_last | SPC5_PUSHR_EOQ) &
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~SPC5_PUSHR_CONT;
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chSysUnlockFromIsr();
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CH_IRQ_EPILOGUE();
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}
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#endif /* SPC5_SPI_USE_DSPI1 */
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#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
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#if !defined(SPC5_DSPI2_TFFF_HANDLER)
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#error "SPC5_DSPI2_TFFF_HANDLER not defined"
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#endif
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/**
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* @brief DSPI2 TFFF interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(SPC5_DSPI2_TFFF_HANDLER) {
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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/* Interrupt served and back to DMA mode.*/
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SPC5_DSPI2.RSER.B.TFFFDIRS = 1;
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SPC5_DSPI2.SR.B.TFFF = 1;
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/* Pushing last frame.*/
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SPC5_DSPI2.PUSHR.R = (SPID3.config->pushr | SPID3.tx_last | SPC5_PUSHR_EOQ) &
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~SPC5_PUSHR_CONT;
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chSysUnlockFromIsr();
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CH_IRQ_EPILOGUE();
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}
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#endif /* SPC5_SPI_USE_DSPI2 */
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#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
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#if !defined(SPC5_DSPI3_TFFF_HANDLER)
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#error "SPC5_DSPI3_TFFF_HANDLER not defined"
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#endif
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/**
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* @brief DSPI3 TFFF interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(SPC5_DSPI3_TFFF_HANDLER) {
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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/* Interrupt served and back to DMA mode.*/
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SPC5_DSPI3.RSER.B.TFFFDIRS = 1;
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SPC5_DSPI3.SR.B.TFFF = 1;
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/* Pushing last frame.*/
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SPC5_DSPI3.PUSHR.R = (SPID4.config->pushr | SPID4.tx_last | SPC5_PUSHR_EOQ) &
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~SPC5_PUSHR_CONT;
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chSysUnlockFromIsr();
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CH_IRQ_EPILOGUE();
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}
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#endif /* SPC5_SPI_USE_DSPI3 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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@ -474,6 +645,7 @@ void spi_lld_init(void) {
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SPID1.tx1_channel = EDMA_ERROR;
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SPID1.tx2_channel = EDMA_ERROR;
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SPID1.rx_channel = EDMA_ERROR;
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INTC.PSR[SPC5_DSPI0_TFFF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO;
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#endif /* SPC5_SPI_USE_DSPI0 */
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#if SPC5_SPI_USE_DSPI1
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@ -483,6 +655,7 @@ void spi_lld_init(void) {
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SPID2.tx1_channel = EDMA_ERROR;
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SPID2.tx2_channel = EDMA_ERROR;
|
||||
SPID2.rx_channel = EDMA_ERROR;
|
||||
INTC.PSR[SPC5_DSPI1_TFFF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO;
|
||||
#endif /* SPC5_SPI_USE_DSPI1 */
|
||||
|
||||
#if SPC5_SPI_USE_DSPI2
|
||||
|
@ -492,6 +665,7 @@ void spi_lld_init(void) {
|
|||
SPID3.tx1_channel = EDMA_ERROR;
|
||||
SPID3.tx2_channel = EDMA_ERROR;
|
||||
SPID3.rx_channel = EDMA_ERROR;
|
||||
INTC.PSR[SPC5_DSPI2_TFFF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO;
|
||||
#endif /* SPC5_SPI_USE_DSPI2 */
|
||||
|
||||
#if SPC5_SPI_USE_DSPI03
|
||||
|
@ -501,6 +675,7 @@ void spi_lld_init(void) {
|
|||
SPID4.tx1_channel = EDMA_ERROR;
|
||||
SPID4.tx2_channel = EDMA_ERROR;
|
||||
SPID4.rx_channel = EDMA_ERROR;
|
||||
INTC.PSR[SPC5_DSPI3_TFFF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO;
|
||||
#endif /* SPC5_SPI_USE_DSPI3 */
|
||||
}
|
||||
|
||||
|
@ -513,6 +688,11 @@ void spi_lld_init(void) {
|
|||
*/
|
||||
void spi_lld_start(SPIDriver *spip) {
|
||||
|
||||
chDbgAssert((spip->config->pushr & DSPI_PUSHR_EXCLUDED_BITS) == 0,
|
||||
"spi_lld_start(), #1", "invalid PUSHR bits specified");
|
||||
chDbgAssert((spip->config->mcr & DSPI_MCR_EXCLUDED_BITS) == 0,
|
||||
"spi_lld_start(), #2", "invalid PUSHR bits specified");
|
||||
|
||||
if (spip->state == SPI_STOP) {
|
||||
/* Enables the peripheral.*/
|
||||
|
||||
|
@ -553,12 +733,14 @@ void spi_lld_start(SPIDriver *spip) {
|
|||
#endif /* SPC5_SPI_USE_DSPI3 */
|
||||
|
||||
chDbgAssert((spip->tx1_channel != EDMA_ERROR) &&
|
||||
(spip->tx2_channel != EDMA_ERROR) &&
|
||||
(spip->rx_channel != EDMA_ERROR),
|
||||
"spi_lld_start(), #1", "channel cannot be allocated");
|
||||
"spi_lld_start(), #3", "channel cannot be allocated");
|
||||
}
|
||||
|
||||
/* Configures the peripheral.*/
|
||||
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT;
|
||||
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT |
|
||||
spip->config->mcr;
|
||||
spip->dspi->CTAR[0].R = spip->config->ctar0;
|
||||
spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
|
||||
SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
|
||||
|
@ -679,8 +861,7 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
|
|||
|
||||
/* Starting transfer.*/
|
||||
spip->dspi->SR.R = spip->dspi->SR.R;
|
||||
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS |
|
||||
(spip->config->mcr & ~DSPI_MCR_EXCLUDED_BITS);
|
||||
spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | spip->config->mcr;
|
||||
|
||||
/* DMAs require a different setup depending on the frame size.*/
|
||||
if (spip->dspi->CTAR[0].B.FMSZ < 8) {
|
||||
|
@ -692,11 +873,6 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
|
|||
the whole transmitted data is pushed here and the TX DMA is not
|
||||
activated.*/
|
||||
spi_tx_prefill8(spip, n, txbuf);
|
||||
/* uint8_t *p = rxbuf;
|
||||
*p++ = spip->dspi->POPR.R;
|
||||
*p++ = spip->dspi->POPR.R;
|
||||
*p++ = spip->dspi->POPR.R;
|
||||
*p++ = spip->dspi->POPR.R;*/
|
||||
}
|
||||
else {
|
||||
spi_start_dma_tx8(spip, n, txbuf);
|
||||
|
|
|
@ -301,6 +301,34 @@
|
|||
#if !defined(SPC5_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
|
||||
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DSPI0 DMA priority.
|
||||
*/
|
||||
#if !defined(SPC5_SPI_DSPI0_IRQ_PRIO) || defined(__DOXYGEN__)
|
||||
#define SPC5_SPI_DSPI0_IRQ_PRIO 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DSPI1 DMA priority.
|
||||
*/
|
||||
#if !defined(SPC5_SPI_DSPI1_IRQ_PRIO) || defined(__DOXYGEN__)
|
||||
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DSPI2 DMA priority.
|
||||
*/
|
||||
#if !defined(SPC5_SPI_DSPI2_IRQ_PRIO) || defined(__DOXYGEN__)
|
||||
#define SPC5_SPI_DSPI2_IRQ_PRIO 10
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief DSPI3 DMA priority.
|
||||
*/
|
||||
#if !defined(SPC5_SPI_DSPI3_IRQ_PRIO) || defined(__DOXYGEN__)
|
||||
#define SPC5_SPI_DSPI3_IRQ_PRIO 10
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
@ -432,6 +460,10 @@ struct SPIDriver {
|
|||
* @brief EDMA channel used for receive.
|
||||
*/
|
||||
edma_channel_t rx_channel;
|
||||
/**
|
||||
* @brief Last frame of a transmission sequence.
|
||||
*/
|
||||
uint32_t tx_last;
|
||||
/**
|
||||
* @brief TX intermediate buffer.
|
||||
* @note This field is written by the TX1 DMA channel and read by the
|
||||
|
|
|
@ -25,7 +25,8 @@ static const SPIConfig hs_spicfg = {
|
|||
0,
|
||||
0,
|
||||
SPC5_MCR_PCSIS0, /* MCR. */
|
||||
SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV128, /* CTAR0. */
|
||||
SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) |
|
||||
SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV128, /* CTAR0. */
|
||||
SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */
|
||||
};
|
||||
|
||||
|
@ -125,6 +126,7 @@ int main(void) {
|
|||
spiExchange(&SPID2, 4, txbuf, rxbuf);
|
||||
spiExchange(&SPID2, 4, txbuf, rxbuf);
|
||||
spiExchange(&SPID2, 4, txbuf, rxbuf);
|
||||
spiExchange(&SPID2, 32, txbuf, rxbuf);
|
||||
spiExchange(&SPID2, 512, txbuf, rxbuf);
|
||||
#if 0
|
||||
/*
|
||||
|
|
Loading…
Reference in New Issue