andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

More unfinished H7 work. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11172 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-12-23 10:21:25 +00:00
parent e6199d4b54
commit 03a27a2096
11 changed files with 3816 additions and 182 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
demos/STM32/RT-STM32H743I-NUCLEO144/Makefile
View File

@ -101,13 +101,13 @@ include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk
# HAL-OSAL files (optional).
#include $(CHIBIOS)/os/hal/hal.mk
#include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk
#include $(CHIBIOS)/os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk
#include $(CHIBIOS)/os/hal/osal/rt/osal.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI/board.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
# RTOS files (optional).
#include $(CHIBIOS)/os/rt/rt.mk
#include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).

2
demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h
View File

@ -146,7 +146,7 @@
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#define HAL_USE_SERIAL FALSE
#endif
/**

12
demos/STM32/RT-STM32H743I-NUCLEO144/main.c
View File

@ -14,12 +14,11 @@
limitations under the License.
*/
//#include "ch.h"
//#include "hal.h"
#include "ch.h"
#include "hal.h"
//#include "rt_test_root.h"
//#include "oslib_test_root.h"
#if 0
/*
* This is a periodic thread that does absolutely nothing except flashing
* a LED.
@ -36,14 +35,12 @@ static THD_FUNCTION(Thread1, arg) {
chThdSleepMilliseconds(500);
}
}
#endif
/*
* Application entry point.
*/
int main(void) {
#if 0
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
@ -63,13 +60,12 @@ int main(void) {
/*
* Activates the serial driver 1 using the driver default configuration.
*/
sdStart(&SD1, NULL);
// sdStart(&SD1, NULL);
/*
* Creates the example thread.
*/
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO+1, Thread1, NULL);
#endif
/*
* Normal main() thread activity, in this demo it does nothing except
@ -81,7 +77,7 @@ int main(void) {
test_execute((BaseSequentialStream *)&SD1, &rt_test_suite);
test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite);
}
chThdSleepMilliseconds(500);
#endif
chThdSleepMilliseconds(500);
}
}

81
demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
View File

@ -51,7 +51,7 @@
#define STM32_PWR_D3CR (PWR_D3CR_VOS_0)
/*
* Clock tree settings.
* Clock tree static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_HSI_ENABLED TRUE
@ -62,7 +62,6 @@
#define STM32_LSE_ENABLED TRUE
#define STM32_HSIDIV STM32_HSIDIV_DIV1
#define STM32_RTCPRE_VALUE 8
#define STM32_RTCSEL STM32_RTCSEL_LSE
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLL1_ENABLED TRUE
#define STM32_PLL1_DIVM_VALUE 4
@ -85,65 +84,29 @@
#define STM32_PLL3_DIVP_VALUE 2
#define STM32_PLL3_DIVQ_VALUE 8
#define STM32_PLL3_DIVR_VALUE 8
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CLK
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
#define STM32_MCO1PRE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#define STM32_MCO2PRE 4
/*
* Core clocks dynamic settings (can be changed at runtime).
* Reading STM32 Reference Manual is required.
*/
#define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_CSI_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 25
#define STM32_PLLN_VALUE 432
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSE
#define STM32_RTCPRE_VALUE 25
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_OFF
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLI2SDIVQ_VALUE 2
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVQ_VALUE 2
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
#define STM32_UART4SEL STM32_UART4SEL_PCLK1
#define STM32_UART5SEL STM32_UART5SEL_PCLK1
#define STM32_USART6SEL STM32_USART6SEL_PCLK2
#define STM32_UART7SEL STM32_UART7SEL_PCLK1
#define STM32_UART8SEL STM32_UART8SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*
* Peripherals clocks static settings.
* Reading STM32 Reference Manual is required.
*/
/*
* IRQ system settings.

266
os/hal/boards/ST_NUCLEO144_H743ZI/board.c Normal file
View File

@ -0,0 +1,266 @@
/*
ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#include "stm32_gpio.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
gpio_setup_t PFData;
#endif
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
gpio_setup_t PGData;
#endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
gpio_setup_t PHData;
#endif
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
gpio_setup_t PIData;
#endif
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_setup_t PJData;
#endif
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
gpio_setup_t PKData;
#endif
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB1(STM32_GPIO_EN_MASK);
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
#if STM32_HAS_GPIOG
gpio_init(GPIOG, &gpio_default_config.PGData);
#endif
#if STM32_HAS_GPIOH
gpio_init(GPIOH, &gpio_default_config.PHData);
#endif
#if STM32_HAS_GPIOI
gpio_init(GPIOI, &gpio_default_config.PIData);
#endif
#if STM32_HAS_GPIOJ
gpio_init(GPIOJ, &gpio_default_config.PJData);
#endif
#if STM32_HAS_GPIOK
gpio_init(GPIOK, &gpio_default_config.PKData);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
stm32_gpio_init();
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}

1862
os/hal/boards/ST_NUCLEO144_H743ZI/board.h Normal file
View File

File diff suppressed because it is too large Load Diff

9
os/hal/boards/ST_NUCLEO144_H743ZI/board.mk Normal file
View File

@ -0,0 +1,9 @@
# List of all the board related files.
BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

1459
os/hal/boards/ST_NUCLEO144_H743ZI/cfg/board.chcfg Normal file
View File

File diff suppressed because it is too large Load Diff

15
os/hal/boards/ST_NUCLEO144_H743ZI/cfg/board.fmpp Normal file
View File

@ -0,0 +1,15 @@
sourceRoot: ../../../../../tools/ftl/processors/boards/stm32h7xx/templates
outputRoot: ..
dataRoot: .
freemarkerLinks: {
lib: ../../../../../tools/ftl/libs
}
data : {
doc1:xml (
board.chcfg
{
}
)
}

279
os/hal/ports/STM32/STM32H7xx/hal_lld.h
View File

@ -210,12 +210,22 @@
*/
#define RCC_CR_HSIDIV_VALUE(n) ((n) << 3U)
#define RCC_CFGR_SW_VALUE(n) ((n) << 0U)
#define RCC_CFGR_RTCPRE_VALUE(n) ((n) << 8U)
#define RCC_CFGR_MCO1PRE_VALUE(n) ((n) << 18U)
#define RCC_CFGR_MCO1_VALUE(n) ((n) << 22U)
#define RCC_CFGR_MCO2PRE_VALUE(n) ((n) << 25U)
#define RCC_CFGR_MCO2_VALUE(n) ((n) << 29U)
#define RCC_D1CFGR_D1CPRE_VALUE(n) ((n) << RCC_D1CFGR_D1CPRE_Pos)
#define RCC_D1CFGR_D1HPRE_VALUE(n) ((n) << RCC_D1CFGR_D1HPRE_Pos)
#define RCC_D1CFGR_D1PPRE3_VALUE(n) ((n) << RCC_D1CFGR_D1PPRE_Pos)
#define RCC_D2CFGR_D2PPRE1_VALUE(n) ((n) << RCC_D2CFGR_D2PPRE1_Pos)
#define RCC_D2CFGR_D2PPRE2_VALUE(n) ((n) << RCC_D2CFGR_D2PPRE2_Pos)
#define RCC_D3CFGR_D3PPRE4_VALUE(n) ((n) << RCC_D3CFGR_D3PPRE_Pos)
#define RCC_PLLCKSELR_DIVM1_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM1_Pos)
#define RCC_PLLCKSELR_DIVM2_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM2_Pos)
#define RCC_PLLCKSELR_DIVM3_VALUE(n) ((n) << RCC_PLLCKSELR_DIVM3_Pos)
@ -241,36 +251,90 @@
#define RCC_PLL3FRACR_FRACN3_VALUE(n) ((n) << RCC_PLL3FRACR_FRACN3_Pos)
#define RCC_D1CCIPR_CKPERSEL_VALUE(n) ((n) << RCC_D1CCIPR_CKPERSEL_Pos)
#define RCC_BDCR_RTCSEL_VALUE(n) ((n) << RCC_BDCR_RTCSEL_Pos)
/** @} */
/**
* @name Configuration switches to be used in @p mcuconf.h
* @{
*/
#define STM32_HSIDIV_DIV1 RCC_CR_HSIDIV_VALUE(0)
#define STM32_HSIDIV_DIV2 RCC_CR_HSIDIV_VALUE(1)
#define STM32_HSIDIV_DIV4 RCC_CR_HSIDIV_VALUE(2)
#define STM32_HSIDIV_DIV8 RCC_CR_HSIDIV_VALUE(3)
#define STM32_SW_HSI_CK RCC_CFGR_SW_VALUE(0U)
#define STM32_SW_CSI_CK RCC_CFGR_SW_VALUE(1U)
#define STM32_SW_HSE_CK RCC_CFGR_SW_VALUE(2U)
#define STM32_SW_PLL1_P_CK RCC_CFGR_SW_VALUE(3U)
#define STM32_MCO1_HSI_CK RCC_CFGR_MCO1_VALUE(0U)
#define STM32_MCO1_LSE_CK RCC_CFGR_MCO1_VALUE(1U)
#define STM32_MCO1_HSE_CK RCC_CFGR_MCO1_VALUE(2U)
#define STM32_MCO1_PLL1_Q_CK RCC_CFGR_MCO1_VALUE(3U)
#define STM32_MCO1_HSI48_CK RCC_CFGR_MCO1_VALUE(4U)
#define STM32_D1CPRE_DIV1 RCC_D1CFGR_D1CPRE_VALUE(0U)
#define STM32_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_VALUE(8U)
#define STM32_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_VALUE(9U)
#define STM32_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_VALUE(10U)
#define STM32_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_VALUE(11U)
#define STM32_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_VALUE(12U)
#define STM32_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_VALUE(13U)
#define STM32_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_VALUE(14U)
#define STM32_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_VALUE(15U)
#define STM32_MCO2_SYS_CK RCC_CFGR_MCO2_VALUE(0U)
#define STM32_MCO2_PLL2_Q_CK RCC_CFGR_MCO2_VALUE(1U)
#define STM32_MCO2_HSE_CK RCC_CFGR_MCO2_VALUE(2U)
#define STM32_MCO2_PLL1_P_CK RCC_CFGR_MCO2_VALUE(3U)
#define STM32_MCO2_CSI_CK RCC_CFGR_MCO2_VALUE(4U)
#define STM32_MCO2_LSI_CK RCC_CFGR_MCO2_VALUE(5U)
#define STM32_D1HPRE_DIV1 RCC_D1CFGR_D1HPRE_VALUE(0U)
#define STM32_D1HPRE_DIV2 RCC_D1CFGR_D1HPRE_VALUE(8U)
#define STM32_D1HPRE_DIV4 RCC_D1CFGR_D1HPRE_VALUE(9U)
#define STM32_D1HPRE_DIV8 RCC_D1CFGR_D1HPRE_VALUE(10U)
#define STM32_D1HPRE_DIV16 RCC_D1CFGR_D1HPRE_VALUE(11U)
#define STM32_D1HPRE_DIV64 RCC_D1CFGR_D1HPRE_VALUE(12U)
#define STM32_D1HPRE_DIV128 RCC_D1CFGR_D1HPRE_VALUE(13U)
#define STM32_D1HPRE_DIV256 RCC_D1CFGR_D1HPRE_VALUE(14U)
#define STM32_D1HPRE_DIV512 RCC_D1CFGR_D1HPRE_VALUE(15U)
#define STM32_D1PPRE3_DIV1 RCC_D1CFGR_D1PPRE3_VALUE(0U)
#define STM32_D1PPRE3_DIV2 RCC_D1CFGR_D1PPRE3_VALUE(4U)
#define STM32_D1PPRE3_DIV4 RCC_D1CFGR_D1PPRE3_VALUE(5U)
#define STM32_D1PPRE3_DIV8 RCC_D1CFGR_D1PPRE3_VALUE(6U)
#define STM32_D1PPRE3_DIV16 RCC_D1CFGR_D1PPRE3_VALUE(7U)
#define STM32_D2PPRE1_DIV1 RCC_D2CFGR_D2PPRE1_VALUE(0U)
#define STM32_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_VALUE(4U)
#define STM32_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_VALUE(5U)
#define STM32_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_VALUE(6U)
#define STM32_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_VALUE(7U)
#define STM32_D2PPRE2_DIV1 RCC_D2CFGR_D2PPRE2_VALUE(0U)
#define STM32_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_VALUE(4U)
#define STM32_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_VALUE(5U)
#define STM32_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_VALUE(6U)
#define STM32_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_VALUE(7U)
#define STM32_D3PPRE4_DIV1 RCC_D1CFGR_D3PPRE4_VALUE(0U)
#define STM32_D3PPRE4_DIV2 RCC_D1CFGR_D3PPRE4_VALUE(4U)
#define STM32_D3PPRE4_DIV4 RCC_D1CFGR_D3PPRE4_VALUE(5U)
#define STM32_D3PPRE4_DIV8 RCC_D1CFGR_D3PPRE4_VALUE(6U)
#define STM32_D3PPRE4_DIV16 RCC_D1CFGR_D3PPRE4_VALUE(7U)
#define STM32_HSIDIV_DIV1 RCC_CR_HSIDIV_VALUE(0U)
#define STM32_HSIDIV_DIV2 RCC_CR_HSIDIV_VALUE(1U)
#define STM32_HSIDIV_DIV4 RCC_CR_HSIDIV_VALUE(2U)
#define STM32_HSIDIV_DIV8 RCC_CR_HSIDIV_VALUE(3U)
#define STM32_MCO1SEL_HSI_CK RCC_CFGR_MCO1_VALUE(0U)
#define STM32_MCO1SEL_LSE_CK RCC_CFGR_MCO1_VALUE(1U)
#define STM32_MCO1SEL_HSE_CK RCC_CFGR_MCO1_VALUE(2U)
#define STM32_MCO1SEL_PLL1_Q_CK RCC_CFGR_MCO1_VALUE(3U)
#define STM32_MCO1SEL_HSI48_CK RCC_CFGR_MCO1_VALUE(4U)
#define STM32_MCO2SEL_SYS_CK RCC_CFGR_MCO2_VALUE(0U)
#define STM32_MCO2SEL_PLL2_Q_CK RCC_CFGR_MCO2_VALUE(1U)
#define STM32_MCO2SEL_HSE_CK RCC_CFGR_MCO2_VALUE(2U)
#define STM32_MCO2SEL_PLL1_P_CK RCC_CFGR_MCO2_VALUE(3U)
#define STM32_MCO2SEL_CSI_CK RCC_CFGR_MCO2_VALUE(4U)
#define STM32_MCO2SEL_LSI_CK RCC_CFGR_MCO2_VALUE(5U)
#define STM32_RTCSEL_NOCLK RCC_BDCR_RTCSEL_VALUE(0U)
#define STM32_RTCSEL_LSE RCC_BDCR_RTCSEL_VALUE(1U)
#define STM32_RTCSEL_LSI RCC_BDCR_RTCSEL_VALUE(2U)
#define STM32_RTCSEL_HSEDIV RCC_BDCR_RTCSEL_VALUE(3U)
#define STM32_RTCSEL_LSE_CK RCC_BDCR_RTCSEL_VALUE(1U)
#define STM32_RTCSEL_LSI_CK RCC_BDCR_RTCSEL_VALUE(2U)
#define STM32_RTCSEL_HSE_1M_CK RCC_BDCR_RTCSEL_VALUE(3U)
#define STM32_CKPERSEL_HSI_KER_CLK RCC_D1CCIPR_CKPERSEL_VALUE(0U)
#define STM32_CKPERSEL_CSI_KER_CLK RCC_D1CCIPR_CKPERSEL_VALUE(1U)
#define STM32_CKPERSEL_HSE_CLK RCC_D1CCIPR_CKPERSEL_VALUE(2U)
/** @} */
/*===========================================================================*/
@ -387,13 +451,6 @@
#define STM32_RTCPRE_VALUE 8
#endif
/**
* @brief RTC clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSE
#endif
/**
* @brief Clock source for all PLLs.
*/
@ -410,6 +467,7 @@
/**
* @brief PLL1 DIVM divider.
* @note The allowed values are 1..63.
*/
#if !defined(STM32_PLL1_DIVM_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL1_DIVM_VALUE 4
@ -417,6 +475,7 @@
/**
* @brief PLL1 DIVN multiplier.
* @note The allowed values are 4..512.
*/
#if !defined(STM32_PLL1_DIVN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL1_DIVN_VALUE 400
@ -424,6 +483,7 @@
/**
* @brief PLL1 FRACN multiplier, zero if no fractional part.
* @note The allowed values are 0..8191.
*/
#if !defined(STM32_PLL1_FRACN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL1_FRACN_VALUE 0
@ -431,6 +491,7 @@
/**
* @brief PLL1 DIVP divider.
* @note The allowed values are 2..128, odd values not allowed.
*/
#if !defined(STM32_PLL1_DIVP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL1_DIVP_VALUE 2
@ -438,6 +499,7 @@
/**
* @brief PLL1 DIVQ divider.
* @note The allowed values are 1..128.
*/
#if !defined(STM32_PLL1_DIVQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL1_DIVQ_VALUE 8
@ -445,6 +507,7 @@
/**
* @brief PLL1 DIVR divider.
* @note The allowed values are 1..128.
*/
#if !defined(STM32_PLL1_DIVR_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL1_DIVR_VALUE 8
@ -459,6 +522,7 @@
/**
* @brief PLL2 DIVM divider.
* @note The allowed values are 1..63.
*/
#if !defined(STM32_PLL2_DIVM_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL2_DIVM_VALUE 4
@ -466,6 +530,7 @@
/**
* @brief PLL2 DIVN multiplier.
* @note The allowed values are 4..512.
*/
#if !defined(STM32_PLL2_DIVN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL2_DIVN_VALUE 400
@ -473,6 +538,7 @@
/**
* @brief PLL2 FRACN multiplier, zero if no fractional part.
* @note The allowed values are 0..8191.
*/
#if !defined(STM32_PLL2_FRACN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL2_FRACN_VALUE 0
@ -480,6 +546,7 @@
/**
* @brief PLL2 DIVP divider.
* @note The allowed values are 2..128, odd values not allowed.
*/
#if !defined(STM32_PLL2_DIVP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL2_DIVP_VALUE 2
@ -487,6 +554,7 @@
/**
* @brief PLL2 DIVQ divider.
* @note The allowed values are 1..128.
*/
#if !defined(STM32_PLL2_DIVQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL2_DIVQ_VALUE 8
@ -494,6 +562,7 @@
/**
* @brief PLL2 DIVR divider.
* @note The allowed values are 1..128.
*/
#if !defined(STM32_PLL2_DIVR_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL2_DIVR_VALUE 8
@ -508,6 +577,7 @@
/**
* @brief PLL3 DIVM divider.
* @note The allowed values are 1..63.
*/
#if !defined(STM32_PLL3_DIVM_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL3_DIVM_VALUE 4
@ -515,6 +585,7 @@
/**
* @brief PLL3 DIVN multiplier.
* @note The allowed values are 4..512.
*/
#if !defined(STM32_PLL3_DIVN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL3_DIVN_VALUE 400
@ -522,6 +593,7 @@
/**
* @brief PLL3 FRACN multiplier, zero if no fractional part.
* @note The allowed values are 0..8191.
*/
#if !defined(STM32_PLL3_FRACN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL3_FRACN_VALUE 0
@ -529,6 +601,7 @@
/**
* @brief PLL3 DIVP divider.
* @note The allowed values are 2..128, odd values not allowed.
*/
#if !defined(STM32_PLL3_DIVP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL3_DIVP_VALUE 2
@ -536,6 +609,7 @@
/**
* @brief PLL3 DIVQ divider.
* @note The allowed values are 1..128.
*/
#if !defined(STM32_PLL3_DIVQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL3_DIVQ_VALUE 8
@ -543,136 +617,125 @@
/**
* @brief PLL3 DIVR divider.
* @note The allowed values are 1..128.
*/
#if !defined(STM32_PLL3_DIVR_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL3_DIVR_VALUE 8
#endif
/**
* @brief Peripherals clock selector.
*/
#if !defined(STM32_CKPERSEL) || defined(__DOXYGEN__)
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CLK
#endif
/**
* @brief MCO1 clock selector.
*/
#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
#endif
/**
* @brief MCO1 clock prescaler.
*/
#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
#define STM32_MCO1PRE 4
#endif
/**
* @brief MCO2 clock selector.
*/
#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
#endif
/**
* @brief MCO2 clock prescaler.
*/
#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
#define STM32_MCO2PRE 4
#endif
/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
* initialized and started.
* @note The default value is calculated for a 400MHz system clock from
* an external 8MHz HSE clock.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_SW) || defined(__DOXYGEN__)
#define STM32_SW RCC_CFGR_SW_PLL1
#define STM32_SW STM32_SW_PLL1_P_CK
#endif
/**
* @brief Clock source for the PLLs.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
* @note The default value is calculated for a 400MHz system clock from
* an external 8MHz HSE clock.
* @brief RTC clock selector.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
#define STM32_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSE
#endif
/**
* @brief PLLM divider value.
* @note The allowed values are 1..63.
* @note The default value is calculated for a 400MHz system clock from
* an external 8MHz HSE clock.
* @brief Clock domain 1 core bus prescaler.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLM_VALUE 4
#if !defined(STM32_D1CPRE) || defined(__DOXYGEN__)
#define STM32_D1CPRE STM32_D1CPRE_DIV1
#endif
/**
* @brief PLLN multiplier value.
* @note The allowed values are 192..432.
* @note The default value is calculated for a 400MHz system clock from
* an external 8MHz HSE clock.
* @brief Clock domain 1 HPRE prescaler.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLN_VALUE 400
#if !defined(STM32_D1HPRE) || defined(__DOXYGEN__)
#define STM32_D1HPRE STM32_D1HPRE_DIV2
#endif
/**
* @brief PLLP divider value.
* @note The allowed values are 2, 4, 6, 8.
* @note The default value is calculated for a 400MHz system clock from
* an external 8MHz HSE clock.
* @brief Clock domain 1 peripherals bus prescaler.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLP_VALUE 2
#if !defined(STM32_D1PPRE) || defined(__DOXYGEN__)
#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
#endif
/**
* @brief PLLQ divider value.
* @note The allowed values are 2..15.
* @note The default value is calculated for a 400MHz system clock from
* an external 8MHz HSE clock.
* @brief Clock domain 2 peripherals bus 1 prescaler.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLQ_VALUE 9
#if !defined(STM32_D2PPRE1) || defined(__DOXYGEN__)
#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
#endif
/**
* @brief AHB prescaler value.
* @brief Clock domain 2 peripherals bus 2 prescaler.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
#define STM32_HPRE STM32_HPRE_DIV1
#if !defined(STM32_D2PPRE2) || defined(__DOXYGEN__)
#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
#endif
/**
* @brief APB1 prescaler value.
* @brief Clock domain 3 peripherals bus prescaler.
* @note This setting can be modified at runtime.
*/
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
#define STM32_PPRE1 STM32_PPRE1_DIV4
#if !defined(STM32_D3PPRE4) || defined(__DOXYGEN__)
#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
#endif
/**
* @brief APB2 prescaler value.
*/
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
#define STM32_PPRE2 STM32_PPRE2_DIV2
#endif
/**
* @brief MCO1 clock source value.
* @note The default value outputs HSI clock on MCO1 pin.
*/
#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#endif
/**
* @brief MCO1 prescaler value.
* @note The default value outputs HSI clock on MCO1 pin.
*/
#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#endif
/**
* @brief MCO2 clock source value.
* @note The default value outputs SYSCLK / 4 on MCO2 pin.
*/
#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#endif
/**
* @brief MCO2 prescaler value.
* @note The default value outputs SYSCLK / 4 on MCO2 pin.
*/
#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#endif
/**
* @brief I2S clock source.

1
os/hal/ports/STM32/STM32H7xx/platform.mk
View File

@ -22,6 +22,7 @@ endif
# Drivers compatible with the platform.
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
# Shared variables