diff --git a/os/common/ports/ARM/chcore.h b/os/common/ports/ARM/chcore.h index c83d19e23..f424e9f1f 100644 --- a/os/common/ports/ARM/chcore.h +++ b/os/common/ports/ARM/chcore.h @@ -247,7 +247,7 @@ struct port_intctx { * at context switch time. */ struct port_context { - struct port_intctx *r13; + struct port_intctx *sp; }; /*===========================================================================*/ @@ -260,11 +260,11 @@ struct port_context { * by an @p port_intctx structure. */ #define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \ - (tp)->ctx.r13 = (struct port_intctx *)((uint8_t *)(wtop) - \ - sizeof (struct port_intctx)); \ - (tp)->ctx.r13->r4 = (regarm_t)(pf); \ - (tp)->ctx.r13->r5 = (regarm_t)(arg); \ - (tp)->ctx.r13->lr = (regarm_t)(_port_thread_start); \ + (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \ + sizeof (struct port_intctx)); \ + (tp)->ctx.sp->r4 = (regarm_t)(pf); \ + (tp)->ctx.sp->r5 = (regarm_t)(arg); \ + (tp)->ctx.sp->lr = (regarm_t)(_port_thread_start); \ } /** diff --git a/os/common/ports/ARMCMx/chcore.h b/os/common/ports/ARMCMx/chcore.h index 16743bbdf..32265cb58 100644 --- a/os/common/ports/ARMCMx/chcore.h +++ b/os/common/ports/ARMCMx/chcore.h @@ -135,7 +135,7 @@ struct port_intctx {}; * at context switch time. */ struct port_context { - struct port_intctx *r13; + struct port_intctx *sp; }; #endif /* !defined(_FROM_ASM_) */ diff --git a/os/common/ports/ARMCMx/chcore_v6m.h b/os/common/ports/ARMCMx/chcore_v6m.h index 0ff3288b6..b4c6b2d01 100644 --- a/os/common/ports/ARMCMx/chcore_v6m.h +++ b/os/common/ports/ARMCMx/chcore_v6m.h @@ -207,11 +207,11 @@ struct port_intctx { * by an @p port_intctx structure. */ #define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \ - (tp)->ctx.r13 = (struct port_intctx *)((uint8_t *)(wtop) - \ - sizeof (struct port_intctx)); \ - (tp)->ctx.r13->r4 = (regarm_t)(pf); \ - (tp)->ctx.r13->r5 = (regarm_t)(arg); \ - (tp)->ctx.r13->lr = (regarm_t)_port_thread_start; \ + (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \ + sizeof (struct port_intctx)); \ + (tp)->ctx.sp->r4 = (regarm_t)(pf); \ + (tp)->ctx.sp->r5 = (regarm_t)(arg); \ + (tp)->ctx.sp->lr = (regarm_t)_port_thread_start; \ } /** diff --git a/os/common/ports/ARMCMx/chcore_v7m.h b/os/common/ports/ARMCMx/chcore_v7m.h index 3c0dfc4a1..e274ea1db 100644 --- a/os/common/ports/ARMCMx/chcore_v7m.h +++ b/os/common/ports/ARMCMx/chcore_v7m.h @@ -363,11 +363,11 @@ struct port_intctx { * by an @p port_intctx structure. */ #define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \ - (tp)->ctx.r13 = (struct port_intctx *)((uint8_t *)(wtop) - \ - sizeof (struct port_intctx)); \ - (tp)->ctx.r13->r4 = (regarm_t)(pf); \ - (tp)->ctx.r13->r5 = (regarm_t)(arg); \ - (tp)->ctx.r13->lr = (regarm_t)_port_thread_start; \ + (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \ + sizeof (struct port_intctx)); \ + (tp)->ctx.sp->r4 = (regarm_t)(pf); \ + (tp)->ctx.sp->r5 = (regarm_t)(arg); \ + (tp)->ctx.sp->lr = (regarm_t)_port_thread_start; \ } /** diff --git a/os/rt/include/chschd.h b/os/rt/include/chschd.h index a3db7a3db..8275a1eee 100644 --- a/os/rt/include/chschd.h +++ b/os/rt/include/chschd.h @@ -51,9 +51,8 @@ priority. */ #define IDLEPRIO (tprio_t)1 /**< @brief Idle priority. */ #define LOWPRIO (tprio_t)2 /**< @brief Lowest priority. */ -#define NORMALPRIO (tprio_t)64 /**< @brief Normal priority. */ -#define HIGHPRIO (tprio_t)127 /**< @brief Highest priority. */ -#define ABSPRIO (tprio_t)255 /**< @brief Greatest priority. */ +#define NORMALPRIO (tprio_t)128 /**< @brief Normal priority. */ +#define HIGHPRIO (tprio_t)255 /**< @brief Highest priority. */ /** @} */ /** diff --git a/os/various/shell/shell_cmd.c b/os/various/shell/shell_cmd.c index 6432f59d3..80d683583 100644 --- a/os/various/shell/shell_cmd.c +++ b/os/various/shell/shell_cmd.c @@ -148,7 +148,7 @@ static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) { tp = chRegFirstThread(); do { chprintf(chp, "%08lx %08lx %08lx %4lu %9s %12s\r\n", - (uint32_t)tp->stklimit, (uint32_t)tp->ctx.r13, (uint32_t)tp, + (uint32_t)tp->stklimit, (uint32_t)tp->ctx.sp, (uint32_t)tp, (uint32_t)tp->prio, states[tp->state], tp->name == NULL ? "" : tp->name); tp = chRegNextThread(tp); diff --git a/release_note_16.1.0.txt b/release_note_16.1.0.txt deleted file mode 100644 index 287a2d932..000000000 --- a/release_note_16.1.0.txt +++ /dev/null @@ -1,90 +0,0 @@ -****************************************************************************** -*** ChibiOS 16.1.0 Release Notes. *** -****************************************************************************** - -ChibiOS 16.1.0 is composed of several independent but inter-operable -sub-projects: RT, NIL, HAL. - -*** ChibiOS 16.1.0 highlighs **** - -This release has been developed with focus mainly on the HAL subsystem and -general STM32 support. RT and NIL received minor bug fixes that have also -been back-ported to previous stable branches. - -*** ChibiOS 16.1.0 general improvements *** - -- ChibiOS release version number redefined as .. in order - to not confuse release version numbers with products version numbers. -- Improved ARMCMx GCC rules.ld supporting multiple RAM regions. It is now - possible to assign stacks, data, bss, etc ot any of the defined RAM regions. - - Added capability to allocate initialized, zeroed and not initialized data - to any of the defined RAM regions. - -*** What's new in RT 3.1.0 *** - -- Support for Cortex-M7. -- Added new function chVTGetTimersStateI() returning the state of the - timers list. This is useful to assess if it is convenient to transition - to lower power modes. -- Added CodeWarrior compiler support to the e200 port. -- Minor bugs fixed. - -*** What's new in HAL 4.0.0 *** - -- New watchdog (WDG) driver. -- Added support for STM32L0xx, STM32L4xx, STM32F7xx, STM32F446, STM32F030xC, - STM32F070x6, STM32F070xB, STM32F091xC, STM32F098xx devices. -- Improved USB driver. - - Modified the driver to have a separate USB_SUSPENDED state, this - allows the application to detect if the USB is communicating or if - it is disconnected or powered down. - - Added synchronous API. - - Removed queued API. - - Improved USB support for STM32 USBv1, OTGv1. - - Isochronous support for STM32 USBv1, OTGv1. - - STM32 USBv1/OTGv1 buffers and queues do not more require to be aligned in - position and size. -- Improved Serial-USB driver. - - New buffers queue object. - - Modified the driver to reject write/read attempts if the - underlying USB is not in active state. In case of disconnection the - SDU driver broadcasts a CHN_DISCONNECTED event. -- Improved CAN driver. - - Better errors reporting for STM32 CANv1. -- Improved UART driver. - - Added synchronous API. -- Improved PAL driver. - - Added "lines" handling to PAL driver, lines are identifiers of both - ports and pins encoded in a single value. Added a set of macros - operating on lines. - - Added GPIOv3 driver for STM32L4xx. -- I2S support added for STM32 SPIv2 peripheral. -- Board files an demos for STM32 Nucleo32 boards. -- Added latest CMSIS headers for all STM32 families. -- STM32 DMA drivers have been unified and consolidated in DMAv1 and DMAv2. - - DMA channels selection now supported on all devices with the new mux - mechanism. -- Added serial driver support for USART 3..6 on STM32F030xC devices. -- Added support for differential mode to the STM32F3xx ADC driver. -- STM32 GPT, ICU and PWM driver enhancements. Now it is possible to - suppress default ISRs by defining STM32_TIMx_SUPPRESS_ISR. - The application is now able to define custom handlers if required - or simply save space if the driver callbacks are not used. - Now the functions xxx_lld_serve_interrupts() have global scope, this - way custom ISRs can call them from outside the driver module. -- Added TIM units use cross-check in STM32 GPT, ICU, PWM and ST drivers, - now use collisions are explicitly reported. -- Added support for I2C3 and I2C4 to the STM32 I2Cv2 I2C driver. -- Added support for SPI4...SPI6 to the STM32 SPIv2 SPI driver. -- Added support for UART4...UART8 to the STM32 UARTv2 UART driver. -- Added support for UART7 and UART8,LPUART1 to the STM32 UARTv2 serial - driver. -- New STM32 ADCv3 driver supporting middle STM32 devices (F3, L4). -- New STM32 ADCv2 driver supporting large STM32 devices (F2, F4, F7). -- New STM32 ADCv1 driver supporting small STM32 devices (F0, L0). -- Introduced support for TIM21 and TIM22 in STM32 ST driver. - -*** What's new in NIL 1.1.0 *** - -- Support for Cortex-M7. -- Minor bugs fixed. diff --git a/release_note_next.txt b/release_note_next.txt new file mode 100644 index 000000000..0d921c24e --- /dev/null +++ b/release_note_next.txt @@ -0,0 +1,44 @@ +****************************************************************************** +*** ChibiOS next Release Notes. *** +****************************************************************************** + +ChibiOS next is composed of several independent but inter-operable +sub-projects: RT, NIL, HAL. + +*** ChibiOS next highlights **** + +This release is focused on RTOS general improvements, both RT and NIL received +a series of important new features. + +*** ChibiOS next general improvements *** + +- Rationalized source tree to reduce code duplication. +- Shared RTOS components, now allocators, mailboxes and binary semaphores + are usable by both RT and NIL. +- Shared ports architecture. Now RTOS ports work for both RT and NIL, no + more duplication. +- Enhanced shell. + +*** What's new in RT 4.0.0 *** + +- Common ports architecture. +- Ability to use the new shared RTOS components. +- Enhanced trace buffer, it is able to store events regarding not just threads + but also IRQs, halts and user events. +- Simplified the dynamic threading model, now it is the thread creator + responsible for memory release, the references counter has been removed + and the code is much simpler. +- New threading API, now creating static threads is even faster. +- Saved space in thread_t structure. +- Extended priority range to 1..255. +- Experimental NASA OSAL implementation. + +*** What's new in HAL 4.1.0 *** + + +*** What's new in NIL 2.0.0 *** + +- Common ports architecture. +- Ability to use the new shared RTOS components. +- State checker. +- Parameter checks.