git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5338 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
d8914f064f
commit
03ef7de020
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@ -45,7 +45,13 @@
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/*
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* ADC driver settings.
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*/
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#define SPC5_ADC_USE_EQADC_Q0 TRUE
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#define SPC5_ADC_USE_ADC0_Q0 TRUE
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#define SPC5_ADC_USE_ADC0_Q1 FALSE
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#define SPC5_ADC_USE_ADC0_Q2 FALSE
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#define SPC5_ADC_USE_ADC1_Q3 TRUE
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#define SPC5_ADC_USE_ADC1_Q4 FALSE
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#define SPC5_ADC_USE_ADC1_Q5 FALSE
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#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
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/*
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* SERIAL driver system settings.
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@ -29,6 +29,12 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief Calibration constant.
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* @details Ideal conversion result for 75%(VRH - VRL) minus 2.
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*/
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#define ADC_IDEAL_RES75_2 12286
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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@ -36,16 +42,51 @@
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/**
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* @brief ADCD1 driver identifier.
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*/
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#if SPC5_ADC_USE_EQADC_Q0 || defined(__DOXYGEN__)
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#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/**
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* @brief ADCD2 driver identifier.
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*/
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#if SPC5_ADC_USE_ADC0_Q1 || defined(__DOXYGEN__)
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ADCDriver ADCD2;
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#endif
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/**
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* @brief ADCD3 driver identifier.
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*/
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#if SPC5_ADC_USE_ADC0_Q2 || defined(__DOXYGEN__)
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ADCDriver ADCD3;
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#endif
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/**
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* @brief ADCD4 driver identifier.
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*/
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#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__)
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ADCDriver ADCD4;
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#endif
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/**
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* @brief ADCD5 driver identifier.
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*/
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#if SPC5_ADC_USE_ADC1_Q4 || defined(__DOXYGEN__)
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ADCDriver ADCD5;
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#endif
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/**
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* @brief ADCD6 driver identifier.
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*/
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#if SPC5_ADC_USE_ADC1_Q5 || defined(__DOXYGEN__)
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ADCDriver ADCD6;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/* Driver local functions and macros. */
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/*===========================================================================*/
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/**
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@ -121,6 +162,93 @@ static void cfifo0_wait_rfifo(uint32_t n) {
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EQADC.FISR[0].R = EQADC_FISR_CLEAR_MASK;
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}
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/**
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* @brief Reads a sample from the RFIFO0.
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*
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* @notapi
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*/
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#define rfifo0_get_value() (EQADC.RFPR[0].R)
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/**
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* @brief Writes an internal ADC register.
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*
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* @param[in] adc the ADC unit
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* @param[in] reg the register index
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* @param[in] value value to be written into the register
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*
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* @notapi
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*/
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#define adc_write_register(adc, reg, value) \
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cfifo0_push_command(EQADC_RW_WRITE | (adc) | EQADC_RW_REG_ADDR(reg) | \
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EQADC_RW_VALUE(value))
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/**
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* @brief Enables both ADCs.
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*
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* @notapi
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*/
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static void adc_enable(void) {
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/* Both ADCs must be enabled because this sentence in the reference manual:
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"Both ADC0 and ADC1 of an eQADC module pair must be enabled before
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calibrating or using either ADC0 or ADC1 of the pair. Failure to
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enable both ADC0 and ADC1 of the pair can result in inaccurate
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conversions.".*/
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adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_CR,
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SPC5_ADC_CR_CLK_PS | ADC_CR_EN);
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adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_CR,
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SPC5_ADC_CR_CLK_PS | ADC_CR_EN);
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}
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/**
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* @brief Disables both ADCs.
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*
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* @notapi
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*/
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static void adc_disable(void) {
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adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_CR,
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SPC5_ADC_CR_CLK_PS);
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adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_CR,
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SPC5_ADC_CR_CLK_PS);
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}
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/**
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* @brief Calibrates both ADCs.
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*
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* @notapi
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*/
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static void adc_calibrate(uint32_t adc) {
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uint16_t res25, res75;
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uint32_t gcc, occ;
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/* Starts the calibration, write command messages to sample 25% and
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75% VREF.*/
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cfifo0_push_command(0x00002C00 | adc); /* Vref 25%.*/
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cfifo0_push_command(0x00002B00 | adc); /* Vref 75%.*/
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cfifo0_wait_rfifo(2);
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/* Reads the results and compute calibration register values.*/
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res25 = rfifo0_get_value();
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res75 = rfifo0_get_value();
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gcc = 0x08000000UL / ((uint32_t)res75 - (uint32_t)res25);
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occ = (uint32_t)ADC_IDEAL_RES75_2 - ((gcc * (uint32_t)res75) >> 14);
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/* Loads the gain and offset values (default configuration, 12 bits).*/
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adc_write_register(adc, ADC_REG_GCCR, gcc);
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adc_write_register(adc, ADC_REG_OCCR, occ & 0xFFFF);
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/* Loads gain and offset values (alternate configuration 1, 10 bits).*/
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adc_write_register(adc, ADC_REG_AC1GCCR, gcc);
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adc_write_register(adc, ADC_REG_AC1OCCR, occ & 0xFFFF);
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/* Loads gain and offset values (alternate configuration 1, 8 bits).*/
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adc_write_register(adc, ADC_REG_AC2GCCR, gcc);
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adc_write_register(adc, ADC_REG_AC2OCCR, occ & 0xFFFF);
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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@ -140,6 +268,27 @@ void adc_lld_init(void) {
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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#endif /* SPC5_ADC_USE_EQADC_Q0 */
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/* Temporarily enables CFIFO0 for calibration and initialization.*/
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cfifo_enable(ADC_FIFO_0, EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWCS, 0);
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adc_enable();
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/* Calibration of both ADC units then programming alternate configs
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one and two for 10 and 8 bits operations.*/
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#if SPC5_ADC_USE_ADC0
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adc_calibrate(EQADC_RW_BN_ADC0);
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adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_AC1CR, ADC_ACR_RESSEL_10BITS);
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adc_write_register(EQADC_RW_BN_ADC0, ADC_REG_AC2CR, ADC_ACR_RESSEL_8BITS);
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#endif
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#if SPC5_ADC_USE_ADC1
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adc_calibrate(EQADC_RW_BN_ADC1);
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adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_AC1CR, ADC_ACR_RESSEL_10BITS);
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adc_write_register(EQADC_RW_BN_ADC1, ADC_REG_AC2CR, ADC_ACR_RESSEL_8BITS);
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#endif
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/* ADCs disabled until the driver is started by the application.*/
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adc_disable();
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cfifo_disable(ADC_FIFO_0);
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}
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/**
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@ -153,7 +302,7 @@ void adc_lld_start(ADCDriver *adcp) {
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if (adcp->state == ADC_STOP) {
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/* Enables the peripheral.*/
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#if SPC5_ADC_USE_EQADC_Q0
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#if SPC5_ADC_USE_ADC0
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if (&ADCD1 == adcp) {
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}
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@ -176,7 +325,7 @@ void adc_lld_stop(ADCDriver *adcp) {
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/* Resets the peripheral.*/
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/* Disables the peripheral.*/
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#if SPC5_ADC_USE_EQADC_Q0
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#if SPC5_ADC_USE_ADC0
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if (&ADCD1 == adcp) {
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}
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@ -78,7 +78,7 @@
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#define EQADC_CFCR_MODE_HWSS_FE EQADC_CFCR_MODE(4)
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#define EQADC_CFCR_MODE_HWSS_RE EQADC_CFCR_MODE(5)
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#define EQADC_CFCR_MODE_HWSS_BE EQADC_CFCR_MODE(6)
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#define EQADC_CFCR_MODE_MODE_SWCS EQADC_CFCR_MODE(9)
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#define EQADC_CFCR_MODE_SWCS EQADC_CFCR_MODE(9)
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#define EQADC_CFCR_MODE_HWCS_LL EQADC_CFCR_MODE(10)
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#define EQADC_CFCR_MODE_HWCS_HL EQADC_CFCR_MODE(11)
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#define EQADC_CFCR_MODE_HWCS_FE EQADC_CFCR_MODE(12)
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@ -112,10 +112,18 @@
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/** @} */
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/**
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* @name EQADC Conversion commands
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* @name EQADC conversion/configuration commands
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* @{
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*/
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#define EQADC_CONV_CHANNEL_MASK (0xFFU << 8)/**< @brief Channel number mask.*/
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#define EQADC_CONV_CONFIG_SEL1 (8U << 0) /**< @brief Alt.config.1. */
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#define EQADC_CONV_CONFIG_SEL2 (9U << 0) /**< @brief Alt.config.2. */
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#define EQADC_CONV_CONFIG_SEL3 (10U << 0) /**< @brief Alt.config.3. */
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#define EQADC_CONV_CONFIG_SEL4 (11U << 0) /**< @brief Alt.config.4. */
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#define EQADC_CONV_CONFIG_SEL5 (12U << 0) /**< @brief Alt.config.5. */
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#define EQADC_CONV_CONFIG_SEL6 (13U << 0) /**< @brief Alt.config.6. */
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#define EQADC_CONV_CONFIG_SEL7 (14U << 0) /**< @brief Alt.config.7. */
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#define EQADC_CONV_CONFIG_SEL8 (15U << 0) /**< @brief Alt.config.8. */
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#define EQADC_CONV_CHANNEL_MASK (255U << 8) /**< @brief Channel number mask.*/
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#define EQADC_CONV_CHANNEL(n) ((n) << 8) /**< @brief Channel number. */
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#define EQADC_CONV_FMT_RJU (0U << 16) /**< @brief Unsigned samples. */
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#define EQADC_CONV_FMT_RJS (1U << 16) /**< @brief Signed samples. */
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@ -130,12 +138,60 @@
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#define EQADC_CONV_MSG_NULL (6U << 20) /**< @brief Null message. */
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#define EQADC_CONV_CAL (1U << 24) /**< @brief Calibrated result. */
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#define EQADC_CONV_BN_MASK (1U << 25) /**< @brief Buffer number mask. */
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#define EQADC_CONV_BN(n) ((n) << 25) /**< @brief Buffer number. */
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#define EQADC_CONV_BN_ADC0 (0U << 25) /**< @brief ADC0 selection. */
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#define EQADC_CONV_BN_ADC1 (1U << 25) /**< @brief ADC1 selection. */
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#define EQADC_CONV_REP (1U << 29) /**< @brief Repeat loop flag. */
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#define EQADC_CONV_PAUSE (1U << 30) /**< @brief Pause flag. */
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#define EQADC_CONV_EOQ (1U << 31) /**< @brief End of queue flag. */
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/** @} */
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/**
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* @name EQADC read/write commands
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* @{
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*/
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#define EQADC_RW_REG_ADDR_MASK (255U << 0)
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#define EQADC_RW_REG_ADDR(n) ((n) << 0)
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#define EQADC_RW_VALUE_MASK (0xFFFF << 8)
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#define EQADC_RW_VALUE(n) ((n) << 8)
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#define EQADC_RW_WRITE (0U << 24)
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#define EQADC_RW_READ (1U << 24)
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#define EQADC_RW_BN_ADC0 (0U << 25)
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#define EQADC_RW_BN_ADC1 (1U << 25)
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#define EQADC_RW_REP (1U << 29)
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#define EQADC_RW_PAUSE (1U << 30)
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#define EQADC_RW_EOQ (1U << 31)
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/** @} */
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/**
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* @name ADC CR register definitions
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* @{
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*/
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#define ADC_CR_CLK_PS_MASK (31U << 0)
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#define ADC_CR_CLK_PS(n) ((((n) >> 1) - 1) | ((n) & 1 ? ADC_CR_ODD_PS\
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: 0))
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#define ADC_CR_CLK_SEL (1U << 5)
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#define ADC_CR_CLK_DTY (1U << 6)
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#define ADC_CR_ODD_PS (1U << 7)
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#define ADC_CR_TBSEL_MASK (3U << 8)
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#define ADC_CR_TBSEL(n) ((n) << 8)
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#define ADC_CR_EMUX (1U << 11)
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#define ADC_CR_EN (1U << 15)
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/** @} */
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/**
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* @name ADC AxCR registers definitions
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* @{
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*/
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#define ADC_ACR_PRE_GAIN_MASK (3U << 0)
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#define ADC_ACR_PRE_GAIN_X1 (0U << 0)
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#define ADC_ACR_PRE_GAIN_X2 (1U << 0)
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#define ADC_ACR_PRE_GAIN_X4 (2U << 0)
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#define ADC_ACR_RESSEL_MASK (3U << 6)
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#define ADC_ACR_RESSEL_12BITS (0U << 6)
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#define ADC_ACR_RESSEL_10BITS (1U << 6)
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#define ADC_ACR_RESSEL_8BITS (2U << 6)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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@ -145,12 +201,65 @@
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* @{
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*/
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/**
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* @brief ADCD10 driver enable switch.
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* @details If set to @p TRUE the support for EQADC1 queue 0 is included.
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* @brief ADCD1 driver enable switch.
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* @details If set to @p TRUE the support for ADC0 queue 0 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_ADC_USE_EQADC_Q0) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_EQADC_Q0 FALSE
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#if !defined(SPC5_ADC_USE_ADC0_Q0) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_ADC0_Q0 FALSE
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#endif
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/**
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* @brief ADCD2 driver enable switch.
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* @details If set to @p TRUE the support for ADC0 queue 1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_ADC_USE_ADC0_Q1) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_ADC0_Q1 FALSE
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#endif
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/**
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* @brief ADCD3 driver enable switch.
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* @details If set to @p TRUE the support for ADC0 queue 2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_ADC_USE_ADC0_Q2) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_ADC0_Q2 FALSE
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#endif
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/**
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* @brief ADCD4 driver enable switch.
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* @details If set to @p TRUE the support for ADC1 queue 3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_ADC_USE_ADC1_Q3) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_ADC1_Q3 FALSE
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#endif
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/**
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* @brief ADCD5 driver enable switch.
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* @details If set to @p TRUE the support for ADC1 queue 4 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_ADC_USE_ADC1_Q4) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_ADC1_Q4 FALSE
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#endif
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/**
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* @brief ADCD6 driver enable switch.
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* @details If set to @p TRUE the support for ADC1 queue 5 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_ADC_USE_ADC1_Q5) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_ADC1_Q5 FALSE
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#endif
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/**
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*
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* @brief EQADC clock prescaler value.
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*/
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#if !defined(SPC5_ADC_CR_CLK_PS) || defined(__DOXYGEN__)
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#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
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#endif
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/** @} */
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@ -158,12 +267,19 @@
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if SPC5_ADC_USE_EQADC_Q0 && !SPC5_HAS_EQADC
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#if !SPC5_HAS_EQADC
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#error "EQADC1 not present in the selected device"
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#endif
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#if !SPC5_ADC_USE_EQADC_Q0
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#error "ADC driver activated but no EQADC peripheral assigned"
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#define SPC5_ADC_USE_ADC0 (SPC5_ADC_USE_ADC0_Q0 | \
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SPC5_ADC_USE_ADC0_Q1 | \
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SPC5_ADC_USE_ADC0_Q2)
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#define SPC5_ADC_USE_ADC1 (SPC5_ADC_USE_ADC1_Q3 | \
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SPC5_ADC_USE_ADC1_Q4 | \
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SPC5_ADC_USE_ADC1_Q5)
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#if !SPC5_ADC_USE_ADC0 && !SPC5_ADC_USE_ADC1
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#error "ADC driver activated but no ADC peripheral assigned"
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#endif
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/*===========================================================================*/
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@ -334,10 +450,30 @@ struct ADCDriver {
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/* External declarations. */
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/*===========================================================================*/
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#if SPC5_ADC_USE_EQADC_Q0 && !defined(__DOXYGEN__)
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#if SPC5_ADC_USE_ADC0_Q0 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD1;
|
||||
#endif
|
||||
|
||||
#if SPC5_ADC_USE_ADC0_Q1 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD2;
|
||||
#endif
|
||||
|
||||
#if SPC5_ADC_USE_ADC0_Q2 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD3;
|
||||
#endif
|
||||
|
||||
#if SPC5_ADC_USE_ADC1_Q3 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD4;
|
||||
#endif
|
||||
|
||||
#if SPC5_ADC_USE_ADC1_Q4 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD5;
|
||||
#endif
|
||||
|
||||
#if SPC5_ADC_USE_ADC1_Q5 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD6;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue