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Fixed L2C_310 defines. 

git-svn-id: https://svn.code.sf.net/p/chibios/svn2/trunk@11572 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
isiora 2018-02-27 00:12:49 +00:00
parent 6c665fa72e
commit 043860de59
1 changed files with 2 additions and 2 deletions
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4
os/common/ext/ARM/CMSIS/Core_A/Include/ARMCA5.h
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@ -114,7 +114,7 @@ typedef enum IRQn
//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache.
//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort.
#define VE_A5_MP_PL310_BASE (0x2C0F0000UL) /*!< (L2C-310 ) Base Address */
#define VE_A5_MP_PL310_BASE (0x00A00000UL) /*!< (L2C-310 ) Base Address */
#define L2C_310_BASE VE_A5_MP_PL310_BASE
/* -------- Configuration of the Cortex-A5 Processor and Core Peripherals ------- */
@ -123,7 +123,7 @@ typedef enum IRQn
#define __FPU_PRESENT 1U /* FPU present */
#define __GIC_PRESENT 1U /* GIC present */
#define __TIM_PRESENT 1U /* TIM present */
#define __L2C_PRESENT 0U /* L2C present */
#define __L2C_PRESENT 1U /* L2C present */
#include "core_ca.h"
#include <system_ARMCA5.h>