diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc new file mode 100644 index 000000000..9a5ad93f9 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc @@ -0,0 +1,134 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_ahb.inc + * @brief Shared AHB clock handler. + * + * @addtogroup STM32_AHB_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @name HPRE field bits definitions + * @{ + */ +#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */ +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ + +/* Checks on configurations.*/ +#if !defined(STM32_HPRE) +#error "STM32_HPRE not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_SYSCLK_MAX) +#error "STM32_SYSCLK_MAX not defined in hal_lld.h" +#endif + +/* Input checks.*/ +#if !defined(STM32_SYSCLK) +#error "STM32_SYSCLK not defined in hal_lld.h" +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) + +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) + +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) + +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) + +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) + +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) + +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) + +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) + +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) + +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* + * SYSCLK frequency check. + */ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/* + * HCLK frequency check. + */ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc new file mode 100644 index 000000000..467dcdbd6 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb1.inc @@ -0,0 +1,111 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_apb1.inc + * @brief Shared APB1 clock handler. + * + * @addtogroup STM32_APB1_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @name PPRE1 field bits definitions + * @{ + */ +#define STM32_PPRE1_MASK (7 << 8) /**< PPRE1 field mask. */ +#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ + +/* Checks on configurations.*/ +#if !defined(STM32_PPRE1) +#error "STM32_PPRE1 not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_PCLK1_MAX) +#error "STM32_PCLK1_MAX not defined in hal_lld.h" +#endif + +/* Input checks.*/ +#if !defined(STM32_HCLK) +#error "STM32_HCLK not defined in hal_lld.h" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) + +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) + +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) + +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) + +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) + +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* + * APB1 frequency check. + */ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc new file mode 100644 index 000000000..af8654d34 --- /dev/null +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_apb2.inc @@ -0,0 +1,111 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RCCv1/stm32_apb2.inc + * @brief Shared APB2 clock handler. + * + * @addtogroup STM32_APB2_HANDLER + * @{ + */ + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @name PPRE1 field bits definitions + * @{ + */ +#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */ +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* Registry checks for robustness.*/ + +/* Checks on configurations.*/ +#if !defined(STM32_PPRE1) +#error "STM32_PPRE1 not defined in mcuconf.h" +#endif + +/* Check on limits.*/ +#if !defined(STM32_PCLK1_MAX) +#error "STM32_PCLK1_MAX not defined in hal_lld.h" +#endif + +/* Input checks.*/ +#if !defined(STM32_HCLK) +#error "STM32_HCLK not defined in hal_lld.h" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) + +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) + +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) + +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) + +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) + +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* + * APB2 frequency check. + */ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc index 4901738c0..def15a376 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi16.inc @@ -26,6 +26,11 @@ /* Driver local definitions. */ /*===========================================================================*/ +/** + * @brief HSI16 clock frequency. + */ +#define STM32_HSI16CLK 16000000 + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc index c3ede98d6..0a4f07b7c 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_hsi48.inc @@ -26,6 +26,11 @@ /* Driver local definitions. */ /*===========================================================================*/ +/** + * @brief HSI48 clock frequency. + */ +#define STM32_HSI48CLK 48000000 + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc index 90374bd75..d9aba2bfb 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_lsi.inc @@ -26,6 +26,11 @@ /* Driver local definitions. */ /*===========================================================================*/ +/** + * @brief LSI clock frequency. + */ +#define STM32_LSICLK 32000 + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc index 657948d07..922608100 100644 --- a/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc +++ b/os/hal/ports/STM32/LLD/RCCv1/stm32_msi.inc @@ -45,6 +45,17 @@ #define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */ /** @} */ +/** + * @name RCC_CSR register bits definitions + * @{ + */ +#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */ +#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */ +#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */ +#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */ +#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */ +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32L5xx/hal_lld.c b/os/hal/ports/STM32/STM32L5xx/hal_lld.c index b4371149c..0cdc70aca 100644 --- a/os/hal/ports/STM32/STM32L5xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L5xx/hal_lld.c @@ -151,8 +151,7 @@ void stm32_clock_init(void) { flash_ws_init(STM32_MSI_FLASHBITS); /* Clocks setup.*/ - lse_init(); /* LSE before MSI because MSIPLL - uses LSE.*/ + lse_init(); /* LSE first because MSIPLL. */ msi_init(); lsi_init(); hsi16_init(); diff --git a/os/hal/ports/STM32/STM32L5xx/hal_lld.h b/os/hal/ports/STM32/STM32L5xx/hal_lld.h index b65ba8ab6..f44af7e3d 100644 --- a/os/hal/ports/STM32/STM32L5xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L5xx/hal_lld.h @@ -65,15 +65,6 @@ #endif /** @} */ -/** - * @name Internal clock sources - * @{ - */ -#define STM32_HSI16CLK 16000000 /**< 16MHz internal clock. */ -#define STM32_HSI48CLK 48000000 /**< 48MHz internal clock. */ -#define STM32_LSICLK 32000 /**< Low speed internal clock. */ -/** @} */ - /** * @name PWR_CR1 register bits definitions * @{ @@ -94,31 +85,6 @@ #define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */ #define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */ -#define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */ -#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define STM32_PPRE1_MASK (7 << 8) /**< PPRE1 field mask. */ -#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ - -#define STM32_PPRE2_MASK (7 << 11) /**< PPRE2 field mask. */ -#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ - #define STM32_STOPWUCK_MASK (1 << 15) /**< STOPWUCK field mask. */ #define STM32_STOPWUCK_MSI (0 << 15) /**< Wakeup clock is MSI. */ #define STM32_STOPWUCK_HSI16 (1 << 15) /**< Wakeup clock is HSI16. */ @@ -326,17 +292,6 @@ #define STM32_LSCOSEL_LSE (3 << 24) /**< LSE on LSCO pin. */ /** @} */ -/** - * @name RCC_CSR register bits definitions - * @{ - */ -#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */ -#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */ -#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */ -#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */ -#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */ -/** @} */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -419,29 +374,6 @@ #define STM32_PLLSAI2SRC STM32_PLLSAI2SRC_MSI #endif -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 120MHz system clock from - * the internal 4MHz MSI clock. - */ -#if !defined(STM32_HPRE) || defined(__DOXYGEN__) -#define STM32_HPRE STM32_HPRE_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) -#define STM32_PPRE1 STM32_PPRE1_DIV1 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) -#define STM32_PPRE2 STM32_PPRE2_DIV1 -#endif - /** * @brief STOPWUCK clock setting. */ @@ -872,10 +804,9 @@ #include "stm32_hse.inc" /* - * HSI16 related checks. + * Platform HSI16-related checks. */ -#if STM32_HSI16_ENABLED -#else /* !STM32_HSI16_ENABLED */ +#if !STM32_HSI16_ENABLED #if STM32_SW == STM32_SW_HSI16 #error "HSI16 not enabled, required by STM32_SW" @@ -997,10 +928,9 @@ #endif /* !STM32_HSI48_ENABLED */ /* - * HSE related checks. + * Platform HSE-related checks. */ -#if STM32_HSE_ENABLED -#else /* !STM32_HSE_ENABLED */ +#if !STM32_HSE_ENABLED #if STM32_SW == STM32_SW_HSE #error "HSE not enabled, required by STM32_SW" @@ -1057,10 +987,9 @@ #endif /* !STM32_HSE_ENABLED */ /* - * LSI related checks. + * Platform LSI-related checks. */ -#if STM32_LSI_ENABLED -#else /* !STM32_LSI_ENABLED */ +#if !STM32_LSI_ENABLED #if STM32_RTCSEL == STM32_RTCSEL_LSI #error "LSI not enabled, required by STM32_RTCSEL" @@ -1077,7 +1006,7 @@ #endif /* !STM32_LSI_ENABLED */ /* - * LSE related checks. + * Platform LSE-related checks. */ #if !STM32_LSE_ENABLED #if STM32_RTCSEL == STM32_RTCSEL_LSE @@ -1312,109 +1241,10 @@ #error "invalid STM32_SW value specified" #endif -/* Check on the system clock.*/ -#if STM32_SYSCLK > STM32_SYSCLK_MAX -#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief AHB frequency. - */ -#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) -#define STM32_HCLK (STM32_SYSCLK / 1) - -#elif STM32_HPRE == STM32_HPRE_DIV2 -#define STM32_HCLK (STM32_SYSCLK / 2) - -#elif STM32_HPRE == STM32_HPRE_DIV4 -#define STM32_HCLK (STM32_SYSCLK / 4) - -#elif STM32_HPRE == STM32_HPRE_DIV8 -#define STM32_HCLK (STM32_SYSCLK / 8) - -#elif STM32_HPRE == STM32_HPRE_DIV16 -#define STM32_HCLK (STM32_SYSCLK / 16) - -#elif STM32_HPRE == STM32_HPRE_DIV64 -#define STM32_HCLK (STM32_SYSCLK / 64) - -#elif STM32_HPRE == STM32_HPRE_DIV128 -#define STM32_HCLK (STM32_SYSCLK / 128) - -#elif STM32_HPRE == STM32_HPRE_DIV256 -#define STM32_HCLK (STM32_SYSCLK / 256) - -#elif STM32_HPRE == STM32_HPRE_DIV512 -#define STM32_HCLK (STM32_SYSCLK / 512) - -#else -#error "invalid STM32_HPRE value specified" -#endif - -/* - * AHB frequency check. - */ -#if STM32_HCLK > STM32_SYSCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK1 (STM32_HCLK / 1) - -#elif STM32_PPRE1 == STM32_PPRE1_DIV2 -#define STM32_PCLK1 (STM32_HCLK / 2) - -#elif STM32_PPRE1 == STM32_PPRE1_DIV4 -#define STM32_PCLK1 (STM32_HCLK / 4) - -#elif STM32_PPRE1 == STM32_PPRE1_DIV8 -#define STM32_PCLK1 (STM32_HCLK / 8) - -#elif STM32_PPRE1 == STM32_PPRE1_DIV16 -#define STM32_PCLK1 (STM32_HCLK / 16) - -#else -#error "invalid STM32_PPRE1 value specified" -#endif - -/* - * APB1 frequency check. - */ -#if STM32_PCLK1 > STM32_PCLK1_MAX -#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) -#define STM32_PCLK2 (STM32_HCLK / 1) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV2 -#define STM32_PCLK2 (STM32_HCLK / 2) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV4 -#define STM32_PCLK2 (STM32_HCLK / 4) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV8 -#define STM32_PCLK2 (STM32_HCLK / 8) - -#elif STM32_PPRE2 == STM32_PPRE2_DIV16 -#define STM32_PCLK2 (STM32_HCLK / 16) - -#else -#error "invalid STM32_PPRE2 value specified" -#endif - -/* - * APB2 frequency check. - */ -#if STM32_PCLK2 > STM32_PCLK2_MAX -#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" -#endif +/* Bus handlers.*/ +#include "stm32_ahb.inc" +#include "stm32_apb1.inc" +#include "stm32_apb2.inc" /** * @brief MCO divider clock frequency.