git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8343 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
1380d928ce
commit
05e3b28528
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@ -59,89 +59,6 @@
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 6
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
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/*
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* EXT driver system settings.
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*/
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#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 FALSE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM9 FALSE
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#define STM32_GPT_USE_TIM10 FALSE
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#define STM32_GPT_USE_TIM11 FALSE
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#define STM32_GPT_TIM2_IRQ_PRIORITY 7
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#define STM32_GPT_TIM3_IRQ_PRIORITY 7
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#define STM32_GPT_TIM4_IRQ_PRIORITY 7
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#define STM32_GPT_TIM5_IRQ_PRIORITY 7
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#define STM32_GPT_TIM6_IRQ_PRIORITY 7
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#define STM32_GPT_TIM7_IRQ_PRIORITY 7
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#define STM32_GPT_TIM9_IRQ_PRIORITY 7
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#define STM32_GPT_TIM10_IRQ_PRIORITY 7
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#define STM32_GPT_TIM11_IRQ_PRIORITY 7
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_TIM2_IRQ_PRIORITY 7
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#define STM32_ICU_TIM3_IRQ_PRIORITY 7
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#define STM32_ICU_TIM4_IRQ_PRIORITY 7
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#define STM32_ICU_TIM9_IRQ_PRIORITY 7
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM9 FALSE
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#define STM32_PWM_TIM2_IRQ_PRIORITY 7
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#define STM32_PWM_TIM3_IRQ_PRIORITY 7
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#define STM32_PWM_TIM4_IRQ_PRIORITY 7
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#define STM32_PWM_TIM9_IRQ_PRIORITY 7
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/*
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* SERIAL driver system settings.
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*/
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@ -152,43 +69,10 @@
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#define STM32_SERIAL_USART2_PRIORITY 12
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#define STM32_SERIAL_USART3_PRIORITY 12
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 8
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#define STM32_ST_USE_TIMER 5
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_USB1 FALSE
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#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
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#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
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#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
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#define STM32_ST_USE_TIMER 2
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#endif /* _MCUCONF_H_ */
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@ -20,17 +20,14 @@
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - STM32_LSECLK.
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* - STM32_LSEDRV.
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* - STM32_LSE_BYPASS (optionally).
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* - STM32_HSECLK.
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* - STM32_HSE_BYPASS (optionally).
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* .
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* One of the following macros must also be defined:
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* - STM32L100xB, STM32L100xBA, STM32L100xC.
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* - STM32L151xB, STM32L151xBA, STM32L151xC, STM32L151xCA,
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* STM32L151xD, STM32L151xDX, STM32L151xE.
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* - STM32L152xB, STM32L152xBA, STM32L152xC, STM32L152xCA,
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* STM32L152xD, STM32L152xDX, STM32L152xE.
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* - STM32L162xC, STM32L162xCA, STM32L162xD, STM32L162xDX,
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* STM32L162xE.
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* - STM32L471xx, STM32L475xx, STM32L476xx.
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* - STM32L485xx, STM32L486xx.
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* .
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*
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* @addtogroup HAL
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@ -50,33 +47,22 @@
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* @name Platform identification
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* @{
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*/
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#if defined(STM32L100xB) || defined(STM32L151xB) || \
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defined(STM32L152xB) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density"
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#if defined(STM32L471xx) || defined(STM32L475xx) || \
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defined(STM32L476xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32L4xx Ultra Low Power"
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#elif defined(STM32L100xBA) || defined(STM32L100xC) || \
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defined(STM32L151xBA) || defined(STM32L151xC) || \
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defined(STM32L151xCA) || defined(STM32L152xBA) || \
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defined(STM32L152xC) || defined(STM32L152xCA) || \
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defined(STM32L162xC) || defined(STM32L162xCA)
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#define PLATFORM_NAME "STM32L1xx Ultra Low Power Medium Density Plus"
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#elif defined(STM32L151xD) || defined(STM32L151xDX) || \
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defined(STM32L151xE) || defined(STM32L152xD) || \
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defined(STM32L152xDX) || defined(STM32L152xE) || \
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defined(STM32L162xD) || defined(STM32L162xDX) || \
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defined(STM32L162xE)
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#define PLATFORM_NAME "STM32L1xx Ultra Low Power High Density"
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#elif defined(STM32L485xx) || defined(STM32L486xx)
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#define PLATFORM_NAME "STM32L4xx Ultra Low Power with Crypto"
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#else
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#error "STM32L1xx device not specified"
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#error "STM32L4xx device not specified"
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#endif
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/**
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* @brief Sub-family identifier.
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*/
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#if !defined(STM32L1XX) || defined(__DOXYGEN__)
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#define STM32L1XX
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#if !defined(STM32L4XX) || defined(__DOXYGEN__)
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#define STM32L4XX
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#endif
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/** @} */
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@ -89,34 +75,46 @@
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/** @} */
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/**
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* @name PWR_CR register bits definitions
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* @name PWR_CR1 register bits definitions
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* @{
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*/
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#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */
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#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */
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#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
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#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */
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#define STM32_VOS_MASK (3 << 9) /**< Core voltage mask. */
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#define STM32_VOS_RANGE1 (1 << 9) /**< Core voltage 1.8 Volts. */
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#define STM32_VOS_RANGE2 (2 << 9) /**< Core voltage 1.5 Volts. */
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/** @} */
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#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
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#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
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#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
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#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
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#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
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#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
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#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
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#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
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/**
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* @name PWR_CR2 register bits definitions
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* @{
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*/
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#define STM32_PLS_MASK (7 << 1) /**< PLS bits mask. */
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#define STM32_PLS_LEV0 (0 << 1) /**< PVD level 0. */
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#define STM32_PLS_LEV1 (1 << 1) /**< PVD level 1. */
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#define STM32_PLS_LEV2 (2 << 1) /**< PVD level 2. */
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#define STM32_PLS_LEV3 (3 << 1) /**< PVD level 3. */
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#define STM32_PLS_LEV4 (4 << 1) /**< PVD level 4. */
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#define STM32_PLS_LEV5 (5 << 1) /**< PVD level 5. */
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#define STM32_PLS_LEV6 (6 << 1) /**< PVD level 6. */
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#define STM32_PLS_EXT (7 << 1) /**< PVD level 7. */
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/** @} */
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/**
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* @name RCC_CR register bits definitions
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* @{
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*/
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#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */
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#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */
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#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */
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#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */
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#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */
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#define STM32_MSIRANGE_MASK (15 << 4) /**< MSIRANGE field mask. */
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#define STM32_MSIRANGE_100K (0 << 4) /**< 100kHz nominal. */
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#define STM32_MSIRANGE_200K (1 << 4) /**< 200kHz nominal. */
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#define STM32_MSIRANGE_400K (2 << 4) /**< 400kHz nominal. */
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#define STM32_MSIRANGE_800K (3 << 4) /**< 800kHz nominal. */
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#define STM32_MSIRANGE_1M (4 << 4) /**< 1MHz nominal. */
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#define STM32_MSIRANGE_2M (5 << 4) /**< 2MHz nominal. */
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#define STM32_MSIRANGE_4M (6 << 4) /**< 4MHz nominal. */
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#define STM32_MSIRANGE_8M (7 << 4) /**< 8MHz nominal. */
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#define STM32_MSIRANGE_16M (8 << 4) /**< 16MHz nominal. */
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#define STM32_MSIRANGE_24M (9 << 4) /**< 24MHz nominal. */
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#define STM32_MSIRANGE_32M (10 << 4) /**< 32MHz nominal. */
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#define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */
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/** @} */
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/**
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@ -124,7 +122,7 @@
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* @{
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*/
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#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
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#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */
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#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI. */
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#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
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#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
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@ -150,13 +148,10 @@
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#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
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#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
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#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
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#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
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#define STM32_MCOSEL_HSI (2 << 24) /**< HSI clock on MCO pin. */
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#define STM32_MCOSEL_MSI (3 << 24) /**< MSI clock on MCO pin. */
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#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */
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#define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */
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#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
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#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
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#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
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@ -170,28 +165,36 @@
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/** @} */
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/**
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* @name RCC_ICSCR register bits definitions
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* @name RCC_PLLCFGR register bits definitions
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* @{
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*/
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#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
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#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */
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#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */
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#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */
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#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */
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#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
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#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
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#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
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#define STM32_PLLSRC_MASK (3 << 16) /**< PLL clock source mask. */
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#define STM32_PLLSRC_NOCLOCK (0 << 16) /**< PLL clock source disabled. */
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#define STM32_PLLSRC_MSI (1 << 16) /**< PLL clock source is MSI. */
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#define STM32_PLLSRC_HSI16 (2 << 16) /**< PLL clock source is HSI16. */
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#define STM32_PLLSRC_HSE (3 << 16) /**< PLL clock source is HSE. */
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/** @} */
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/**
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* @name RCC_BDCR register bits definitions
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* @{
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*/
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#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
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#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
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#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
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#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
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#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
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/** @} */
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/**
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* @name RCC_CSR register bits definitions
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* @{
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*/
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#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
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#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
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#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
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#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
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#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
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#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */
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#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */
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#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */
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#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */
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#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */
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/** @} */
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/*===========================================================================*/
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@ -301,7 +304,7 @@
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* the internal 16MHz HSI clock.
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*/
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#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
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#define STM32_PLLSRC STM32_PLLSRC_HSI
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#define STM32_PLLSRC STM32_PLLSRC_HSI16
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#endif
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/**
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@ -367,13 +370,6 @@
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#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
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#define STM32_RTCSEL STM32_RTCSEL_LSE
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#endif
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/**
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* @brief HSE divider toward RTC setting.
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*/
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#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
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#define STM32_RTCPRE STM32_RTCPRE_DIV2
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#endif
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/** @} */
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/*===========================================================================*/
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@ -458,12 +454,12 @@
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#endif
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#else /* !STM32_HSI_ENABLED */
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#if STM32_ADC_CLOCK_ENABLED || \
|
||||
(STM32_SW == STM32_SW_HSI) || \
|
||||
(STM32_SW == STM32_SW_HSI16) || \
|
||||
((STM32_SW == STM32_SW_PLL) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI)) || \
|
||||
(STM32_MCOSEL == STM32_MCOSEL_HSI) || \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI16)) || \
|
||||
(STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
|
||||
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI))
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI16))
|
||||
#error "required HSI clock is not enabled"
|
||||
#endif
|
||||
#endif /* !STM32_HSI_ENABLED */
|
||||
|
|
@ -578,7 +574,7 @@
|
|||
*/
|
||||
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLCLKIN STM32_HSECLK
|
||||
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
||||
#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
|
||||
#define STM32_PLLCLKIN STM32_HSICLK
|
||||
#else
|
||||
#error "invalid STM32_PLLSRC value specified"
|
||||
|
|
@ -638,7 +634,7 @@
|
|||
#define STM32_SYSCLK 2100000
|
||||
#elif (STM32_SW == STM32_SW_MSI)
|
||||
#define STM32_SYSCLK STM32_MSICLK
|
||||
#elif (STM32_SW == STM32_SW_HSI)
|
||||
#elif (STM32_SW == STM32_SW_HSI16)
|
||||
#define STM32_SYSCLK STM32_HSICLK
|
||||
#elif (STM32_SW == STM32_SW_HSE)
|
||||
#define STM32_SYSCLK STM32_HSECLK
|
||||
|
|
@ -732,7 +728,7 @@
|
|||
*/
|
||||
#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
|
||||
#define STM32_MCODIVCLK 0
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_HSI
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
|
||||
#define STM32_MCODIVCLK STM32_HSICLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_MSI
|
||||
#define STM32_MCODIVCLK STM32_MSICLK
|
||||
|
|
@ -765,21 +761,6 @@
|
|||
#error "invalid STM32_MCOPRE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief HSE divider toward RTC clock.
|
||||
*/
|
||||
#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
|
||||
#define STM32_HSEDIVCLK (STM32_HSECLK / 2)
|
||||
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
|
||||
#define STM32_HSEDIVCLK (STM32_HSECLK / 4)
|
||||
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
|
||||
#define STM32_HSEDIVCLK (STM32_HSECLK / 8)
|
||||
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
|
||||
#define STM32_HSEDIVCLK (STM32_HSECLK / 16)
|
||||
#else
|
||||
#error "invalid STM32_RTCPRE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RTC/LCD clock.
|
||||
*/
|
||||
|
|
@ -790,7 +771,7 @@
|
|||
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
|
||||
#define STM32_RTCCLK STM32_LSICLK
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
||||
#define STM32_RTCCLK STM32_HSEDIVCLK
|
||||
#define STM32_RTCCLK (STM32_HSECLK / 32)
|
||||
#else
|
||||
#error "invalid STM32_RTCSEL value specified"
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue