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Initial commit of I2C driver code 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@2684 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
barthess 2011-01-25 18:59:18 +00:00
parent a1b70ed301
commit 063c6e138d
6 changed files with 689 additions and 184 deletions
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114
Copy of todo.txt
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@ -1,114 +0,0 @@
Status:
- = Planned.
X = In progress, some work done.
* = Done.
? = Not sure if worth the effort or useful at all.
N = Decided against.
Within 2.1.x
* Binary Semaphores on top of Counting Semaphores.
* Direct unbuffered UART driver.
Requirements: low level, callbacks, DMA capable, state machines buildable
on top, support data words greater than 8 bits, callback for
"last byte transmitted (RS485)", simple implementation,
verifiable.
* Rework STM32 drivers to use friendly IRQ names and centralized DMA macros.
* I-class functions for the ADC/PWM drivers.
* All the device driver structures must have a fields extension macro and
initializer hook.
* All the device driver callbacks must have the driver pointer as first
parameter.
* Change the SPI driver to be able to work asynchronously using callbacks,
keep the synchronous APIs available as option.
* Add an optional spiPolledExchange() API to the SPI driver model.
* Update the STM32 SPI driver to the new model.
* Make the ADC driver have the same synchronous/asynchronous API of the
new SPI driver model.
* General HAL improvements.
* Update the AT91SAM7 SPI driver (DMA and/or ISR).
* Verify the FatFs demo on both the AT91SAM7X and AT91SAM7S.
* Update the LPC214x SPI driver (ISR).
* Verify the LPC214x FatFs demo.
* Write a new SPI driver for LPC1xxx (ISR)(it should be very close to the
LPC214x one).
N Evaluate if to add a synchronous API to the UART driver, eventually do so.
* Global documentation reorganization in order to allow both separate documents
and the usual blob document.
* PDF generation from the documentation system (only separate documents, not
the blob).
* Automatic compilation and upload of the various documents on the web site
(doxygen + rsync).
* New STM8S/A SPI driver.
* Reorganization of the STM32 family port-level support.
* Remove preprocessor directives from the assembler files and restore the
RIDE7 build files in the STM32 demo.
* Move dynamic APIs into a separate source file.
* Improved support in the STM32 HAL support for multiple sub-families. Do
not check for the family in the various drivers but simply check for
switch macros like STM32_HAS_USART3, STM32_HAS_SPI3. This what the
drivers will not need changes when adding new sub-families.
* STM8L official HAL support, it will have to be separated from the STM8S/STM8A
HAL because it is very different.
* Shared ISR management.
* STM8L-Discovery demo.
* Add the STM32F100 (Value Line) sub-family to the official STM32 HAL support.
* STM32VL-Discovery demo.
* Remove the PAL default configuration from the various hal_lld.c and move
them into board.c files, this will remove an ugly dependency.
* Realign the STM8 port to the new STM8L one as options, naming conventions
and general solutions.
* Support for more compilers (IAR, Keil, ARMCMx only initially).
X Support for not just Makefiles (Ride7, Crossworks etc).
* IAR port for Cortex-Mx, add demos for all the supported families.
* Keil port for Cortex-Mx, add demos for all the supported families.
* Change the serial drivers to have a single event source instead of three.
Add Rx and Tx to the existing flags mechanism. Move up the flags handling in
the superclass.
X Except for the above, bug fixing only until the 2.2.0 release.
Within 2.3.x (hopefully)
- Resist doing more changes and optimizations to the kernel.
? Make thread functions return void.
- Introduce a "THREAD" function prefix in order to hide compiler-specific
optimizations for thread functions.
X Add an USB abstract device driver class.
X USB driver implementation for STM32F103/STM32F102.
X Add a Serial over USB generic device driver implementing a USB Communication
Device Class and offering a Serial-like interface to the applications.
- Add a switch to enable/disable the priority inheritance algorithm in mutexes.
X File System infrastructure.
- Official FatFs wrapper using the new infrastructure, dedicated test suite.
X Transactional flash file system implementation.
X I2C device driver class support and at least one implementation.
- Serial over UART complex driver driver, evaluate from the performance
results if to make obsolete the current dedicated Serial driver.
X Shared DMA channels support in the STM32/STM8L HALs.
X New device driver models: Clock, Systick, RTC, WDG, DAC, Power Monitor.
- MAC driver for STM32F107 (hardware missing).
- Device drivers for STM8/STM8L (ADC, PWM, bring them on par with STM32).
- Batch testing of the ARM7/ARMCMx port using OpenOCD, with reports.
- Debug-related features and tools.
- Add a *very simple* ADC API for single one shot sampling (implement it as
an injected conversion on the STM32).
- Update C++ wrapper (Heap, Pools, Mailboxes and any new feature).
- Threads Pools manager in the library.
Later but within 2.x.x
- Dedicated TCP/IP stack.
? ISO7816 driver over UART driver, both reader and card side (hardware
missing).
- Merge the Coldfire branch in mainline (hardware missing).
- Merge the H8S branch in mainline (hardware missing).
- MAC driver revision in order to support copy-less operations, this will
require changes to lwIP or a new TCP/IP stack however.
Ideas for 3.x.x:
- MMU/MPU support.
- High resolution timers and tickless kernel.
- Multicore support.
Side projects:
X ChibiOS Wizard, UML modeling and ChibiOS applications code and
documentation generator.
? File System
- Visual debugger/monitor interfaced through OpenOCD.

16
os/hal/include/i2c.h
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@ -34,6 +34,7 @@
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -112,23 +113,20 @@ typedef enum {
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void i2cInit(void);
void i2cObjectInit(I2CDriver *i2cp);
void i2cStart(I2CDriver *i2cp, const I2CConfig *config);
void i2cStart(I2CDriver *i2cp, I2CConfig *config);
void i2cStop(I2CDriver *i2cp);
void i2cMasterStartI(I2CDriver *i2cp,
uint16_t header,
i2ccallback_t callback);
void i2cMasterTransmit(I2CDriver *i2cp, uint8_t slave_addr1, uint8_t slave_addr2, size_t n, const void *txbuf);
void i2cMasterReceive(I2CDriver *i2cp, uint8_t slave_addr1, uint8_t slave_addr2, size_t n, void *rxbuf);
void i2cMasterStartI(I2CDriver *i2cp,uint16_t header,i2ccallback_t callback);
void i2cMasterStopI(I2CDriver *i2cp, i2ccallback_t callback);
void i2cMasterRestartI(I2CDriver *i2cp, i2ccallback_t callback);
void i2cMasterTransmitI(I2CDriver *i2cp, size_t n, const uint8_t *txbuf,
i2ccallback_t callback);
void i2cMasterReceiveI(I2CDriver *i2cp, size_t n, uint8_t *rxbuf,
i2ccallback_t callback);
void i2cMasterTransmitI(I2CDriver *i2cp, size_t n, const uint8_t *txbuf, i2ccallback_t callback);
void i2cMasterReceiveI(I2CDriver *i2cp, size_t n, uint8_t *rxbuf, i2ccallback_t callback);
#if I2C_USE_MUTUAL_EXCLUSION
void i2cAcquireBus(I2CDriver *i2cp);
void i2cReleaseBus(I2CDriver *i2cp);

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os/hal/platforms/STM32/i2c_lld.c Normal file
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/**
* @file STM32/i2c_lld.c
* @brief STM32 I2C subsystem low level driver source. Slave mode not implemented.
* @addtogroup STM32_I2C
* @{
*/
#include "ch.h"
#include "hal.h"
#include "i2c_lld.h"
#if HAL_USE_I2C || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief I2C1 driver identifier.*/
#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
I2CDriver I2CD1;
#endif
/** @brief I2C2 driver identifier.*/
#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
I2CDriver I2CD2;
#endif
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief TODO: Status bits translation.
*
* @param[in] sr USART SR register value
*
* @return The error flags.
*/
static i2cflags_t translate_errors(uint16_t sr) {
i2cflags_t sts = 0;
if (sr & USART_SR_ORE)
sts |= UART_OVERRUN_ERROR;
if (sr & USART_SR_PE)
sts |= UART_PARITY_ERROR;
if (sr & USART_SR_FE)
sts |= UART_FRAMING_ERROR;
if (sr & USART_SR_NE)
sts |= UART_NOISE_ERROR;
if (sr & USART_SR_LBD)
sts |= UART_BREAK_DETECTED;
return sts;
}
static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
}
static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
}
#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
/**
* @brief I2C1 event interrupt handler.
*/
CH_IRQ_HANDLER(VectorBC) {
CH_IRQ_PROLOGUE();
i2c_serve_event_interrupt(&I2CD1);
CH_IRQ_EPILOGUE();
}
/**
* @brief I2C1 error interrupt handler.
*/
CH_IRQ_HANDLER(VectorC0) {
CH_IRQ_PROLOGUE();
i2c_serve_error_interrupt(&I2CD1);
CH_IRQ_EPILOGUE();
}
#endif
#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
/**
* @brief I2C2 event interrupt handler.
*/
CH_IRQ_HANDLER(VectorC4) {
CH_IRQ_PROLOGUE();
i2c_serve_event_interrupt(&I2CD2);
CH_IRQ_EPILOGUE();
}
/**
* @brief I2C2 error interrupt handler.
*/
CH_IRQ_HANDLER(VectorC8) {
CH_IRQ_PROLOGUE();
i2c_serve_error_interrupt(&I2CD2);
CH_IRQ_EPILOGUE();
}
#endif
/**
* @brief Low level I2C driver initialization.
*/
void i2c_lld_init(void) {
#if STM32_I2C_USE_I2C1
RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1
RCC->APB1RSTR = 0;
i2cObjectInit(&I2CD1);
I2CD1.id_i2c = I2C1;
#endif
#if STM32_I2C_USE_I2C2
RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; // reset I2C 2
RCC->APB1RSTR = 0;
i2cObjectInit(&I2CD2);
I2CD2.id_i2c = I2C2;
#endif
}
/**
* @brief Configures and activates the I2C peripheral.
*
* @param[in] i2cp pointer to the @p I2CDriver object
*/
void i2c_lld_start(I2CDriver *i2cp) {
/* If in stopped state then enables the I2C clock.*/
if (i2cp->id_state == I2C_STOP) {
#if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) {
NVICEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
NVICEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // I2C 1 clock enable
}
#endif
#if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) {
NVICEnableVector(I2C2_EV_IRQn, STM32_I2C2_IRQ_PRIORITY);
NVICEnableVector(I2C2_ER_IRQn, STM32_I2C2_IRQ_PRIORITY);
RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; // I2C 2 clock enable
}
#endif
}
/* I2C setup.*/
i2cp->id_i2c->CR1 = I2C_CR1_SWRST; // reset i2c peripherial
i2cp->id_i2c->CR1 = 0;
i2cp->id_i2c->CR1 = i2cp->id_config->i2cc_cr1;
i2cp->id_i2c->CR2 = i2cp->id_config->i2cc_cr2 |
//I2C_CR2_ITERREN |
//I2C_CR2_ITEVTEN |
//I2C_CR2_ITBUFEN |
36; //TODO: replace this by macro calculation
/* TODO:
* 1. macro timing calculator
* 2. parameter checker
* 3. definitions in halconf.h: i2c-freq, i2c_mode, etc
* 4. trise time calculator/checker
*/
i2cp->id_i2c->CCR = i2cp->id_config->i2cc_ccr | 180;
i2cp->id_i2c->TRISE = i2cp->id_config->i2cc_trise | 37;
i2cp->id_i2c->CR1 |= 1; // enable interface
}
/**
* @brief Deactivates the I2C peripheral.
*
* @param[in] i2cp pointer to the @p I2CDriver object
*/
void i2c_lld_stop(I2CDriver *i2cp) {
/* If in ready state then disables the I2C clock.*/
if (i2cp->id_state == I2C_READY) {
#if STM32_I2C_USE_I2C1
if (&I2CD1 == i2cp) {
NVICDisableVector(I2C1_EV_IRQn);
NVICDisableVector(I2C1_ER_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
}
#endif
#if STM32_I2C_USE_I2C2
if (&I2CD2 == i2cp) {
NVICDisableVector(I2C2_EV_IRQn);
NVICDisableVector(I2C2_ER_IRQn);
RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
}
#endif
}
i2cp->id_state = I2C_STOP;
}
/**
* @brief Transmits data ever the I2C bus as master.
* TODO:@details
*
* @param[in] i2cp pointer to the @p I2CDriver object
* @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
* @param[in] restart bool. If TRUE then generate restart condition insted of stop
*/
void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart) {
//TODO: check txbytes <= sizeof(i2cscfg->txbuf) here, or in hylevel API
chSysLock();
int i = 0;
i2cp->id_slave_config = i2cscfg;
i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition
while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)){
i++; // wait start bit
}
i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) | I2C_WRITE; // write slave addres in DR
while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){
i++; // wait Address sent
}
i = i2cp->id_i2c->SR2; // TODO: check is it need to read this register for I2C to proper functionality
i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
// now write data byte by byte in DR register
uint32_t n = 0;
for (n = 0; n < i2cp->id_slave_config->txbytes; n++){
i2cp->id_i2c->DR = i2cscfg->txbuf[n];
while (!(i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
i++;
}
}
while (!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
i++;
}
if (restart){
i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate restart condition
}
else i2cp->id_i2c->CR1 |= I2C_CR1_STOP; // generate stop condition
chSysUnlock();
}
/**
* @brief Receives data from the I2C bus.
* @details To receive data from I2C slave you must sent them some
* control bytes first. Driver takes this data from @p I2CSlaveConfig
* structure (*txbuf and txbytes fields), so you must manually
* fill this fields before invocating receiving function
*
* @param[in] i2cp pointer to the @p I2CDriver object
* @param[in] i2cscfg pointer to the @p I2CSlaveConfig object
*/
void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
chSysLock();
i2cp->id_slave_config = i2cscfg;
uint16_t i = 0;
uint16_t tmp = 0;
// send control secuence to slave
//i2c_lld_master_transmit(i2cp, i2cscfg, TRUE);
i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition
while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)){
i++; // wait start bit
}
i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) | I2C_WRITE; // write slave addres in DR
while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){
i++; // wait Address sent
}
i = i2cp->id_i2c->SR2; // TODO: check is it need to read this register for I2C to proper functionality
i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
// now write data byte by byte in DR register
uint32_t n = 0;
for (n = 0; n < i2cp->id_slave_config->txbytes; n++){
i2cp->id_i2c->DR = i2cscfg->txbuf[n];
while (!(i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
i++;
}
}
while (!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
i++;
}
i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate restart condition
while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)){
i++; // wait start bit
}
// send slave addres with read-bit
i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) | I2C_READ;
while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){
i++; // wait Address sent
}
i = i2cp->id_i2c->SR2; // TODO: check is it need to read this register for I2C to proper functionality
i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
// set ACK bit
i2cp->id_i2c->CR1 |= I2C_CR1_ACK;
// collect data from slave
for (i = 0; i < i2cp->id_slave_config->rxbytes; i++){
if ((i2cp->id_slave_config->rxbytes - i) == 1){ // TODO: is it better <= in place of == ?
// clear ACK bit for automatically send NACK
i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);}
while (!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){
tmp++;
}
i2cp->id_slave_config->rxbuf[i] = i2cp->id_i2c->DR;
}
// generate STOP
i2cp->id_i2c->CR1 |= I2C_CR1_STOP;
chSysUnlock();
}
#endif // HAL_USE_I2C

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/**
* @file STM32/i2c_lld.h
* @brief STM32 I2C subsystem low level driver header.
* @addtogroup STM32_I2C
* @{
*/
#ifndef _I2C_LLD_H_
#define _I2C_LLD_H_
#if HAL_USE_I2C || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief I2C1 driver enable switch.
* @details If set to @p TRUE the support for I2C1 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
#define STM32_I2C_USE_I2C1 TRUE
#endif
/**
* @brief I2C2 driver enable switch.
* @details If set to @p TRUE the support for I2C2 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
#define STM32_I2C_USE_I2C2 TRUE
#endif
/**
* @brief I2C1 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
*/
#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C1_IRQ_PRIORITY 0xA0
#endif
/**
* @brief I2C2 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
*/
#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C2_IRQ_PRIORITY 0xA0
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/** @brief No pending conditions.*/
#define I2C_NO_ERROR 0
/*@brief external Stop or Start condition during an address or a data transfer*/
#define I2C_BUS_ERROR 1
/** @brief */
#define I2C_ARBITRATION_LOSS 2
/** @brief */
#define I2C_ACK_FAIL 4
/** @brief */
#define I2C_OVERRUN_UNDERRUN 8
/** @brief */
#define I2C_PEC_ERROR 16
/** @brief */
#define I2C_TIMEOUT 32
/** @brief */
#define I2C_SMBUS_ALERT 64
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief I2C notification callback type.
*
* @param[in] i2cp FIXME: pointer to the @p I2CDriver object triggering the
* callback
*/
typedef void (*i2ccallback_t)(void);
/**
* @brief I2C error notification callback type.
*
* @param[in] i2cp FIXME: pointer to the @p I2CDriver object triggering the
* callback
*/
typedef void (*i2cerrorcallback_t)(void);
/**
* @brief Driver configuration structure.
*/
typedef struct {
/**
* @brief I2C initialization data.
*/
uint16_t i2cc_cr1;
uint16_t i2cc_cr2;
uint16_t i2cc_ccr;
uint16_t i2cc_trise;
} I2CConfig;
/**
* @brief TODO:
*/
typedef uint32_t i2cflags_t;
/**
* @brief TODO:
*/
typedef uint8_t i2cblock_t;
/**
* @brief Structure representing an I2C slave configuration.
* @details Each slave has its own data buffers, adress, and error flags.
*/
typedef struct {
/**
* @brief Callback pointer.
* @note TODO: I don't know, when this callback is inwoked
* @p NULL then the callback is disabled.
*/
i2ccallback_t id_callback;
/**
* @brief Callback pointer.
* @note TODO: I don't know, when this callback is inwoked
* @p NULL then the callback is disabled.
*/
i2cerrorcallback_t id_errcallback;
i2cblock_t *rxbuf; // pointer to buffer
size_t rxdepth;// depth of buffer
size_t rxbytes;// count of bytes to sent in one sending
i2cblock_t *txbuf;
size_t txdepth;
size_t txbytes;
uint8_t slave_addr1; // 7-bit address of the slave
uint8_t slave_addr2; // used in 10-bit address mode
uint16_t error_flags;
}I2CSlaveConfig;
/**
* @brief Structure representing an I2C driver.
*/
typedef struct {
/**
* @brief Driver state.
*/
i2cstate_t id_state;
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
Mutex id_mutex;
#elif CH_USE_SEMAPHORES
Semaphore id_semaphore;
#endif
#endif /* I2C_USE_MUTUAL_EXCLUSION */
/**
* @brief Current configuration data.
*/
I2CConfig *id_config;
/**
* @brief Current slave configuration data.
*/
I2CSlaveConfig *id_slave_config;
/* End of the mandatory fields.*/
/**
* @brief Thread waiting for I/O completion.
*/
Thread *id_thread;
/**
* @brief Pointer to the I2Cx registers block.
*/
I2C_TypeDef *id_i2c;
} I2CDriver;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/** @cond never*/
#if STM32_I2C_USE_I2C1
extern I2CDriver I2CD1;
#endif
#if STM32_I2C_USE_I2C2
extern I2CDriver I2CD2;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void i2c_lld_init(void);
void i2c_lld_start(I2CDriver *i2cp);
void i2c_lld_stop(I2CDriver *i2cp);
void i2c_lld_master_start(I2CDriver *i2cp, uint16_t header);
void i2c_lld_master_stop(I2CDriver *i2cp);
void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart);
void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
//static i2cflags_t translate_errors(uint16_t sr);
#ifdef __cplusplus
}
#endif
/** @endcond*/
#endif // CH_HAL_USE_I2C
#endif // _I2C_LLD_H_

3
os/hal/platforms/STM32/platform.mk
View File

@ -7,7 +7,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/stm32_dma.c
${CHIBIOS}/os/hal/platforms/STM32/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32

163
os/hal/src/i2c.c
View File

@ -54,7 +54,6 @@
* @init
*/
void i2cInit(void) {
i2c_lld_init();
}
@ -67,8 +66,9 @@ void i2cInit(void) {
*/
void i2cObjectInit(I2CDriver *i2cp) {
i2cp->i2c_state = I2C_STOP;
i2cp->i2c_config = NULL;
i2cp->id_state = I2C_STOP;
i2cp->id_config = NULL;
i2cp->id_slave_config = NULL;
#if defined(I2C_DRIVER_EXT_INIT_HOOK)
I2C_DRIVER_EXT_INIT_HOOK(i2cp);
#endif
@ -82,17 +82,17 @@ void i2cObjectInit(I2CDriver *i2cp) {
*
* @api
*/
void i2cStart(I2CDriver *i2cp, const I2CConfig *config) {
void i2cStart(I2CDriver *i2cp, I2CConfig *config) {
chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart");
chSysLock();
chDbgAssert((i2cp->i2c_state == I2C_STOP) || (i2cp->i2c_state == I2C_READY),
chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),
"i2cStart(), #1",
"invalid state");
i2cp->i2c_config = config;
i2cp->id_config = config;
i2c_lld_start(i2cp);
i2cp->i2c_state = I2C_READY;
i2cp->id_state = I2C_READY;
chSysUnlock();
}
@ -108,13 +108,56 @@ void i2cStop(I2CDriver *i2cp) {
chDbgCheck(i2cp != NULL, "i2cStop");
chSysLock();
chDbgAssert((i2cp->i2c_state == I2C_STOP) || (i2cp->i2c_state == I2C_READY),
chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),
"i2cStop(), #1",
"invalid state");
i2c_lld_stop(i2cp);
i2cp->i2c_state = I2C_STOP;
i2cp->id_state = I2C_STOP;
chSysUnlock();
}
/**
* @brief Sends data ever the I2C bus.
*
* @param[in] i2cp pointer to the @p I2CDriver object
* @param[in] slave_addr1 7-bit address of the slave
* @param[in] slave_addr1 used in 10-bit address mode
* @param[in] n number of words to send
* @param[in] txbuf the pointer to the transmit buffer
*
*/
void i2cMasterTransmit(I2CDriver *i2cp, uint8_t slave_addr1, uint8_t slave_addr2, size_t n, const void *txbuf) {
chDbgCheck((i2cp != NULL) && (n > 0) && (txbuf != NULL),
"i2cSend");
chDbgAssert(i2cp->id_state == I2C_READY,
"i2cSend(), #1",
"not active");
//i2c_lld_master_transmit(i2cp, slave_addr1, slave_addr2, n, txbuf);
}
/**
* @brief Receives data from the I2C bus.
*
* @param[in] i2cp pointer to the @p I2CDriver object
* @param[in] slave_addr1 7-bit address of the slave
* @param[in] slave_addr1 used in 10-bit address mode
* @param[in] n number of words to receive
* @param[out] rxbuf the pointer to the receive buffer
*
*/
void i2cMasterReceive(I2CDriver *i2cp, uint8_t slave_addr1, uint8_t slave_addr2, size_t n, void *rxbuf) {
chDbgCheck((i2cp != NULL) && (n > 0) && (rxbuf != NULL),
"i2cReceive");
chDbgAssert(i2cp->id_state == I2C_READY,
"i2cReceive(), #1",
"not active");
//i2c_lld_master_receive(i2cp, slave_addr1, slave_addr2, n, rxbuf);
}
/**
* @brief Initiates a master bus transaction.
@ -127,17 +170,17 @@ void i2cStop(I2CDriver *i2cp) {
*
* @iclass
*/
void i2cMasterStartI(I2CDriver *i2cp,
uint16_t header,
i2ccallback_t callback) {
chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterStartI");
chDbgAssert(i2cp->i2c_state == I2C_READY,
"i2cMasterStartI(), #1", "invalid state");
i2cp->id_callback = callback;
i2c_lld_master_start(i2cp, header);
}
//void i2cMasterStartI(I2CDriver *i2cp,
// uint16_t header,
// i2ccallback_t callback) {
//
// chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterStartI");
// chDbgAssert(i2cp->id_state == I2C_READY,
// "i2cMasterStartI(), #1", "invalid state");
//
// i2cp->id_callback = callback;
// i2c_lld_master_start(i2cp, header);
//}
/**
* @brief Terminates a master bus transaction.
@ -147,15 +190,15 @@ void i2cMasterStartI(I2CDriver *i2cp,
*
* @iclass
*/
void i2cMasterStopI(I2CDriver *i2cp, i2ccallback_t callback) {
chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterStopI");
chDbgAssert(i2cp->i2c_state == I2C_MREADY,
"i2cMasterStopI(), #1", "invalid state");
i2cp->id_callback = callback;
i2c_lld_master_stop(i2cp);
}
//void i2cMasterStopI(I2CDriver *i2cp, i2ccallback_t callback) {
//
// chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterStopI");
// chDbgAssert(i2cp->id_state == I2C_MREADY,
// "i2cMasterStopI(), #1", "invalid state");
//
// i2cp->id_callback = callback;
// i2c_lld_master_stop(i2cp);
//}
/**
@ -167,15 +210,15 @@ void i2cMasterStopI(I2CDriver *i2cp, i2ccallback_t callback) {
*
* @iclass
*/
void i2cMasterRestartI(I2CDriver *i2cp, i2ccallback_t callback) {
chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterRestartI");
chDbgAssert(i2cp->i2c_state == I2C_MREADY,
"i2cMasterRestartI(), #1", "invalid state");
i2cp->id_callback = callback;
i2c_lld_master_restart(i2cp);
}
//void i2cMasterRestartI(I2CDriver *i2cp, i2ccallback_t callback) {
//
// chDbgCheck((i2cp != NULL) && (callback != NULL), "i2cMasterRestartI");
// chDbgAssert(i2cp->id_state == I2C_MREADY,
// "i2cMasterRestartI(), #1", "invalid state");
//
// i2cp->id_callback = callback;
// i2c_lld_master_restart(i2cp);
//}
/**
* @brief Master transmission.
@ -187,17 +230,17 @@ void i2cMasterRestartI(I2CDriver *i2cp, i2ccallback_t callback) {
*
* @iclass
*/
void i2cMasterTransmitI(I2CDriver *i2cp, size_t n, const uint8_t *txbuf,
i2ccallback_t callback) {
chDbgCheck((i2cp != NULL) && (n > 0) &&
(txbuf != NULL) && (callback != NULL), "i2cMasterTransmitI");
chDbgAssert(i2cp->i2c_state == I2C_MREADY,
"i2cMasterTransmitI(), #1", "invalid state");
i2cp->id_callback = callback;
i2c_lld_master_transmit(i2cp, n, txbuf);
}
//void i2cMasterTransmitI(I2CDriver *i2cp, size_t n, const uint8_t *txbuf,
// i2ccallback_t callback) {
//
// chDbgCheck((i2cp != NULL) && (n > 0) &&
// (txbuf != NULL) && (callback != NULL), "i2cMasterTransmitI");
// chDbgAssert(i2cp->id_state == I2C_MREADY,
// "i2cMasterTransmitI(), #1", "invalid state");
//
// i2cp->id_callback = callback;
// i2c_lld_master_transmit(i2cp, n, txbuf);
//}
/**
* @brief Master receive.
@ -209,17 +252,17 @@ void i2cMasterTransmitI(I2CDriver *i2cp, size_t n, const uint8_t *txbuf,
*
* @iclass
*/
void i2cMasterReceiveI(I2CDriver *i2cp, size_t n, uint8_t *rxbuf,
i2ccallback_t callback) {
chDbgCheck((i2cp != NULL) && (n > 0) &&
(rxbuf != NULL) && (callback != NULL), "i2cMasterReceiveI");
chDbgAssert(i2cp->i2c_state == I2C_MREADY,
"i2cMasterReceiveI(), #1", "invalid state");
i2cp->id_callback = callback;
i2c_lld_master_receive(i2cp, n, rxbuf);
}
//void i2cMasterReceiveI(I2CDriver *i2cp, size_t n, uint8_t *rxbuf,
// i2ccallback_t callback) {
//
// chDbgCheck((i2cp != NULL) && (n > 0) &&
// (rxbuf != NULL) && (callback != NULL), "i2cMasterReceiveI");
// chDbgAssert(i2cp->id_state == I2C_MREADY,
// "i2cMasterReceiveI(), #1", "invalid state");
//
// i2cp->id_callback = callback;
// i2c_lld_master_receive(i2cp, n, rxbuf);
//}
#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
/**