diff --git a/os/common/ext/Artery/AT32F4xx/at32f435xx.h b/os/common/ext/Artery/AT32F4xx/at32f435xx.h
new file mode 100644
index 000000000..50315d381
--- /dev/null
+++ b/os/common/ext/Artery/AT32F4xx/at32f435xx.h
@@ -0,0 +1,17123 @@
+/**
+ ******************************************************************************
+ * @file stm32f437xx.h
+ * @author MCD Application Team
+ * @version V2.6.1
+ * @date 14-February-2017
+ * @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f437xx
+ * @{
+ */
+
+#ifndef __AT32F435xx_H
+#define __AT32F435xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_at32f4xx.h"
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1;
+ __IO uint32_t MACDBGR;
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+/* Reserved on AT32F435/7 */
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+/* Reserved on AT32F435/7 */
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+/* Legacy define */
+#define ADC_BASE ADC123_COMMON_BASE
+/* Reserved on AT32F435/7 */
+//#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+/* Only on AT32F435/7 */
+#define TIM20_BASE (APB2PERIPH_BASE + 0x4C00U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+
+/* Only on AT32F435/7 */
+#define EMAC_BAS (AHB1PERIPH_BASE + 0x8000U)
+#define SDIO_BASE (AHB1PERIPH_BASE + 0xC400U)
+
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC ADC123_COMMON
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!© COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __AT32F4xx_H
+#define __AT32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+ /* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+ STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+ /* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.6.1
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(AT32F435xx) || defined(AT32F437xx)
+ #include "at32f435xx.h"
+#else
+ #error "Please select first the target AT32F4xx device used in your application (in at32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __AT32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/common/ext/Artery/AT32F4xx/system_at32f4xx.h b/os/common/ext/Artery/AT32F4xx/system_at32f4xx.h
new file mode 100644
index 000000000..06309051c
--- /dev/null
+++ b/os/common/ext/Artery/AT32F4xx/system_at32f4xx.h
@@ -0,0 +1,124 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.6.1
+ * @date 14-February-2017
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f4xx.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f4xx.mk
new file mode 100644
index 000000000..e33f7bcf6
--- /dev/null
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f4xx.mk
@@ -0,0 +1,18 @@
+# List of the ChibiOS generic AT32F4xx startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
+
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+ $(CHIBIOS)/os/common/startup/ARMCMx/devices/AT32F4xx \
+ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
+ $(CHIBIOS)/os/common/ext/Artery/AT32F4xx
+
+STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/devices/AT32F4xx/cmparams.h b/os/common/startup/ARMCMx/devices/AT32F4xx/cmparams.h
new file mode 100644
index 000000000..efbd434f5
--- /dev/null
+++ b/os/common/startup/ARMCMx/devices/AT32F4xx/cmparams.h
@@ -0,0 +1,88 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32F4xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F4xx platform.
+ * @{
+ */
+
+#ifndef CMPARAMS_H
+#define CMPARAMS_H
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL 4
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(AT32F435xx) && !defined(AT32F437xx)
+#include "board.h"
+#endif
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 104
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "at32f4xx.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+ unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_M
+#error "CMSIS __CORTEX_M mismatch"
+#endif
+
+#if CORTEX_HAS_FPU != __FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+/*lint -restore*/
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CMPARAMS_H */
+
+/** @} */
diff --git a/os/hal/ports/AT32/AT32F4xx/at32_registry.h b/os/hal/ports/AT32/AT32F4xx/at32_registry.h
index 7e5a209a3..df7004a58 100644
--- a/os/hal/ports/AT32/AT32F4xx/at32_registry.h
+++ b/os/hal/ports/AT32/AT32F4xx/at32_registry.h
@@ -22,57 +22,15 @@
* @{
*/
-#ifndef STM32_REGISTRY_H
-#define STM32_REGISTRY_H
+#ifndef AT32_REGISTRY_H
+#define AT32_REGISTRY_H
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define STM32F469_479xx
-#define STM32F4XX
-
-#elif defined(STM32F446xx)
-#define STM32F4XX
-
-#elif defined(STM32F439xx) || defined(STM32F429xx)
-#define STM32F429_439xx
-#define STM32F4XX
-
-#elif defined(STM32F437xx) || defined(STM32F427xx)
+#if defined(AT32F437xx) || defined(AT32F435xx)
#define STM32F427_437xx
#define STM32F4XX
-#elif defined(STM32F413xx)
-#define STM32F413xx
-#define STM32F4XX
-
-#elif defined(STM32F412Cx) || defined(STM32F412Rx) || \
- defined(STM32F412Vx) || defined(STM32F412Zx)
-#define STM32F412xx
-#define STM32F4XX
-
-#elif defined(STM32F411xE)
-#define STM32F411xx
-#define STM32F4XX
-
-#elif defined(STM32F410Cx) || defined(STM32F410Rx) || \
- defined(STM32F410Tx)
-#define STM32F410xx
-#define STM32F4XX
-
-#elif defined(STM32F405xx) || defined(STM32F415xx) || \
- defined(STM32F407xx) || defined(STM32F417xx)
-#define STM32F40_41xxx
-#define STM32F4XX
-
-#elif defined(STM32F401xC) || defined(STM32F401xE)
-#define STM32F401xx
-#define STM32F4XX
-
-#elif defined(STM32F205xx) || defined(STM32F215xx) || \
- defined(STM32F207xx) || defined(STM32F217xx)
-#define STM32F2XX
-
#else
-#error "STM32F2xx/F4xx device not specified"
+#error "Artery AT32F4xx device not specified"
#endif
/*===========================================================================*/
@@ -117,745 +75,7 @@
} while (false)
/*===========================================================================*/
-/* STM32F469xx, STM32F479xx. */
-/*===========================================================================*/
-
-#if defined(STM32F469_479xx) || defined(__DOXYGEN__)
-
-/* Clock tree attributes.*/
-#define STM32_HAS_RCC_PLLSAI TRUE
-#define STM32_HAS_RCC_PLLI2S TRUE
-#define STM32_HAS_RCC_DCKCFGR TRUE
-#define STM32_HAS_RCC_DCKCFGR2 FALSE
-#define STM32_HAS_RCC_I2SSRC TRUE
-#define STM32_HAS_RCC_I2SPLLSRC FALSE
-#define STM32_HAS_RCC_CK48MSEL TRUE
-#define STM32_RCC_CK48MSEL_USES_I2S FALSE
-#define STM32_PLL48CLK_ALTSRC STM32_PLLSAI_Q_CLKOUT
-#define STM32_TIMPRE_PRESCALE4 TRUE
-
-/* ADC attributes.*/
-#define STM32_ADC_HANDLER Vector88
-#define STM32_ADC_NUMBER 18
-
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 TRUE
-#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN 0x00001100
-
-#define STM32_HAS_ADC3 TRUE
-#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 1))
-#define STM32_ADC3_DMA_CHN 0x00000022
-
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_HAS_CAN3 FALSE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 TRUE
-#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_DAC1_CH1_DMA_CHN 0x00700000
-
-#define STM32_HAS_DAC1_CH2 TRUE
-#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_DAC1_CH2_DMA_CHN 0x07000000
-
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_DMA_CACHE_HANDLING FALSE
-#define STM32_DMA_SUPPORTS_DMAMUX FALSE
-
-#define STM32_HAS_DMA1 TRUE
-#define STM32_DMA1_CH0_HANDLER Vector6C
-#define STM32_DMA1_CH1_HANDLER Vector70
-#define STM32_DMA1_CH2_HANDLER Vector74
-#define STM32_DMA1_CH3_HANDLER Vector78
-#define STM32_DMA1_CH4_HANDLER Vector7C
-#define STM32_DMA1_CH5_HANDLER Vector80
-#define STM32_DMA1_CH6_HANDLER Vector84
-#define STM32_DMA1_CH7_HANDLER VectorFC
-#define STM32_DMA1_CH0_NUMBER 11
-#define STM32_DMA1_CH1_NUMBER 12
-#define STM32_DMA1_CH2_NUMBER 13
-#define STM32_DMA1_CH3_NUMBER 14
-#define STM32_DMA1_CH4_NUMBER 15
-#define STM32_DMA1_CH5_NUMBER 16
-#define STM32_DMA1_CH6_NUMBER 17
-#define STM32_DMA1_CH7_NUMBER 47
-
-#define STM32_HAS_DMA2 TRUE
-#define STM32_DMA2_CH0_HANDLER Vector120
-#define STM32_DMA2_CH1_HANDLER Vector124
-#define STM32_DMA2_CH2_HANDLER Vector128
-#define STM32_DMA2_CH3_HANDLER Vector12C
-#define STM32_DMA2_CH4_HANDLER Vector130
-#define STM32_DMA2_CH5_HANDLER Vector150
-#define STM32_DMA2_CH6_HANDLER Vector154
-#define STM32_DMA2_CH7_HANDLER Vector158
-#define STM32_DMA2_CH0_NUMBER 56
-#define STM32_DMA2_CH1_NUMBER 57
-#define STM32_DMA2_CH2_NUMBER 58
-#define STM32_DMA2_CH3_NUMBER 59
-#define STM32_DMA2_CH4_NUMBER 60
-#define STM32_DMA2_CH5_NUMBER 68
-#define STM32_DMA2_CH6_NUMBER 69
-#define STM32_DMA2_CH7_NUMBER 70
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH TRUE
-#define STM32_ETH_HANDLER Vector134
-#define STM32_ETH_NUMBER 61
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR1_MASK 0x00000000U
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOI TRUE
-#define STM32_HAS_GPIOJ TRUE
-#define STM32_HAS_GPIOK TRUE
-
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | \
- RCC_AHB1ENR_GPIOFEN | \
- RCC_AHB1ENR_GPIOGEN | \
- RCC_AHB1ENR_GPIOHEN | \
- RCC_AHB1ENR_GPIOIEN | \
- RCC_AHB1ENR_GPIOJEN | \
- RCC_AHB1ENR_GPIOKEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_I2C3_RX_DMA_CHN 0x00000300
-#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_I2C3_TX_DMA_CHN 0x00030000
-
-#define STM32_HAS_I2C4 FALSE
-
-/* QUADSPI attributes.*/
-#define STM32_HAS_QUADSPI1 TRUE
-#define STM32_QUADSPI1_HANDLER Vector1AC
-#define STM32_QUADSPI1_NUMBER 91
-#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_QUADSPI1_DMA_CHN 0x30000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_SUPPORTS_I2S TRUE
-#define STM32_SPI1_I2S_FULLDUPLEX TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_SUPPORTS_I2S TRUE
-#define STM32_SPI2_I2S_FULLDUPLEX TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_SUPPORTS_I2S TRUE
-#define STM32_SPI3_I2S_FULLDUPLEX TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_SUPPORTS_I2S FALSE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI4_RX_DMA_CHN 0x00005004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-
-#define STM32_HAS_SPI5 TRUE
-#define STM32_SPI5_SUPPORTS_I2S FALSE
-#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI5_RX_DMA_CHN 0x00702000
-#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI5_TX_DMA_CHN 0x07020000
-
-#define STM32_HAS_SPI6 TRUE
-#define STM32_SPI6_SUPPORTS_I2S FALSE
-#define STM32_SPI6_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6)
-#define STM32_SPI6_RX_DMA_CHN 0x01000000
-#define STM32_SPI6_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
-#define STM32_SPI6_TX_DMA_CHN 0x00100000
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM6 TRUE
-#define STM32_TIM6_IS_32BITS FALSE
-#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM7 TRUE
-#define STM32_TIM7_IS_32BITS FALSE
-#define STM32_TIM7_CHANNELS 0
-
-#define STM32_HAS_TIM8 TRUE
-#define STM32_TIM8_IS_32BITS FALSE
-#define STM32_TIM8_CHANNELS 4
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 1
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 1
-
-#define STM32_HAS_TIM12 TRUE
-#define STM32_TIM12_IS_32BITS FALSE
-#define STM32_TIM12_CHANNELS 2
-
-#define STM32_HAS_TIM13 TRUE
-#define STM32_TIM13_IS_32BITS FALSE
-#define STM32_TIM13_CHANNELS 1
-
-#define STM32_HAS_TIM14 TRUE
-#define STM32_TIM14_IS_32BITS FALSE
-#define STM32_TIM14_CHANNELS 1
-
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_USART3_RX_DMA_CHN 0x00000040
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
- STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_UART4_RX_DMA_CHN 0x00000400
-#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_UART4_TX_DMA_CHN 0x00040000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
-#define STM32_UART5_RX_DMA_CHN 0x00000004
-#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_UART5_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-#define STM32_HAS_UART7 TRUE
-#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_UART7_RX_DMA_CHN 0x00005000
-#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_UART7_TX_DMA_CHN 0x00000050
-
-#define STM32_HAS_UART8 TRUE
-#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_UART8_RX_DMA_CHN 0x05000000
-#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
-#define STM32_UART8_TX_DMA_CHN 0x00000005
-
-#define STM32_HAS_UART9 FALSE
-#define STM32_HAS_UART10 FALSE
-#define STM32_HAS_LPUART1 FALSE
-
-/* USB attributes.*/
-#define STM32_OTG_STEPPING 2
-#define STM32_HAS_OTG1 TRUE
-#define STM32_OTG1_ENDPOINTS 5
-#define STM32_HAS_OTG2 TRUE
-#define STM32_OTG2_ENDPOINTS 7
-
-#define STM32_HAS_USB FALSE
-
-/* IWDG attributes.*/
-#define STM32_HAS_IWDG TRUE
-#define STM32_IWDG_IS_WINDOWED FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC TRUE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D TRUE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC TRUE
-#define STM32_FSMC_IS_FMC TRUE
-#define STM32_FSMC_HANDLER Vector100
-#define STM32_FSMC_NUMBER 48
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F469_479xx) */
-
-/*===========================================================================*/
-/* STM32F446xx. */
-/*===========================================================================*/
-
-#if defined(STM32F446xx)
-
-/* Clock tree attributes.*/
-#define STM32_HAS_RCC_PLLSAI TRUE
-#define STM32_HAS_RCC_PLLI2S TRUE
-#define STM32_HAS_RCC_DCKCFGR TRUE
-#define STM32_HAS_RCC_DCKCFGR2 TRUE
-#define STM32_HAS_RCC_I2SSRC FALSE
-#define STM32_HAS_RCC_I2SPLLSRC FALSE
-#define STM32_HAS_RCC_CK48MSEL TRUE
-#define STM32_RCC_CK48MSEL_USES_I2S FALSE
-#define STM32_PLL48CLK_ALTSRC STM32_PLLSAI_P_CLKOUT
-#define STM32_TIMPRE_PRESCALE4 TRUE
-
-/* ADC attributes.*/
-#define STM32_ADC_HANDLER Vector88
-#define STM32_ADC_NUMBER 18
-
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 TRUE
-#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN 0x00001100
-
-#define STM32_HAS_ADC3 TRUE
-#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 1))
-#define STM32_ADC3_DMA_CHN 0x00000022
-
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_HAS_CAN3 FALSE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 TRUE
-#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_DAC1_CH1_DMA_CHN 0x00700000
-
-#define STM32_HAS_DAC1_CH2 TRUE
-#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_DAC1_CH2_DMA_CHN 0x07000000
-
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_DMA_CACHE_HANDLING FALSE
-#define STM32_DMA_SUPPORTS_DMAMUX FALSE
-
-#define STM32_HAS_DMA1 TRUE
-#define STM32_DMA1_CH0_HANDLER Vector6C
-#define STM32_DMA1_CH1_HANDLER Vector70
-#define STM32_DMA1_CH2_HANDLER Vector74
-#define STM32_DMA1_CH3_HANDLER Vector78
-#define STM32_DMA1_CH4_HANDLER Vector7C
-#define STM32_DMA1_CH5_HANDLER Vector80
-#define STM32_DMA1_CH6_HANDLER Vector84
-#define STM32_DMA1_CH7_HANDLER VectorFC
-#define STM32_DMA1_CH0_NUMBER 11
-#define STM32_DMA1_CH1_NUMBER 12
-#define STM32_DMA1_CH2_NUMBER 13
-#define STM32_DMA1_CH3_NUMBER 14
-#define STM32_DMA1_CH4_NUMBER 15
-#define STM32_DMA1_CH5_NUMBER 16
-#define STM32_DMA1_CH6_NUMBER 17
-#define STM32_DMA1_CH7_NUMBER 47
-
-#define STM32_HAS_DMA2 TRUE
-#define STM32_DMA2_CH0_HANDLER Vector120
-#define STM32_DMA2_CH1_HANDLER Vector124
-#define STM32_DMA2_CH2_HANDLER Vector128
-#define STM32_DMA2_CH3_HANDLER Vector12C
-#define STM32_DMA2_CH4_HANDLER Vector130
-#define STM32_DMA2_CH5_HANDLER Vector150
-#define STM32_DMA2_CH6_HANDLER Vector154
-#define STM32_DMA2_CH7_HANDLER Vector158
-#define STM32_DMA2_CH0_NUMBER 56
-#define STM32_DMA2_CH1_NUMBER 57
-#define STM32_DMA2_CH2_NUMBER 58
-#define STM32_DMA2_CH3_NUMBER 59
-#define STM32_DMA2_CH4_NUMBER 60
-#define STM32_DMA2_CH5_NUMBER 68
-#define STM32_DMA2_CH6_NUMBER 69
-#define STM32_DMA2_CH7_NUMBER 70
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR1_MASK 0x00000000U
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOI FALSE
-#define STM32_HAS_GPIOJ FALSE
-#define STM32_HAS_GPIOK FALSE
-
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | \
- RCC_AHB1ENR_GPIOFEN | \
- RCC_AHB1ENR_GPIOGEN | \
- RCC_AHB1ENR_GPIOHEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_I2C3_RX_DMA_CHN 0x00000300
-#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_I2C3_TX_DMA_CHN 0x00030000
-
-#define STM32_HAS_I2C4 FALSE
-
-/* QUADSPI attributes.*/
-#define STM32_HAS_QUADSPI1 TRUE
-#define STM32_QUADSPI1_HANDLER Vector1B0
-#define STM32_QUADSPI1_NUMBER 92
-#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_QUADSPI1_DMA_CHN 0x30000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_SUPPORTS_I2S TRUE
-#define STM32_SPI1_I2S_FULLDUPLEX FALSE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_SUPPORTS_I2S TRUE
-#define STM32_SPI2_I2S_FULLDUPLEX FALSE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_SUPPORTS_I2S TRUE
-#define STM32_SPI3_I2S_FULLDUPLEX FALSE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_SUPPORTS_I2S FALSE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI4_RX_DMA_CHN 0x00005004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM6 TRUE
-#define STM32_TIM6_IS_32BITS FALSE
-#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM7 TRUE
-#define STM32_TIM7_IS_32BITS FALSE
-#define STM32_TIM7_CHANNELS 0
-
-#define STM32_HAS_TIM8 TRUE
-#define STM32_TIM8_IS_32BITS FALSE
-#define STM32_TIM8_CHANNELS 4
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 1
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 1
-
-#define STM32_HAS_TIM12 TRUE
-#define STM32_TIM12_IS_32BITS FALSE
-#define STM32_TIM12_CHANNELS 2
-
-#define STM32_HAS_TIM13 TRUE
-#define STM32_TIM13_IS_32BITS FALSE
-#define STM32_TIM13_CHANNELS 1
-
-#define STM32_HAS_TIM14 TRUE
-#define STM32_TIM14_IS_32BITS FALSE
-#define STM32_TIM14_CHANNELS 1
-
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_USART3_RX_DMA_CHN 0x00000040
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
- STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_UART4_RX_DMA_CHN 0x00000400
-#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_UART4_TX_DMA_CHN 0x00040000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
-#define STM32_UART5_RX_DMA_CHN 0x00000004
-#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_UART5_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-#define STM32_HAS_UART7 FALSE
-#define STM32_HAS_UART8 FALSE
-#define STM32_HAS_UART9 FALSE
-#define STM32_HAS_UART10 FALSE
-#define STM32_HAS_LPUART1 FALSE
-
-/* USB attributes.*/
-#define STM32_OTG_STEPPING 2
-#define STM32_HAS_OTG1 TRUE
-#define STM32_OTG1_ENDPOINTS 5
-#define STM32_HAS_OTG2 TRUE
-#define STM32_OTG2_ENDPOINTS 7
-
-#define STM32_HAS_USB FALSE
-
-/* IWDG attributes.*/
-#define STM32_HAS_IWDG TRUE
-#define STM32_IWDG_IS_WINDOWED FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC TRUE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D TRUE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC TRUE
-#define STM32_FSMC_IS_FMC TRUE
-#define STM32_FSMC_HANDLER Vector100
-#define STM32_FSMC_NUMBER 48
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F446xx) */
-
-/*===========================================================================*/
-/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */
+/* AT32F435xx, AT32F437xx */
/*===========================================================================*/
#if defined(STM32F429_439xx) || defined(STM32F427_437xx)
@@ -1232,1967 +452,6 @@
#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
-/*===========================================================================*/
-/* STM32F413xx. */
-/*===========================================================================*/
-
-#if defined(STM32F413xx)
-
-/* Clock tree attributes.*/
-#define STM32_HAS_RCC_PLLSAI FALSE
-#define STM32_HAS_RCC_PLLI2S TRUE
-#define STM32_HAS_RCC_DCKCFGR TRUE
-#define STM32_HAS_RCC_DCKCFGR2 TRUE
-#define STM32_HAS_RCC_I2SSRC FALSE
-#define STM32_HAS_RCC_I2SPLLSRC TRUE
-#define STM32_HAS_RCC_CK48MSEL TRUE
-#define STM32_RCC_CK48MSEL_USES_I2S TRUE
-#define STM32_PLL48CLK_ALTSRC STM32_PLLI2S_Q_CLKOUT
-#define STM32_TIMPRE_PRESCALE4 FALSE
-
-/* ADC attributes.*/
-#define STM32_ADC_HANDLER Vector88
-#define STM32_ADC_NUMBER 18
-
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 FALSE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_HAS_CAN3 TRUE
-#define STM32_CAN_MAX_FILTERS 28
-#define STM32_CAN3_MAX_FILTERS 14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 TRUE
-#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_DAC1_CH1_DMA_CHN 0x00700000
-
-#define STM32_HAS_DAC1_CH2 TRUE
-#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_DAC1_CH2_DMA_CHN 0x07000000
-
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_DMA_CACHE_HANDLING FALSE
-#define STM32_DMA_SUPPORTS_DMAMUX FALSE
-
-#define STM32_HAS_DMA1 TRUE
-#define STM32_DMA1_CH0_HANDLER Vector6C
-#define STM32_DMA1_CH1_HANDLER Vector70
-#define STM32_DMA1_CH2_HANDLER Vector74
-#define STM32_DMA1_CH3_HANDLER Vector78
-#define STM32_DMA1_CH4_HANDLER Vector7C
-#define STM32_DMA1_CH5_HANDLER Vector80
-#define STM32_DMA1_CH6_HANDLER Vector84
-#define STM32_DMA1_CH7_HANDLER VectorFC
-#define STM32_DMA1_CH0_NUMBER 11
-#define STM32_DMA1_CH1_NUMBER 12
-#define STM32_DMA1_CH2_NUMBER 13
-#define STM32_DMA1_CH3_NUMBER 14
-#define STM32_DMA1_CH4_NUMBER 15
-#define STM32_DMA1_CH5_NUMBER 16
-#define STM32_DMA1_CH6_NUMBER 17
-#define STM32_DMA1_CH7_NUMBER 47
-
-#define STM32_HAS_DMA2 TRUE
-#define STM32_DMA2_CH0_HANDLER Vector120
-#define STM32_DMA2_CH1_HANDLER Vector124
-#define STM32_DMA2_CH2_HANDLER Vector128
-#define STM32_DMA2_CH3_HANDLER Vector12C
-#define STM32_DMA2_CH4_HANDLER Vector130
-#define STM32_DMA2_CH5_HANDLER Vector150
-#define STM32_DMA2_CH6_HANDLER Vector154
-#define STM32_DMA2_CH7_HANDLER Vector158
-#define STM32_DMA2_CH0_NUMBER 56
-#define STM32_DMA2_CH1_NUMBER 57
-#define STM32_DMA2_CH2_NUMBER 58
-#define STM32_DMA2_CH3_NUMBER 59
-#define STM32_DMA2_CH4_NUMBER 60
-#define STM32_DMA2_CH5_NUMBER 68
-#define STM32_DMA2_CH6_NUMBER 69
-#define STM32_DMA2_CH7_NUMBER 70
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR1_MASK 0x00000000U
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOI FALSE
-#define STM32_HAS_GPIOJ FALSE
-#define STM32_HAS_GPIOK FALSE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | \
- RCC_AHB1ENR_GPIOFEN | \
- RCC_AHB1ENR_GPIOGEN | \
- RCC_AHB1ENR_GPIOHEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C3_RX_DMA_CHN 0x00000310
-#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C3_TX_DMA_CHN 0x00630000
-
-#define STM32_HAS_I2C4 TRUE
-#define STM32_I2C4_SUPPORTS_FMP TRUE
-#define STM32_HAS_I2C4 TRUE
-#define STM32_I2C4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_I2C4_RX_DMA_CHN 0x00001000
-#define STM32_I2C4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_I2C4_TX_DMA_CHN 0x00000020
-
-/* QUADSPI attributes.*/
-#define STM32_HAS_QUADSPI1 TRUE
-#define STM32_QUADSPI1_HANDLER Vector1B0
-#define STM32_QUADSPI1_NUMBER 92
-#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_QUADSPI1_DMA_CHN 0x30000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_SUPPORTS_I2S TRUE
-#define STM32_SPI1_I2S_FULLDUPLEX TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303200
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_SUPPORTS_I2S TRUE
-#define STM32_SPI2_I2S_FULLDUPLEX TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_SUPPORTS_I2S TRUE
-#define STM32_SPI3_I2S_FULLDUPLEX TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_SUPPORTS_I2S TRUE
-#define STM32_SPI4_I2S_FULLDUPLEX TRUE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_RX_DMA_CHN 0x00045004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-
-#define STM32_HAS_SPI5 TRUE
-#define STM32_SPI5_SUPPORTS_I2S TRUE
-#define STM32_SPI5_I2S_FULLDUPLEX TRUE
-#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI5_RX_DMA_CHN 0x00702000
-#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
- STM32_DMA_STREAM_ID_MSK(2, 5) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI5_TX_DMA_CHN 0x07520000
-
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM6 TRUE
-#define STM32_TIM6_IS_32BITS FALSE
-#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM7 TRUE
-#define STM32_TIM7_IS_32BITS FALSE
-#define STM32_TIM7_CHANNELS 0
-
-#define STM32_HAS_TIM8 TRUE
-#define STM32_TIM8_IS_32BITS FALSE
-#define STM32_TIM8_CHANNELS 4
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 1
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 1
-
-#define STM32_HAS_TIM12 TRUE
-#define STM32_TIM12_IS_32BITS FALSE
-#define STM32_TIM12_CHANNELS 2
-
-#define STM32_HAS_TIM13 TRUE
-#define STM32_TIM13_IS_32BITS FALSE
-#define STM32_TIM13_CHANNELS 1
-
-#define STM32_HAS_TIM14 TRUE
-#define STM32_TIM14_IS_32BITS FALSE
-#define STM32_TIM14_CHANNELS 1
-
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-#define STM32_HAS_LPTIM1 TRUE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_USART3_RX_DMA_CHN 0x00000040
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
- STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_UART4_RX_DMA_CHN 0x00000400
-#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_UART4_TX_DMA_CHN 0x00040000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
-#define STM32_UART5_RX_DMA_CHN 0x00000004
-#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_UART5_TX_DMA_CHN 0x80000000
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-#define STM32_HAS_UART7 TRUE
-#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_UART7_RX_DMA_CHN 0x00005000
-#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_UART7_TX_DMA_CHN 0x00000050
-
-#define STM32_HAS_UART8 TRUE
-#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_UART8_RX_DMA_CHN 0x05000000
-#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
-#define STM32_UART8_TX_DMA_CHN 0x00000005
-
-#define STM32_HAS_UART9 TRUE
-#define STM32_UART9_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_UART9_RX_DMA_CHN 0x00000000
-#define STM32_UART9_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 0)
-#define STM32_UART9_TX_DMA_CHN 0x00000001
-
-#define STM32_HAS_UART10 TRUE
-#define STM32_UART10_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 0)
-#define STM32_UART10_RX_DMA_CHN 0x00000005
-#define STM32_UART10_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_UART10_TX_DMA_CHN 0x60000000
-
-#define STM32_HAS_LPUART1 FALSE
-
-/* USB attributes.*/
-#define STM32_OTG_STEPPING 2
-#define STM32_HAS_OTG1 TRUE
-#define STM32_OTG1_ENDPOINTS 5
-
-#define STM32_HAS_OTG2 FALSE
-#define STM32_HAS_USB FALSE
-
-/* IWDG attributes.*/
-#define STM32_HAS_IWDG TRUE
-#define STM32_IWDG_IS_WINDOWED FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC FALSE
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F413xx) */
-
-/*===========================================================================*/
-/* STM32F412xx. */
-/*===========================================================================*/
-
-#if defined(STM32F412xx)
-
-/* Clock tree attributes.*/
-#define STM32_HAS_RCC_PLLSAI FALSE
-#define STM32_HAS_RCC_PLLI2S TRUE
-#define STM32_HAS_RCC_DCKCFGR TRUE
-#define STM32_HAS_RCC_DCKCFGR2 TRUE
-#define STM32_HAS_RCC_I2SSRC FALSE
-#define STM32_HAS_RCC_I2SPLLSRC TRUE
-#define STM32_HAS_RCC_CK48MSEL TRUE
-#define STM32_RCC_CK48MSEL_USES_I2S TRUE
-#define STM32_PLL48CLK_ALTSRC STM32_PLLI2S_Q_CLKOUT
-#define STM32_TIMPRE_PRESCALE4 FALSE
-
-/* ADC attributes.*/
-#define STM32_ADC_HANDLER Vector88
-#define STM32_ADC_NUMBER 18
-
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 FALSE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_HAS_CAN3 FALSE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_HAS_DAC1_CH2 FALSE
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_DMA_CACHE_HANDLING FALSE
-#define STM32_DMA_SUPPORTS_DMAMUX FALSE
-
-#define STM32_HAS_DMA1 TRUE
-#define STM32_DMA1_CH0_HANDLER Vector6C
-#define STM32_DMA1_CH1_HANDLER Vector70
-#define STM32_DMA1_CH2_HANDLER Vector74
-#define STM32_DMA1_CH3_HANDLER Vector78
-#define STM32_DMA1_CH4_HANDLER Vector7C
-#define STM32_DMA1_CH5_HANDLER Vector80
-#define STM32_DMA1_CH6_HANDLER Vector84
-#define STM32_DMA1_CH7_HANDLER VectorFC
-#define STM32_DMA1_CH0_NUMBER 11
-#define STM32_DMA1_CH1_NUMBER 12
-#define STM32_DMA1_CH2_NUMBER 13
-#define STM32_DMA1_CH3_NUMBER 14
-#define STM32_DMA1_CH4_NUMBER 15
-#define STM32_DMA1_CH5_NUMBER 16
-#define STM32_DMA1_CH6_NUMBER 17
-#define STM32_DMA1_CH7_NUMBER 47
-
-#define STM32_HAS_DMA2 TRUE
-#define STM32_DMA2_CH0_HANDLER Vector120
-#define STM32_DMA2_CH1_HANDLER Vector124
-#define STM32_DMA2_CH2_HANDLER Vector128
-#define STM32_DMA2_CH3_HANDLER Vector12C
-#define STM32_DMA2_CH4_HANDLER Vector130
-#define STM32_DMA2_CH5_HANDLER Vector150
-#define STM32_DMA2_CH6_HANDLER Vector154
-#define STM32_DMA2_CH7_HANDLER Vector158
-#define STM32_DMA2_CH0_NUMBER 56
-#define STM32_DMA2_CH1_NUMBER 57
-#define STM32_DMA2_CH2_NUMBER 58
-#define STM32_DMA2_CH3_NUMBER 59
-#define STM32_DMA2_CH4_NUMBER 60
-#define STM32_DMA2_CH5_NUMBER 68
-#define STM32_DMA2_CH6_NUMBER 69
-#define STM32_DMA2_CH7_NUMBER 70
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR1_MASK 0x00000000U
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOI FALSE
-#define STM32_HAS_GPIOJ FALSE
-#define STM32_HAS_GPIOK FALSE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | \
- RCC_AHB1ENR_GPIOFEN | \
- RCC_AHB1ENR_GPIOGEN | \
- RCC_AHB1ENR_GPIOHEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
- STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C3_RX_DMA_CHN 0x00000310
-#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C3_TX_DMA_CHN 0x00630000
-
-#define STM32_HAS_I2C4 FALSE
-
-/* QUADSPI attributes.*/
-#define STM32_HAS_QUADSPI1 TRUE
-#define STM32_QUADSPI1_HANDLER Vector1B0
-#define STM32_QUADSPI1_NUMBER 92
-#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_QUADSPI1_DMA_CHN 0x30000000
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_SUPPORTS_I2S TRUE
-#define STM32_SPI1_I2S_FULLDUPLEX TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_SUPPORTS_I2S TRUE
-#define STM32_SPI2_I2S_FULLDUPLEX TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_SUPPORTS_I2S TRUE
-#define STM32_SPI3_I2S_FULLDUPLEX TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_SUPPORTS_I2S TRUE
-#define STM32_SPI4_I2S_FULLDUPLEX TRUE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_RX_DMA_CHN 0x00045004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-
-#define STM32_HAS_SPI5 TRUE
-#define STM32_SPI5_SUPPORTS_I2S TRUE
-#define STM32_SPI5_I2S_FULLDUPLEX TRUE
-#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI5_RX_DMA_CHN 0x00702000
-#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
- STM32_DMA_STREAM_ID_MSK(2, 5) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI5_TX_DMA_CHN 0x07520000
-
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM6 TRUE
-#define STM32_TIM6_IS_32BITS FALSE
-#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM7 TRUE
-#define STM32_TIM7_IS_32BITS FALSE
-#define STM32_TIM7_CHANNELS 0
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 1
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 1
-
-#define STM32_HAS_TIM12 TRUE
-#define STM32_TIM12_IS_32BITS FALSE
-#define STM32_TIM12_CHANNELS 2
-
-#define STM32_HAS_TIM13 TRUE
-#define STM32_TIM13_IS_32BITS FALSE
-#define STM32_TIM13_CHANNELS 1
-
-#define STM32_HAS_TIM14 TRUE
-#define STM32_TIM14_IS_32BITS FALSE
-#define STM32_TIM14_CHANNELS 1
-
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_USART3_RX_DMA_CHN 0x00000040
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
- STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074000
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-#define STM32_HAS_UART4 FALSE
-#define STM32_HAS_UART5 FALSE
-#define STM32_HAS_UART7 FALSE
-#define STM32_HAS_UART8 FALSE
-#define STM32_HAS_UART9 FALSE
-#define STM32_HAS_UART10 FALSE
-#define STM32_HAS_LPUART1 FALSE
-
-/* USB attributes.*/
-#define STM32_OTG_STEPPING 2
-#define STM32_HAS_OTG1 TRUE
-#define STM32_OTG1_ENDPOINTS 5
-
-#define STM32_HAS_OTG2 FALSE
-#define STM32_HAS_USB FALSE
-
-/* IWDG attributes.*/
-#define STM32_HAS_IWDG TRUE
-#define STM32_IWDG_IS_WINDOWED FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC FALSE
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F412xx) */
-
-/*===========================================================================*/
-/* STM32F411xx. */
-/*===========================================================================*/
-
-#if defined(STM32F411xx)
-
-/* Clock tree attributes.*/
-#define STM32_HAS_RCC_PLLSAI FALSE
-#define STM32_HAS_RCC_PLLI2S TRUE
-#define STM32_HAS_RCC_DCKCFGR TRUE
-#define STM32_HAS_RCC_DCKCFGR2 FALSE
-#define STM32_HAS_RCC_I2SSRC TRUE
-#define STM32_HAS_RCC_I2SPLLSRC FALSE
-#define STM32_HAS_RCC_CK48MSEL FALSE
-#define STM32_RCC_CK48MSEL_USES_I2S FALSE
-#define STM32_PLL48CLK_ALTSRC STM32_PLLSAI_Q_CLKOUT
-#define STM32_TIMPRE_PRESCALE4 FALSE
-
-/* ADC attributes.*/
-#define STM32_ADC_HANDLER Vector88
-#define STM32_ADC_NUMBER 18
-
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 FALSE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 FALSE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_HAS_CAN3 FALSE
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_HAS_DAC1_CH2 FALSE
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_DMA_CACHE_HANDLING FALSE
-#define STM32_DMA_SUPPORTS_DMAMUX FALSE
-
-#define STM32_HAS_DMA1 TRUE
-#define STM32_DMA1_CH0_HANDLER Vector6C
-#define STM32_DMA1_CH1_HANDLER Vector70
-#define STM32_DMA1_CH2_HANDLER Vector74
-#define STM32_DMA1_CH3_HANDLER Vector78
-#define STM32_DMA1_CH4_HANDLER Vector7C
-#define STM32_DMA1_CH5_HANDLER Vector80
-#define STM32_DMA1_CH6_HANDLER Vector84
-#define STM32_DMA1_CH7_HANDLER VectorFC
-#define STM32_DMA1_CH0_NUMBER 11
-#define STM32_DMA1_CH1_NUMBER 12
-#define STM32_DMA1_CH2_NUMBER 13
-#define STM32_DMA1_CH3_NUMBER 14
-#define STM32_DMA1_CH4_NUMBER 15
-#define STM32_DMA1_CH5_NUMBER 16
-#define STM32_DMA1_CH6_NUMBER 17
-#define STM32_DMA1_CH7_NUMBER 47
-
-#define STM32_HAS_DMA2 TRUE
-#define STM32_DMA2_CH0_HANDLER Vector120
-#define STM32_DMA2_CH1_HANDLER Vector124
-#define STM32_DMA2_CH2_HANDLER Vector128
-#define STM32_DMA2_CH3_HANDLER Vector12C
-#define STM32_DMA2_CH4_HANDLER Vector130
-#define STM32_DMA2_CH5_HANDLER Vector150
-#define STM32_DMA2_CH6_HANDLER Vector154
-#define STM32_DMA2_CH7_HANDLER Vector158
-#define STM32_DMA2_CH0_NUMBER 56
-#define STM32_DMA2_CH1_NUMBER 57
-#define STM32_DMA2_CH2_NUMBER 58
-#define STM32_DMA2_CH3_NUMBER 59
-#define STM32_DMA2_CH4_NUMBER 60
-#define STM32_DMA2_CH5_NUMBER 68
-#define STM32_DMA2_CH6_NUMBER 69
-#define STM32_DMA2_CH7_NUMBER 70
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR1_MASK 0x00000000U
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOI FALSE
-#define STM32_HAS_GPIOJ FALSE
-#define STM32_HAS_GPIOK FALSE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | \
- RCC_AHB1ENR_GPIOHEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6) |\
- STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
-+ STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C3_RX_DMA_CHN 0x00000310
-#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
-+ STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C3_TX_DMA_CHN 0x00630000
-
-#define STM32_HAS_I2C4 FALSE
-
-/* QUADSPI attributes.*/
-#define STM32_HAS_QUADSPI1 FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_SUPPORTS_I2S TRUE
-#define STM32_SPI1_I2S_FULLDUPLEX TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_SUPPORTS_I2S TRUE
-#define STM32_SPI2_I2S_FULLDUPLEX TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_SUPPORTS_I2S TRUE
-#define STM32_SPI3_I2S_FULLDUPLEX TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_SUPPORTS_I2S TRUE
-#define STM32_SPI4_I2S_FULLDUPLEX TRUE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI4_RX_DMA_CHN 0x00005004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-
-#define STM32_HAS_SPI5 TRUE
-#define STM32_SPI5_SUPPORTS_I2S TRUE
-#define STM32_SPI5_I2S_FULLDUPLEX TRUE
-#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI5_RX_DMA_CHN 0x00702000
-#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI5_TX_DMA_CHN 0x07020000
-
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 1
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 1
-
-#define STM32_HAS_TIM6 FALSE
-#define STM32_HAS_TIM7 FALSE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 FALSE
-#define STM32_HAS_UART4 FALSE
-#define STM32_HAS_UART5 FALSE
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-#define STM32_HAS_UART7 FALSE
-#define STM32_HAS_UART8 FALSE
-#define STM32_HAS_UART9 FALSE
-#define STM32_HAS_UART10 FALSE
-#define STM32_HAS_LPUART1 FALSE
-
-/* USB attributes.*/
-#define STM32_OTG_STEPPING 1
-#define STM32_HAS_OTG1 TRUE
-#define STM32_OTG1_ENDPOINTS 3
-
-#define STM32_HAS_OTG2 FALSE
-#define STM32_HAS_USB FALSE
-
-/* IWDG attributes.*/
-#define STM32_HAS_IWDG TRUE
-#define STM32_IWDG_IS_WINDOWED FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC FALSE
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F411xx) */
-
-/*===========================================================================*/
-/* STM32F410xx. */
-/*===========================================================================*/
-
-#if defined(STM32F410xx)
-
-/* Clock tree attributes.*/
-#define STM32_HAS_RCC_PLLSAI FALSE
-#define STM32_HAS_RCC_PLLI2S FALSE
-#define STM32_HAS_RCC_DCKCFGR TRUE
-#define STM32_HAS_RCC_DCKCFGR2 TRUE
-#define STM32_HAS_RCC_I2SSRC FALSE
-#define STM32_HAS_RCC_I2SPLLSRC FALSE
-#define STM32_HAS_RCC_CK48MSEL FALSE
-#define STM32_RCC_CK48MSEL_USES_I2S FALSE
-#define STM32_PLL48CLK_ALTSRC STM32_PLLSAI_Q_CLKOUT
-#define STM32_TIMPRE_PRESCALE4 FALSE
-
-/* ADC attributes.*/
-#define STM32_ADC_HANDLER Vector88
-#define STM32_ADC_NUMBER 18
-
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 FALSE
-#define STM32_HAS_ADC3 FALSE
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 FALSE
-#define STM32_HAS_CAN2 FALSE
-#define STM32_HAS_CAN3 FALSE
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 TRUE
-#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_DAC1_CH1_DMA_CHN 0x00700000
-
-#define STM32_HAS_DAC1_CH2 FALSE
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_DMA_CACHE_HANDLING FALSE
-#define STM32_DMA_SUPPORTS_DMAMUX FALSE
-
-#define STM32_HAS_DMA1 TRUE
-#define STM32_DMA1_CH0_HANDLER Vector6C
-#define STM32_DMA1_CH1_HANDLER Vector70
-#define STM32_DMA1_CH2_HANDLER Vector74
-#define STM32_DMA1_CH3_HANDLER Vector78
-#define STM32_DMA1_CH4_HANDLER Vector7C
-#define STM32_DMA1_CH5_HANDLER Vector80
-#define STM32_DMA1_CH6_HANDLER Vector84
-#define STM32_DMA1_CH7_HANDLER VectorFC
-#define STM32_DMA1_CH0_NUMBER 11
-#define STM32_DMA1_CH1_NUMBER 12
-#define STM32_DMA1_CH2_NUMBER 13
-#define STM32_DMA1_CH3_NUMBER 14
-#define STM32_DMA1_CH4_NUMBER 15
-#define STM32_DMA1_CH5_NUMBER 16
-#define STM32_DMA1_CH6_NUMBER 17
-#define STM32_DMA1_CH7_NUMBER 47
-
-#define STM32_HAS_DMA2 TRUE
-#define STM32_DMA2_CH0_HANDLER Vector120
-#define STM32_DMA2_CH1_HANDLER Vector124
-#define STM32_DMA2_CH2_HANDLER Vector128
-#define STM32_DMA2_CH3_HANDLER Vector12C
-#define STM32_DMA2_CH4_HANDLER Vector130
-#define STM32_DMA2_CH5_HANDLER Vector150
-#define STM32_DMA2_CH6_HANDLER Vector154
-#define STM32_DMA2_CH7_HANDLER Vector158
-#define STM32_DMA2_CH0_NUMBER 56
-#define STM32_DMA2_CH1_NUMBER 57
-#define STM32_DMA2_CH2_NUMBER 58
-#define STM32_DMA2_CH3_NUMBER 59
-#define STM32_DMA2_CH4_NUMBER 60
-#define STM32_DMA2_CH5_NUMBER 68
-#define STM32_DMA2_CH6_NUMBER 69
-#define STM32_DMA2_CH7_NUMBER 70
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR1_MASK 0x00000000U
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD FALSE
-#define STM32_HAS_GPIOE FALSE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOI FALSE
-#define STM32_HAS_GPIOJ FALSE
-#define STM32_HAS_GPIOK FALSE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIOHEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 FALSE
-
-#define STM32_HAS_I2C4 TRUE
-#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C4_RX_DMA_CHN 0x00002007
-#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) |\
- STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_I2C4_TX_DMA_CHN 0x00040020
-
-/* QUADSPI attributes.*/
-#define STM32_HAS_QUADSPI1 FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_SUPPORTS_I2S TRUE
-#define STM32_SPI1_I2S_FULLDUPLEX TRUE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI1_TX_DMA_CHN 0x00003200
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_SUPPORTS_I2S TRUE
-#define STM32_SPI2_I2S_FULLDUPLEX TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI5 TRUE
-#define STM32_SPI5_SUPPORTS_I2S TRUE
-#define STM32_SPI5_I2S_FULLDUPLEX TRUE
-#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI5_RX_DMA_CHN 0x00702000
-#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SPI5_TX_DMA_CHN 0x07020000
-
-#define STM32_HAS_SPI3 FALSE
-#define STM32_HAS_SPI4 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM6 TRUE
-#define STM32_TIM6_IS_32BITS FALSE
-#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 1
-
-#define STM32_HAS_TIM2 FALSE
-#define STM32_HAS_TIM3 FALSE
-#define STM32_HAS_TIM4 FALSE
-#define STM32_HAS_TIM7 FALSE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM10 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_USART2_RX_DMA_CHN 0x60400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 FALSE
-#define STM32_HAS_UART4 FALSE
-#define STM32_HAS_UART5 FALSE
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-#define STM32_HAS_UART7 FALSE
-#define STM32_HAS_UART8 FALSE
-#define STM32_HAS_UART9 FALSE
-#define STM32_HAS_UART10 FALSE
-#define STM32_HAS_LPUART1 FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB FALSE
-#define STM32_HAS_OTG1 FALSE
-#define STM32_HAS_OTG2 FALSE
-
-/* IWDG attributes.*/
-#define STM32_HAS_IWDG TRUE
-#define STM32_IWDG_IS_WINDOWED FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC FALSE
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F410xx) */
-
-/*===========================================================================*/
-/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx, */
-/* STM32F215xx, STM32F207xx, STM32F217xx. */
-/*===========================================================================*/
-
-#if defined(STM32F40_41xxx) || defined(STM32F2XX)
-
-/* Clock tree attributes.*/
-#define STM32_HAS_RCC_PLLSAI FALSE
-#define STM32_HAS_RCC_PLLI2S TRUE
-#define STM32_HAS_RCC_DCKCFGR FALSE
-#define STM32_HAS_RCC_DCKCFGR2 FALSE
-#define STM32_HAS_RCC_I2SSRC TRUE
-#define STM32_HAS_RCC_I2SPLLSRC FALSE
-#define STM32_HAS_RCC_CK48MSEL FALSE
-#define STM32_RCC_CK48MSEL_USES_I2S FALSE
-#define STM32_TIMPRE_PRESCALE4 TRUE
-
-/* ADC attributes.*/
-#define STM32_ADC_HANDLER Vector88
-#define STM32_ADC_NUMBER 18
-
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 TRUE
-#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN 0x00001100
-
-#define STM32_HAS_ADC3 TRUE
-#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 1))
-#define STM32_ADC3_DMA_CHN 0x00000022
-
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_HAS_CAN3 FALSE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 TRUE
-#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_DAC1_CH1_DMA_CHN 0x00700000
-
-#define STM32_HAS_DAC1_CH2 TRUE
-#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_DAC1_CH2_DMA_CHN 0x07000000
-
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_DMA_CACHE_HANDLING FALSE
-#define STM32_DMA_SUPPORTS_DMAMUX FALSE
-
-#define STM32_HAS_DMA1 TRUE
-#define STM32_DMA1_CH0_HANDLER Vector6C
-#define STM32_DMA1_CH1_HANDLER Vector70
-#define STM32_DMA1_CH2_HANDLER Vector74
-#define STM32_DMA1_CH3_HANDLER Vector78
-#define STM32_DMA1_CH4_HANDLER Vector7C
-#define STM32_DMA1_CH5_HANDLER Vector80
-#define STM32_DMA1_CH6_HANDLER Vector84
-#define STM32_DMA1_CH7_HANDLER VectorFC
-#define STM32_DMA1_CH0_NUMBER 11
-#define STM32_DMA1_CH1_NUMBER 12
-#define STM32_DMA1_CH2_NUMBER 13
-#define STM32_DMA1_CH3_NUMBER 14
-#define STM32_DMA1_CH4_NUMBER 15
-#define STM32_DMA1_CH5_NUMBER 16
-#define STM32_DMA1_CH6_NUMBER 17
-#define STM32_DMA1_CH7_NUMBER 47
-
-#define STM32_HAS_DMA2 TRUE
-#define STM32_DMA2_CH0_HANDLER Vector120
-#define STM32_DMA2_CH1_HANDLER Vector124
-#define STM32_DMA2_CH2_HANDLER Vector128
-#define STM32_DMA2_CH3_HANDLER Vector12C
-#define STM32_DMA2_CH4_HANDLER Vector130
-#define STM32_DMA2_CH5_HANDLER Vector150
-#define STM32_DMA2_CH6_HANDLER Vector154
-#define STM32_DMA2_CH7_HANDLER Vector158
-#define STM32_DMA2_CH0_NUMBER 56
-#define STM32_DMA2_CH1_NUMBER 57
-#define STM32_DMA2_CH2_NUMBER 58
-#define STM32_DMA2_CH3_NUMBER 59
-#define STM32_DMA2_CH4_NUMBER 60
-#define STM32_DMA2_CH5_NUMBER 68
-#define STM32_DMA2_CH6_NUMBER 69
-#define STM32_DMA2_CH7_NUMBER 70
-
-/* ETH attributes.*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F205xx) || \
- defined(STM32F215xx)
-#define STM32_HAS_ETH FALSE
-#else
-#define STM32_HAS_ETH TRUE
-#define STM32_ETH_HANDLER Vector134
-#define STM32_ETH_NUMBER 61
-#endif
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR1_MASK 0x00000000U
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF TRUE
-#define STM32_HAS_GPIOG TRUE
-#define STM32_HAS_GPIOI TRUE
-#define STM32_HAS_GPIOJ FALSE
-#define STM32_HAS_GPIOK FALSE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN | \
- RCC_AHB1ENR_GPIOFEN | \
- RCC_AHB1ENR_GPIOGEN | \
- RCC_AHB1ENR_GPIOHEN | \
- RCC_AHB1ENR_GPIOIEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_I2C3_RX_DMA_CHN 0x00000300
-#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_I2C3_TX_DMA_CHN 0x00030000
-
-#define STM32_HAS_I2C4 FALSE
-
-/* QUADSPI attributes.*/
-#define STM32_HAS_QUADSPI1 FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_SUPPORTS_I2S FALSE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_SUPPORTS_I2S TRUE
-#define STM32_SPI2_I2S_FULLDUPLEX TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_SUPPORTS_I2S TRUE
-#define STM32_SPI3_I2S_FULLDUPLEX TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 FALSE
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM6 TRUE
-#define STM32_TIM6_IS_32BITS FALSE
-#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM7 TRUE
-#define STM32_TIM7_IS_32BITS FALSE
-#define STM32_TIM7_CHANNELS 0
-
-#define STM32_HAS_TIM8 TRUE
-#define STM32_TIM8_IS_32BITS FALSE
-#define STM32_TIM8_CHANNELS 6
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 1
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 1
-
-#define STM32_HAS_TIM12 TRUE
-#define STM32_TIM12_IS_32BITS FALSE
-#define STM32_TIM12_CHANNELS 2
-
-#define STM32_HAS_TIM13 TRUE
-#define STM32_TIM13_IS_32BITS FALSE
-#define STM32_TIM13_CHANNELS 1
-
-#define STM32_HAS_TIM14 TRUE
-#define STM32_TIM14_IS_32BITS FALSE
-#define STM32_TIM14_CHANNELS 1
-
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 TRUE
-#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
-#define STM32_USART3_RX_DMA_CHN 0x00000040
-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
- STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074000
-
-#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_UART4_RX_DMA_CHN 0x00000400
-#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_UART4_TX_DMA_CHN 0x00040000
-
-#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
-#define STM32_UART5_RX_DMA_CHN 0x00000004
-#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_UART5_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-#define STM32_HAS_UART7 FALSE
-#define STM32_HAS_UART8 FALSE
-#define STM32_HAS_UART9 FALSE
-#define STM32_HAS_UART10 FALSE
-#define STM32_HAS_LPUART1 FALSE
-
-/* USB attributes.*/
-#define STM32_OTG_STEPPING 1
-#define STM32_HAS_OTG1 TRUE
-#define STM32_OTG1_ENDPOINTS 3
-#define STM32_HAS_OTG2 TRUE
-#define STM32_OTG2_ENDPOINTS 5
-
-#define STM32_HAS_USB FALSE
-
-/* IWDG attributes.*/
-#define STM32_HAS_IWDG TRUE
-#define STM32_IWDG_IS_WINDOWED FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC TRUE
-#define STM32_FSMC_IS_FMC FALSE
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */
-
-/*===========================================================================*/
-/* STM32F401xx. */
-/*===========================================================================*/
-
-#if defined(STM32F401xx)
-
-/* Clock tree attributes.*/
-#define STM32_HAS_RCC_PLLSAI FALSE
-#define STM32_HAS_RCC_PLLI2S FALSE
-#define STM32_HAS_RCC_DCKCFGR TRUE
-#define STM32_HAS_RCC_DCKCFGR2 FALSE
-#define STM32_HAS_RCC_I2SSRC FALSE
-#define STM32_HAS_RCC_I2SPLLSRC FALSE
-#define STM32_HAS_RCC_CK48MSEL FALSE
-#define STM32_RCC_CK48MSEL_USES_I2S FALSE
-#define STM32_TIMPRE_PRESCALE4 FALSE
-
-/* ADC attributes.*/
-#define STM32_ADC_HANDLER Vector88
-#define STM32_ADC_NUMBER 18
-
-#define STM32_HAS_ADC1 TRUE
-#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_ADC1_DMA_CHN 0x00000000
-
-#define STM32_HAS_ADC2 TRUE
-#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_ADC2_DMA_CHN 0x00001100
-
-#define STM32_HAS_ADC3 TRUE
-#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 1))
-#define STM32_ADC3_DMA_CHN 0x00000022
-
-#define STM32_HAS_ADC4 FALSE
-
-#define STM32_HAS_SDADC1 FALSE
-#define STM32_HAS_SDADC2 FALSE
-#define STM32_HAS_SDADC3 FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1 TRUE
-#define STM32_HAS_CAN2 TRUE
-#define STM32_HAS_CAN3 FALSE
-#define STM32_CAN_MAX_FILTERS 28
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_HAS_DAC1_CH2 FALSE
-#define STM32_HAS_DAC2_CH1 FALSE
-#define STM32_HAS_DAC2_CH2 FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA TRUE
-#define STM32_DMA_CACHE_HANDLING FALSE
-#define STM32_DMA_SUPPORTS_DMAMUX FALSE
-
-#define STM32_HAS_DMA1 TRUE
-#define STM32_DMA1_CH0_HANDLER Vector6C
-#define STM32_DMA1_CH1_HANDLER Vector70
-#define STM32_DMA1_CH2_HANDLER Vector74
-#define STM32_DMA1_CH3_HANDLER Vector78
-#define STM32_DMA1_CH4_HANDLER Vector7C
-#define STM32_DMA1_CH5_HANDLER Vector80
-#define STM32_DMA1_CH6_HANDLER Vector84
-#define STM32_DMA1_CH7_HANDLER VectorFC
-#define STM32_DMA1_CH0_NUMBER 11
-#define STM32_DMA1_CH1_NUMBER 12
-#define STM32_DMA1_CH2_NUMBER 13
-#define STM32_DMA1_CH3_NUMBER 14
-#define STM32_DMA1_CH4_NUMBER 15
-#define STM32_DMA1_CH5_NUMBER 16
-#define STM32_DMA1_CH6_NUMBER 17
-#define STM32_DMA1_CH7_NUMBER 47
-
-#define STM32_HAS_DMA2 TRUE
-#define STM32_DMA2_CH0_HANDLER Vector120
-#define STM32_DMA2_CH1_HANDLER Vector124
-#define STM32_DMA2_CH2_HANDLER Vector128
-#define STM32_DMA2_CH3_HANDLER Vector12C
-#define STM32_DMA2_CH4_HANDLER Vector130
-#define STM32_DMA2_CH5_HANDLER Vector150
-#define STM32_DMA2_CH6_HANDLER Vector154
-#define STM32_DMA2_CH7_HANDLER Vector158
-#define STM32_DMA2_CH0_NUMBER 56
-#define STM32_DMA2_CH1_NUMBER 57
-#define STM32_DMA2_CH2_NUMBER 58
-#define STM32_DMA2_CH3_NUMBER 59
-#define STM32_DMA2_CH4_NUMBER 60
-#define STM32_DMA2_CH5_NUMBER 68
-#define STM32_DMA2_CH6_NUMBER 69
-#define STM32_DMA2_CH7_NUMBER 70
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_LINES 23
-#define STM32_EXTI_IMR1_MASK 0x00000000U
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA TRUE
-#define STM32_HAS_GPIOB TRUE
-#define STM32_HAS_GPIOC TRUE
-#define STM32_HAS_GPIOD TRUE
-#define STM32_HAS_GPIOE TRUE
-#define STM32_HAS_GPIOH TRUE
-#define STM32_HAS_GPIOF FALSE
-#define STM32_HAS_GPIOG FALSE
-#define STM32_HAS_GPIOI FALSE
-#define STM32_HAS_GPIOJ FALSE
-#define STM32_HAS_GPIOK FALSE
-#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
- RCC_AHB1ENR_GPIOBEN | \
- RCC_AHB1ENR_GPIOCEN | \
- RCC_AHB1ENR_GPIODEN | \
- RCC_AHB1ENR_GPIOEEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C1_RX_DMA_CHN 0x00100001
-#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
- STM32_DMA_STREAM_ID_MSK(1, 6))
-#define STM32_I2C1_TX_DMA_CHN 0x11000000
-
-#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
- STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C2_RX_DMA_CHN 0x00007700
-#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
-#define STM32_I2C2_TX_DMA_CHN 0x70000000
-
-#define STM32_HAS_I2C3 TRUE
-#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_I2C3_RX_DMA_CHN 0x00000300
-#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_I2C3_TX_DMA_CHN 0x00030000
-
-#define STM32_HAS_I2C4 FALSE
-
-/* QUADSPI attributes.*/
-#define STM32_HAS_QUADSPI1 FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO TRUE
-#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 6))
-#define STM32_SDC_SDIO_DMA_CHN 0x04004000
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI1_SUPPORTS_I2S FALSE
-#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_SPI1_RX_DMA_CHN 0x00000303
-#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_SPI1_TX_DMA_CHN 0x00303000
-
-#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI2_SUPPORTS_I2S TRUE
-#define STM32_SPI2_I2S_FULLDUPLEX TRUE
-#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI2_RX_DMA_CHN 0x00000000
-#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI3 TRUE
-#define STM32_SPI3_SUPPORTS_I2S TRUE
-#define STM32_SPI3_I2S_FULLDUPLEX TRUE
-#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
- STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_SPI3_RX_DMA_CHN 0x00000000
-#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
- STM32_DMA_STREAM_ID_MSK(1, 7))
-#define STM32_SPI3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_SPI4 TRUE
-#define STM32_SPI4_SUPPORTS_I2S FALSE
-#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
- STM32_DMA_STREAM_ID_MSK(2, 3))
-#define STM32_SPI4_RX_DMA_CHN 0x00005004
-#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 4))
-#define STM32_SPI4_TX_DMA_CHN 0x00050040
-
-#define STM32_HAS_SPI5 FALSE
-#define STM32_HAS_SPI6 FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
-
-#define STM32_HAS_TIM1 TRUE
-#define STM32_TIM1_IS_32BITS FALSE
-#define STM32_TIM1_CHANNELS 4
-
-#define STM32_HAS_TIM2 TRUE
-#define STM32_TIM2_IS_32BITS TRUE
-#define STM32_TIM2_CHANNELS 4
-
-#define STM32_HAS_TIM3 TRUE
-#define STM32_TIM3_IS_32BITS FALSE
-#define STM32_TIM3_CHANNELS 4
-
-#define STM32_HAS_TIM4 TRUE
-#define STM32_TIM4_IS_32BITS FALSE
-#define STM32_TIM4_CHANNELS 4
-
-#define STM32_HAS_TIM5 TRUE
-#define STM32_TIM5_IS_32BITS TRUE
-#define STM32_TIM5_CHANNELS 4
-
-#define STM32_HAS_TIM9 TRUE
-#define STM32_TIM9_IS_32BITS FALSE
-#define STM32_TIM9_CHANNELS 2
-
-#define STM32_HAS_TIM10 TRUE
-#define STM32_TIM10_IS_32BITS FALSE
-#define STM32_TIM10_CHANNELS 1
-
-#define STM32_HAS_TIM11 TRUE
-#define STM32_TIM11_IS_32BITS FALSE
-#define STM32_TIM11_CHANNELS 1
-
-#define STM32_HAS_TIM6 FALSE
-#define STM32_HAS_TIM7 FALSE
-#define STM32_HAS_TIM8 FALSE
-#define STM32_HAS_TIM12 FALSE
-#define STM32_HAS_TIM13 FALSE
-#define STM32_HAS_TIM14 FALSE
-#define STM32_HAS_TIM15 FALSE
-#define STM32_HAS_TIM16 FALSE
-#define STM32_HAS_TIM17 FALSE
-#define STM32_HAS_TIM18 FALSE
-#define STM32_HAS_TIM19 FALSE
-#define STM32_HAS_TIM20 FALSE
-#define STM32_HAS_TIM21 FALSE
-#define STM32_HAS_TIM22 FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1 TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
- STM32_DMA_STREAM_ID_MSK(2, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00400400
-#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
-#define STM32_USART1_TX_DMA_CHN 0x40000000
-
-#define STM32_HAS_USART2 TRUE
-#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_USART2_RX_DMA_CHN 0x00400000
-#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
-#define STM32_USART2_TX_DMA_CHN 0x04000000
-
-#define STM32_HAS_USART3 FALSE
-#define STM32_HAS_UART4 FALSE
-#define STM32_HAS_UART5 FALSE
-
-#define STM32_HAS_USART6 TRUE
-#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
- STM32_DMA_STREAM_ID_MSK(2, 2))
-#define STM32_USART6_RX_DMA_CHN 0x00000550
-#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_USART6_TX_DMA_CHN 0x55000000
-
-#define STM32_HAS_UART7 FALSE
-#define STM32_HAS_UART8 FALSE
-#define STM32_HAS_UART9 FALSE
-#define STM32_HAS_UART10 FALSE
-#define STM32_HAS_LPUART1 FALSE
-
-/* USB attributes.*/
-#define STM32_OTG_STEPPING 1
-#define STM32_HAS_OTG1 TRUE
-#define STM32_OTG1_ENDPOINTS 3
-#define STM32_HAS_OTG2 FALSE
-
-#define STM32_HAS_USB FALSE
-
-/* IWDG attributes.*/
-#define STM32_HAS_IWDG TRUE
-#define STM32_IWDG_IS_WINDOWED FALSE
-
-/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
-
-/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
-
-/* FSMC attributes.*/
-#define STM32_HAS_FSMC FALSE
-
-/* CRC attributes.*/
-#define STM32_HAS_CRC TRUE
-#define STM32_CRC_PROGRAMMABLE FALSE
-
-#endif /* defined(STM32F401xx) */
-/** @} */
-
-#endif /* STM32_REGISTRY_H */
+#endif /* AT32_REGISTRY_H */
/** @} */
diff --git a/os/hal/ports/AT32/AT32F4xx/hal_lld.h b/os/hal/ports/AT32/AT32F4xx/hal_lld.h
index b4ac55a2e..fac6478de 100644
--- a/os/hal/ports/AT32/AT32F4xx/hal_lld.h
+++ b/os/hal/ports/AT32/AT32F4xx/hal_lld.h
@@ -27,11 +27,7 @@
#include "at32_registry.h"
-#if defined(STM32F413xx)
-#include "hal_lld_type2.h"
-#else
#include "hal_lld_type1.h"
-#endif
/* Various helpers.*/
#include "nvic.h"
diff --git a/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h b/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h
index 615be83e0..93375adf4 100644
--- a/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h
+++ b/os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h
@@ -56,65 +56,11 @@
* @name Platform identification macros
* @{
*/
-#if defined(STM32F205xx) || defined(__DOXYGEN__)
-#define PLATFORM_NAME "STM32F205 High Performance"
-
-#elif defined(STM32F207xx)
-#define PLATFORM_NAME "STM32F207 High Performance"
-
-#elif defined(STM32F215xx)
-#define PLATFORM_NAME "STM32F215 High Performance"
-
-#elif defined(STM32F217xx)
-#define PLATFORM_NAME "STM32F217 High Performance"
-
-#elif defined(STM32F401xx)
-#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
-
-#elif defined(STM32F405xx)
-#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU"
-
-#elif defined(STM32F407xx)
-#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU"
-
-#elif defined(STM32F410xx)
-#define PLATFORM_NAME "STM32F410 High Performance with DSP and FPU"
-
-#elif defined(STM32F411xx)
-#define PLATFORM_NAME "STM32F411 High Performance with DSP and FPU"
-
-#elif defined(STM32F412xx)
-#define PLATFORM_NAME "STM32F412 High Performance with DSP and FPU"
-
-#elif defined(STM32F415xx)
-#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU"
-
-#elif defined(STM32F417xx)
-#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU"
-
-#elif defined(STM32F427xx)
-#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU"
-
-#elif defined(STM32F429xx)
-#define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU"
-
-#elif defined(STM32F437xx)
-#define PLATFORM_NAME "STM32F437 High Performance with DSP and FPU"
-
-#elif defined(STM32F439xx)
-#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU"
-
-#elif defined(STM32F446xx)
-#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU"
-
-#elif defined(STM32F469xx)
-#define PLATFORM_NAME "STM32F469 High Performance with DSP and FPU"
-
-#elif defined(STM32F479xx)
-#define PLATFORM_NAME "STM32F479 High Performance with DSP and FPU"
+#if defined(AT32F435xx) || defined(AT32F437xx)
+#define PLATFORM_NAME "AT32F435/437 High Performance with DSP, FPU and MPU"
#else
-#error "STM32F2xx/F4xx device not specified"
+#error "AT32FF4xx device not specified"
#endif
/** @} */
@@ -122,9 +68,7 @@
* @name Absolute Maximum Ratings
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(__DOXYGEN__)
+#if defined(AT32F435xx) || defined(AT32F437xx) || defined(__DOXYGEN__)
/**
* @brief Absolute maximum system clock.
*/
@@ -220,109 +164,6 @@
*/
#define STM32_SPII2S_MAX 45000000
#endif
-
-#if defined(STM32F40_41xxx)
-#define STM32_SYSCLK_MAX 168000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 50000000
-#define STM32_HSECLK_MIN 4000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2100000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 192000000
-#define STM32_PLLOUT_MAX 168000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 42000000
-#define STM32_PCLK2_MAX 84000000
-#define STM32_SPII2S_MAX 42000000
-#endif
-
-#if defined(STM32F401xx)
-#define STM32_SYSCLK_MAX 84000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 50000000
-#define STM32_HSECLK_MIN 4000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2100000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 192000000
-#define STM32_PLLOUT_MAX 84000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 42000000
-#define STM32_PCLK2_MAX 84000000
-#define STM32_SPII2S_MAX 42000000
-#endif
-
-#if defined(STM32F410xx) || defined(STM32F411xx) || \
- defined(STM32F412xx)
-#define STM32_SYSCLK_MAX 100000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 50000000
-#define STM32_HSECLK_MIN 4000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2100000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 100000000
-#define STM32_PLLOUT_MAX 100000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 50000000
-#define STM32_PCLK2_MAX 100000000
-#define STM32_SPII2S_MAX 50000000
-#endif
-
-#if defined(STM32F446xx)
-#define STM32_SYSCLK_MAX 180000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 50000000
-#define STM32_HSECLK_MIN 4000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2100000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 100000000
-#define STM32_PLLOUT_MAX 180000000
-#define STM32_PLLOUT_MIN 12500000
-#define STM32_PLLI2SOUT_MAX 216000000
-#define STM32_PLLSAIOUT_MAX 216000000
-#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
-#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
-#define STM32_SPII2S_MAX 45000000
-#endif
-
-#if defined(STM32F2XX)
-#define STM32_SYSCLK_MAX 120000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 26000000
-#define STM32_HSECLK_MIN 1000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2000000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 192000000
-#define STM32_PLLOUT_MAX 120000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 30000000
-#define STM32_PCLK2_MAX 60000000
-#define STM32_SPII2S_MAX 30000000
-#endif
/** @} */
/**
diff --git a/os/hal/ports/AT32/AT32F4xx/hal_lld_type2.h b/os/hal/ports/AT32/AT32F4xx/hal_lld_type2.h
deleted file mode 100644
index b90a427f5..000000000
--- a/os/hal/ports/AT32/AT32F4xx/hal_lld_type2.h
+++ /dev/null
@@ -1,1212 +0,0 @@
-/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F4xx/hal_lld_type2.h
- * @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header.
- * @pre This module requires the following macros to be defined in the
- * @p board.h file:
- * - STM32_LSECLK.
- * - STM32_LSE_BYPASS (optionally).
- * - STM32_HSECLK.
- * - STM32_HSE_BYPASS (optionally).
- * - STM32_VDD (as hundredths of Volt).
- * .
- * One of the following macros must also be defined:
- * - STM32F413xx for High-performance STM32F4 devices of Access line.
- * .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef HAL_LLD_TYPE2_H
-#define HAL_LLD_TYPE2_H
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS TRUE
-
-/**
- * @name Platform identification macros
- * @{
- */
-#if defined(STM32F413xx)
-#define PLATFORM_NAME "STM32F413 High Performance with DSP and FPU"
-
-#else
-#error "STM32F2xx/F4xx device not specified"
-#endif
-/** @} */
-
-/**
- * @name Absolute Maximum Ratings
- * @{
- */
-
-#if defined(STM32F413xx) || defined(__DOXYGEN__)
-/**
- * @brief Absolute maximum system clock.
- */
-#define STM32_SYSCLK_MAX 100000000
-
-/**
- * @brief Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX 26000000
-
-/**
- * @brief Maximum HSE clock frequency using an external source.
- */
-#define STM32_HSECLK_BYP_MAX 50000000
-
-/**
- * @brief Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN 4000000
-
-/**
- * @brief Minimum HSE clock frequency using an external source.
- */
-#define STM32_HSECLK_BYP_MIN 1000000
-
-/**
- * @brief Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX 32768
-
-/**
- * @brief Maximum LSE clock frequency using an external source.
- */
-#define STM32_LSECLK_BYP_MAX 1000000
-
-/**
- * @brief Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN 32768
-
-/**
- * @brief Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX 2100000
-
-/**
- * @brief Minimum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN 950000
-
-/**
- * @brief Maximum PLLs VCO clock frequency.
- */
-#define STM32_PLLVCO_MAX 432000000
-
-/**
- * @brief Minimum PLLs VCO clock frequency.
- */
-#define STM32_PLLVCO_MIN 100000000
-
-/**
- * @brief Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX 100000000
-
-/**
- * @brief Minimum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN 24000000
-
-/**
- * @brief Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX 50000000
-
-/**
- * @brief Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX 100000000
-
-/**
- * @brief Maximum SPI/I2S clock frequency.
- */
-#define STM32_SPII2S_MAX 50000000
-#endif
-/** @} */
-
-/**
- * @name Internal clock sources
- * @{
- */
-#define STM32_HSICLK 16000000 /**< High speed internal clock. */
-#define STM32_LSICLK 32000 /**< Low speed internal clock. */
-/** @} */
-
-/**
- * @name PWR_CR register bits definitions
- * @{
- */
-#define STM32_VOS_SCALE3 0x00004000
-#define STM32_VOS_SCALE2 0x00008000
-#define STM32_VOS_SCALE1 0x0000C000
-#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
-#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
-#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
-#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
-#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
-#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
-#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
-#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
-/** @} */
-
-/**
- * @name RCC_PLLCFGR register bits definitions
- * @{
- */
-#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */
-#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */
-#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */
-#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */
-#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */
-
-#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */
-#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */
-/** @} */
-
-/**
- * @name RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_MASK (3 << 0) /**< SW mask. */
-#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
-#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
-#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
-
-#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */
-#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
-#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
-#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
-#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
-#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
-#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
-#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
-#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
-#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
-
-#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */
-#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */
-#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */
-#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */
-#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */
-#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */
-
-#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */
-#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */
-#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */
-#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */
-#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */
-#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */
-
-#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */
-
-#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */
-#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */
-#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */
-#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
-#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
-
-#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
-#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
-#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
-#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */
-#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */
-#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */
-
-#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */
-#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */
-#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */
-#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */
-#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
-#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
-
-#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
-#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
-#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
-#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
-#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
-
-/**
- * @name RCC_PLLI2SCFGR register bits definitions
- * @{
- */
-#define STM32_PLLI2SM_MASK (31 << 0) /**< PLLI2SM mask. */
-#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
-#define STM32_PLLI2SSRC_MASK (1 << 22) /**< PLLI2SSRC mask. */
-#define STM32_PLLI2SSRC_PLLSRC (0 << 22) /**< PLLI2SSRC is selected PLL
- source. */
-#define STM32_PLLI2SSRC_CKIN (1 << 22) /**< PLLI2SSRC is I2S_CKIN. */
-#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */
-#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */
-/** @} */
-
-/**
- * @name RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
-#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
-#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
-#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
-#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
-/** @} */
-
-/**
- * @name RCC_DCKCFGR register bits definitions
- * @{
- */
-#define STM32_PLLI2SDIVR_MASK (31 << 0) /**< PLLI2SDIVR mask. */
-#define STM32_PLLDIVR_MASK (31 << 8) /**< PLLDIVR mask. */
-
-#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
-#define STM32_SAI1SEL_PLLSAI (0 << 20) /**< SAI1 source is PLLSAI. */
-#define STM32_SAI1SEL_PLLI2S (1 << 20) /**< SAI1 source is PLLI2S. */
-#define STM32_SAI1SEL_PLLR (2 << 20) /**< SAI1 source is PLLR. */
-#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
-
-#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
-#define STM32_SAI2SEL_PLLSAI (0 << 22) /**< SAI2 source is PLLSAI. */
-#define STM32_SAI2SEL_PLLI2S (1 << 22) /**< SAI2 source is PLLI2S. */
-#define STM32_SAI2SEL_PLLR (2 << 22) /**< SAI2 source is PLLR. */
-#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
-
-#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
-#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
-#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */
-
-#define STM32_I2S1SEL_MASK (3 << 25) /**< I2S1SEL mask. */
-#define STM32_I2S1SEL_PLLR (0 << 25) /**< I2S1 source is PLLR. */
-#define STM32_I2S1SEL_AFIN (1 << 25) /**< I2S1 source is AF Input. */
-#define STM32_I2S1SEL_MCO1 (2 << 25) /**< I2S1 source is MCO1. */
-#define STM32_I2S1SEL_OFF 0xFFFFFFFFU /**< I2S1 clock is not required.*/
-
-#define STM32_I2S2SEL_MASK (3 << 27) /**< I2S2SEL mask. */
-#define STM32_I2S2SEL_PLLR (0 << 27) /**< I2S2 source is PLLR. */
-#define STM32_I2S2SEL_AFIN (1 << 27) /**< I2S2 source is AF Input. */
-#define STM32_I2S2SEL_MCO1 (2 << 27) /**< I2S2 source is MCO1. */
-#define STM32_I2S2SEL_OFF 0xFFFFFFFFU /**< I2S2 clock is not required.*/
-/** @} */
-
-/**
- * @name RCC_DCKCFGR2 register bits definitions
- * @{
- */
-#define STM32_I2CFMP1SEL_MASK (3 << 22) /**< I2CFMP1SEL mask. */
-#define STM32_I2CFMP1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */
-#define STM32_I2CFMP1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
-#define STM32_I2CFMP1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
-
-#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
-#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
-#define STM32_CK48MSEL_PLLI2S (1 << 27) /**< PLL48CLK source is PLLI2S. */
-#define STM32_CK48MSEL_PLLALT (1 << 27) /**< Alias. */
-
-#define STM32_SDIOSEL_MASK (1 << 28) /**< SDIOSEL mask. */
-#define STM32_SDIOSEL_PLL48CLK (0 << 28) /**< SDIO source is PLL48CLK. */
-#define STM32_SDIOSEL_SYSCLK (1 << 28) /**< SDIO source is SYSCLK. */
-
-#define STM32_LPTIM1SEL_MASK (3 << 30) /**< LPTIM1 mask. */
-#define STM32_LPTIM1SEL_APB (0 << 30) /**< LPTIM1 source is APB. */
-#define STM32_LPTIM1SEL_HSI (1 << 30) /**< LPTIM1 source is HSI. */
-#define STM32_LPTIM1SEL_LSI (2 << 30) /**< LPTIM1 source is LSI. */
-#define STM32_LPTIM1SEL_LSE (3 << 30) /**< LPTIM1 source is LSE. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief Disables the PWR/RCC initialization in the HAL.
- */
-#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT FALSE
-#endif
-
-/**
- * @brief Enables or disables the programmable voltage detector.
- */
-#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE FALSE
-#endif
-
-/**
- * @brief Sets voltage level for programmable voltage detector.
- */
-#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS STM32_PLS_LEV0
-#endif
-
-/**
- * @brief Enables the backup RAM regulator.
- */
-#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__)
-#define STM32_BKPRAM_ENABLE FALSE
-#endif
-
-/**
- * @brief Enables or disables the HSI clock source.
- */
-#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED TRUE
-#endif
-
-/**
- * @brief Enables or disables the LSI clock source.
- */
-#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED FALSE
-#endif
-
-/**
- * @brief Enables or disables the HSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED TRUE
-#endif
-
-/**
- * @brief Enables or disables the LSE clock source.
- */
-#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED FALSE
-#endif
-
-/**
- * @brief USB/SDIO clock setting.
- */
-#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_CLOCK48_REQUIRED TRUE
-#endif
-
-/**
- * @brief Main clock source selection.
- * @note If the selected clock source is not the PLL then the PLL is not
- * initialized and started.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW STM32_SW_PLL
-#endif
-
-/**
- * @brief Clock source for the PLLs.
- * @note This setting has only effect if the PLL is selected as the
- * system clock source.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief PLLM divider value.
- * @note The allowed values are 2..63.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLM_VALUE 8
-#endif
-
-/**
- * @brief PLLN multiplier value.
- * @note The allowed values are 192..432.
- * @note The default value is calculated for a 96MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLN_VALUE 384
-#endif
-
-/**
- * @brief PLLP divider value.
- * @note The allowed values are 2, 4, 6, 8.
- * @note The default value is calculated for a 96MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLP_VALUE 4
-#endif
-
-/**
- * @brief PLLQ multiplier value.
- * @note The allowed values are 2..15.
- * @note The default value is calculated for a 96MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLQ_VALUE 8
-#endif
-
-/**
- * @brief AHB prescaler value.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1 STM32_PPRE1_DIV4
-#endif
-
-/**
- * @brief APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2 STM32_PPRE2_DIV2
-#endif
-
-/**
- * @brief I2S clock source (pre-PLL).
- */
-#if !defined(STM32_PLLI2SSRC) || defined(__DOXYGEN__)
-#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC
-#endif
-
-/**
- * @brief I2S external clock value, zero if not present.
- */
-#if !defined(STM32_I2SCKIN_VALUE) || defined(__DOXYGEN__)
-#define STM32_I2SCKIN_VALUE 0
-#endif
-
-/**
- * @brief PLLI2SM divider value.
- * @note The allowed values are 2..63.
- * @note The default value is calculated for a 96MHz I2S clock
- * output from an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SM_VALUE 8
-#endif
-
-/**
- * @brief PLLI2SN multiplier value.
- * @note The allowed values are 192..432, except for
- * STM32F446 where values are 50...432.
- * @note The default value is calculated for a 96MHz I2S clock
- * output from an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SN_VALUE 192
-#endif
-
-/**
- * @brief PLLI2SR divider value.
- * @note The allowed values are 2..7.
- * @note The default value is calculated for a 96MHz I2S clock
- * output from an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SR_VALUE 4
-#endif
-
-/**
- * @brief PLLI2SQ divider value.
- * @note The allowed values are 2..15.
- */
-#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SQ_VALUE 4
-#endif
-
-/**
- * @brief PLLI2SDIVR divider value (SAI clock divider).
- * @note The allowed values are 1..32.
- */
-#if !defined(STM32_PLLI2SDIVR_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SDIVR_VALUE 1
-#endif
-
-/**
- * @brief PLLDIVR divider value (SAI clock divider).
- * @note The allowed values are 1..32.
- */
-#if !defined(STM32_PLLDIVR_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLDIVR_VALUE 1
-#endif
-
-/**
- * @brief SAI1SEL value (SAI1 clock source).
- */
-#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)
-#define STM32_SAI1SEL STM32_SAI1SEL_OFF
-#endif
-
-/**
- * @brief SAI2SEL value (SAI2 clock source).
- */
-#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)
-#define STM32_SAI2SEL STM32_SAI2SEL_OFF
-#endif
-
-/**
- * @brief TIM prescaler clock source.
- */
-#if !defined(STM32_TIMPRE) || defined(__DOXYGEN__)
-#define STM32_TIMPRE STM32_TIMPRE_PCLK
-#endif
-
-/**
- * @brief PLL48CLK clock source.
- */
-#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__)
-#define STM32_CK48MSEL STM32_CK48MSEL_PLL
-#endif
-
-/**
- * @brief RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL STM32_RTCSEL_LSE
-#endif
-
-/**
- * @brief RTC HSE prescaler value.
- */
-#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__)
-#define STM32_RTCPRE_VALUE 8
-#endif
-
-/**
- * @brief MCO1 clock source value.
- * @note The default value outputs HSI clock on MCO1 pin.
- */
-#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__)
-#define STM32_MCO1SEL STM32_MCO1SEL_HSI
-#endif
-
-/**
- * @brief MCO1 prescaler value.
- * @note The default value outputs HSI clock on MCO1 pin.
- */
-#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__)
-#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
-#endif
-
-/**
- * @brief MCO2 clock source value.
- * @note The default value outputs SYSCLK / 5 on MCO2 pin.
- */
-#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
-#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
-#endif
-
-/**
- * @brief MCO2 prescaler value.
- * @note The default value outputs SYSCLK / 5 on MCO2 pin.
- */
-#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__)
-#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F4xx_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"
-#endif
-
-#if defined(STM32F413xx) && !defined(STM32F413_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F413_MCUCONF not defined"
-#endif
-
-/**
- * @name Maximum frequency thresholds, wait states and
- * parallelism for flash access.
- * @{
- */
-#if defined(STM32F413xx)
-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
-#define STM32_0WS_THRESHOLD 25000000
-#define STM32_1WS_THRESHOLD 50000000
-#define STM32_2WS_THRESHOLD 75000000
-#define STM32_3WS_THRESHOLD 100000000
-#define STM32_4WS_THRESHOLD 0
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#define STM32_FLASH_PSIZE 2
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD 20000000
-#define STM32_1WS_THRESHOLD 40000000
-#define STM32_2WS_THRESHOLD 60000000
-#define STM32_3WS_THRESHOLD 80000000
-#define STM32_4WS_THRESHOLD 100000000
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#define STM32_FLASH_PSIZE 1
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD 18000000
-#define STM32_1WS_THRESHOLD 36000000
-#define STM32_2WS_THRESHOLD 54000000
-#define STM32_3WS_THRESHOLD 72000000
-#define STM32_4WS_THRESHOLD 90000000
-#define STM32_5WS_THRESHOLD 100000000
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#define STM32_FLASH_PSIZE 1
-#elif (STM32_VDD >= 170) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD 16000000
-#define STM32_1WS_THRESHOLD 32000000
-#define STM32_2WS_THRESHOLD 48000000
-#define STM32_3WS_THRESHOLD 64000000
-#define STM32_4WS_THRESHOLD 80000000
-#define STM32_5WS_THRESHOLD 96000000
-#define STM32_6WS_THRESHOLD 100000000
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#define STM32_FLASH_PSIZE 0
-#else
-#error "invalid VDD voltage specified"
-#endif
-#define FLASH_SR_OPERR FLASH_SR_SOP
-#endif /* defined(STM32F413xx) */
-/** @} */
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \
- ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCO1SEL"
-#endif
-
-#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_MCO2SEL"
-#endif
-
-#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_I2SSRC"
-#endif
-
-#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
- (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SAI1SEL"
-#endif
-
-#if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \
- (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SAI2SEL"
-#endif
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#else /* STM32_HSECLK != 0 */
-#if defined(STM32_HSE_BYPASS)
-#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)"
-#endif
-#else /* !defined(STM32_HSE_BYPASS) */
-#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-#endif /* !defined(STM32_HSE_BYPASS) */
-#endif /* STM32_HSECLK != 0 */
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \
- ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCO1SEL"
-#endif
-
-#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \
- ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCO2SEL"
-#endif
-
-#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) && \
- (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_PLLI2SSRC"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if HAL_USE_RTC && (STM32_RTCSEL == STM32_RTCSEL_LSI)
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if (STM32_LSECLK == 0)
-#error "LSE frequency not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/**
- * @brief Clock frequency feeding PLLs.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLSRCCLK STM32_HSECLK
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLSRCCLK STM32_HSICLK
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/**
- * @brief STM32_PLLM field.
- */
-#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLM (STM32_PLLM_VALUE << 0)
-#else
-#error "invalid STM32_PLLM_VALUE value specified"
-#endif
-
-/**
- * @brief PLL input clock frequency.
- */
-#define STM32_PLLCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE)
-
-/*
- * PLLs input frequency range check.
- */
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/*
- * PLL enable check.
- */
-#if (STM32_CLOCK48_REQUIRED && \
- STM32_HAS_RCC_CK48MSEL && \
- (STM32_CK48MSEL == STM32_CK48MSEL_PLL)) || \
- (STM32_SW == STM32_SW_PLL) || \
- (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \
- (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \
- defined(__DOXYGEN__)
-/**
- * @brief PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL TRUE
-#else
-#define STM32_ACTIVATE_PLL FALSE
-#endif
-
-/**
- * @brief STM32_PLLN field.
- */
-#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLN (STM32_PLLN_VALUE << 6)
-#else
-#error "invalid STM32_PLLN_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLP field.
- */
-#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLP STM32_PLLP_DIV2
-#elif STM32_PLLP_VALUE == 4
-#define STM32_PLLP STM32_PLLP_DIV4
-#elif STM32_PLLP_VALUE == 6
-#define STM32_PLLP STM32_PLLP_DIV6
-#elif STM32_PLLP_VALUE == 8
-#define STM32_PLLP STM32_PLLP_DIV8
-#else
-#error "invalid STM32_PLLP_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLQ field.
- */
-#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLQ (STM32_PLLQ_VALUE << 24)
-#else
-#error "invalid STM32_PLLQ_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLDIVR_VALUE field.
- */
-#if ((STM32_PLLDIVR_VALUE >= 1) && (STM32_PLLDIVR_VALUE <= 32)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLDIVR ((STM32_PLLDIVR_VALUE - 1) << 8)
-#else
-#error "invalid STM32_PLLDIVR_VALUE value specified"
-#endif
-
-/**
- * @brief PLL VCO frequency.
- */
-#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
-
-/*
- * PLL VCO frequency range check.
- */
-#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
-#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
-#endif
-
-/**
- * @brief PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
-
-/*
- * PLL output frequency range check.
- */
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief System clock source.
- */
-#if STM32_NO_INIT || defined(__DOXYGEN__)
-#define STM32_SYSCLK STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK STM32_HSECLK
-#elif (STM32_SW == STM32_SW_PLL)
-#define STM32_SYSCLK STM32_PLLCLKOUT
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/* Calculating VOS settings, it is different for each sub-platform.*/
-#if defined(STM32F413xx)
-#if STM32_SYSCLK <= 64000000
-#define STM32_VOS STM32_VOS_SCALE3
-#elif STM32_SYSCLK <= 84000000
-#define STM32_VOS STM32_VOS_SCALE2
-#else
-#define STM32_VOS STM32_VOS_SCALE1
-#endif
-#define STM32_OVERDRIVE_REQUIRED FALSE
-#endif
-
-/**
- * @brief AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/*
- * AHB frequency check.
- */
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1 (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1 (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1 (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1 (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/*
- * APB1 frequency check.
- */
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2 (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2 (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2 (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2 (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/*
- * APB2 frequency check.
- */
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/*
- * PLLI2S enable check.
- */
-#if (STM32_HAS_RCC_PLLI2S && \
- (STM32_CLOCK48_REQUIRED && \
- (STM32_HAS_RCC_CK48MSEL && \
- STM32_RCC_CK48MSEL_USES_I2S && \
- (STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S)) || \
- (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
- (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S))) || \
- defined(__DOXYGEN__)
-
-/**
- * @brief PLLI2S activation flag.
- */
-#define STM32_ACTIVATE_PLLI2S TRUE
-#else
-#define STM32_ACTIVATE_PLLI2S FALSE
-#endif
-
-/**
- * @brief STM32_PLLI2SM field.
- */
-#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLI2SM (STM32_PLLI2SM_VALUE << 0)
-#else
-#error "invalid STM32_PLLI2SM_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLI2SN field.
- */
-#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
-#else
-#error "invalid STM32_PLLI2SN_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLI2SQ field.
- */
-#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24)
-#else
-#error "invalid STM32_PLLI2SQ_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLI2SR field.
- */
-#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28)
-#else
-#error "invalid STM32_PLLI2SR_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLI2SDIVR field.
- */
-#if ((STM32_PLLI2SDIVR_VALUE >= 1) && (STM32_PLLI2SDIVR_VALUE <= 32)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLI2SDIVR ((STM32_PLLI2SR_VALUE - 1) << 0)
-#else
-#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"
-#endif
-
-/**
- * @brief PLLI2S input clock frequency.
- */
-#if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)
-#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)
-#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_CKIN
-#define STM32_PLLI2SCLKIN (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)
-#else
-#error "invalid STM32_PLLI2SSRC value specified"
-#endif
-#else
-#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLM_VALUE)
-#endif
-
-/**
- * @brief PLLI2S VCO frequency.
- */
-#define STM32_PLLI2SVCO (STM32_PLLI2SCLKIN * STM32_PLLI2SN_VALUE)
-
-/*
- * PLLI2S VCO frequency range check.
- */
-#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
- (STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
-#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
-#endif
-
-/**
- * @brief PLLI2S Q output clock frequency.
- */
-#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)
-
-/**
- * @brief PLLI2S R output clock frequency.
- */
-#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
-
-/**
- * @brief PLLI2SP enable bit.
- * @note Always 0, there is no PLLI2SP.
- */
-#define STM32_PLLI2SP 0
-
-/**
- * @brief PLLSAI activation flag.
- * @note Always FALSE, there is no PLLSAI.
- */
-#define STM32_ACTIVATE_PLLSAI FALSE
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void hal_lld_init(void);
- void stm32_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_LLD_TYPE2_H */
-
-/** @} */