diff --git a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/chconf.h b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/chconf.h
index 53b3224c8..d4d2979fe 100644
--- a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/chconf.h
+++ b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/cfg/chconf.h
@@ -589,7 +589,7 @@
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif
/**
diff --git a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
index 137ea2afe..b9ca3415d 100644
--- a/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
+++ b/demos/STM32/RT-STM32L552ZE-NUCLEO144-TEST/debug/RT-STM32L552ZE-NUCLEO144-TEST (ST-Link GDB Server, Flash and Run).launch
@@ -33,7 +33,7 @@
-
+
diff --git a/os/common/ports/ARMv8-M-ML/chcore.c b/os/common/ports/ARMv8-M-ML/chcore.c
index 259d36016..f1d4255c3 100644
--- a/os/common/ports/ARMv8-M-ML/chcore.c
+++ b/os/common/ports/ARMv8-M-ML/chcore.c
@@ -60,6 +60,10 @@
void *port_swap_stacks(void *sp) {
thread_t *ntp;
+#if CH_DBG_ENABLE_STACK_CHECK == TRUE
+ currp->ctx.splim = __get_PSPLIM();
+#endif
+
chSysLock();
/* TODO statistics, tracing etc */
@@ -68,6 +72,10 @@ void *port_swap_stacks(void *sp) {
chSysUnlock();
+#if CH_DBG_ENABLE_STACK_CHECK == TRUE
+ __set_PSPLIM(ntp->ctx.splim);
+#endif
+
return ntp->ctx.sp;
}
diff --git a/os/common/ports/ARMv8-M-ML/chcore.h b/os/common/ports/ARMv8-M-ML/chcore.h
index 95bc1c07a..def5d20f9 100644
--- a/os/common/ports/ARMv8-M-ML/chcore.h
+++ b/os/common/ports/ARMv8-M-ML/chcore.h
@@ -284,6 +284,9 @@ struct port_intctx {
*/
struct port_context {
struct port_intctx *sp;
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__)
+ uint32_t splim;
+#endif
};
#endif /* !defined(_FROM_ASM_) */
@@ -359,9 +362,11 @@ struct port_context {
* @details This code usually setup the context switching frame represented
* by an @p port_intctx structure.
*/
+#if (CH_DBG_ENABLE_STACK_CHECK == TRUE) || defined(__DOXYGEN__)
#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) do { \
- (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
- sizeof (struct port_intctx)); \
+ (tp)->ctx.splim = (uint32_t)(wbase); \
+ (tp)->ctx.sp = (struct port_intctx *) \
+ ((uint8_t *)(wtop) - sizeof (struct port_intctx));\
(tp)->ctx.sp->basepri = CORTEX_BASEPRI_KERNEL; \
(tp)->ctx.sp->r5 = (uint32_t)(arg); \
(tp)->ctx.sp->r4 = (uint32_t)(pf); \
@@ -369,6 +374,18 @@ struct port_context {
(tp)->ctx.sp->xpsr = (uint32_t)0x01000000; \
(tp)->ctx.sp->pc = (uint32_t)__port_thread_start; \
} while (false)
+#else
+#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) do { \
+ (tp)->ctx.sp = (struct port_intctx *) \
+ ((uint8_t *)(wtop) - sizeof (struct port_intctx));\
+ (tp)->ctx.sp->basepri = CORTEX_BASEPRI_KERNEL; \
+ (tp)->ctx.sp->r5 = (uint32_t)(arg); \
+ (tp)->ctx.sp->r4 = (uint32_t)(pf); \
+ (tp)->ctx.sp->lr_exc = (uint32_t)0xFFFFFFFD; \
+ (tp)->ctx.sp->xpsr = (uint32_t)0x01000000; \
+ (tp)->ctx.sp->pc = (uint32_t)__port_thread_start; \
+} while (false)
+#endif
/**
* @brief Computes the thread working area global size.
@@ -452,6 +469,7 @@ struct port_context {
} while (false)
#else
#define port_switch(ntp, otp) do { \
+ _dbg_leave_lock(); \
register thread_t *_ntp asm ("r0") = (ntp); \
register thread_t *_otp asm ("r1") = (otp); \
struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \
@@ -459,6 +477,7 @@ struct port_context {
chSysHalt("stack overflow"); \
} \
asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp) : "memory"); \
+ _dbg_enter_lock(); \
} while (false)
#endif
diff --git a/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S b/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
index 572c4fd9e..1c65eac75 100644
--- a/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
+++ b/os/common/ports/ARMv8-M-ML/compilers/GCC/chcoreasm.S
@@ -79,6 +79,12 @@ SVC_Handler:
mrs r2, PSP
stmdb r2!, {r3-r11,lr}
str r2, [r1, #CONTEXT_OFFSET]
+#if CH_DBG_ENABLE_STACK_CHECK
+ mrs r2, PSPLIM
+ str r2, [r1, #CONTEXT_OFFSET + 4]
+ ldr r2, [r0, #CONTEXT_OFFSET + 4]
+ msr PSPLIM, r2
+#endif
ldr r2, [r0, #CONTEXT_OFFSET]
ldmia r2!, {r3-r11, lr}
msr PSP, r2
diff --git a/os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-mainline.S b/os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-ml.S
similarity index 93%
rename from os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-mainline.S
rename to os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-ml.S
index 4ce96d668..c4ce0c7f1 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-mainline.S
+++ b/os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-ml.S
@@ -15,10 +15,10 @@
*/
/**
- * @file crt0_v7m.S
- * @brief Generic ARMv7-M (Cortex-M3/M4/M7) startup file for ChibiOS.
+ * @file crt0_v8m-ml.S
+ * @brief Generic ARMv8-M mainline (Cortex-M33/M55) startup file for ChibiOS.
*
- * @addtogroup ARMCMx_GCC_STARTUP_V7M
+ * @addtogroup ARMCMx_GCC_STARTUP_V8M_ML
* @{
*/
@@ -169,7 +169,7 @@
#if !defined(__DOXYGEN__)
.syntax unified
- .cpu cortex-m3
+ .cpu cortex-m33
#if CRT0_INIT_FPU == TRUE
.fpu fpv4-sp-d16
#else
@@ -194,10 +194,14 @@ _crt0_entry:
ldr r0, =__main_stack_end__
msr MSP, r0
#endif
+ ldr r0, =__main_stack_base__
+ msr MSPLIM, r0
/* PSP stack pointers initialization.*/
ldr r0, =__process_stack_end__
msr PSP, r0
+ ldr r0, =__process_stack_base__
+ msr PSPLIM, r0
#if CRT0_VTOR_INIT == TRUE
ldr r0, =_vectors
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l5xx.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l5xx.mk
index 19debe764..06af47383 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l5xx.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l5xx.mk
@@ -2,7 +2,7 @@
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S \
- $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-mainline.S
+ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v8m-ml.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/devices/STM32L5xx \