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More work on STM32 SPIv3 and DMAv3 drivers, to be tested. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11215 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2018-01-03 10:47:31 +00:00
parent 84e0ad64f0
commit 06cdcc071c
4 changed files with 260 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c
View File

@ -61,22 +61,22 @@
* instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{DMA1_Stream0, &DMA1->LIFCR, 0, 0, STM32_DMA1_CH0_NUMBER},
{DMA1_Stream1, &DMA1->LIFCR, 6, 1, STM32_DMA1_CH1_NUMBER},
{DMA1_Stream2, &DMA1->LIFCR, 16, 2, STM32_DMA1_CH2_NUMBER},
{DMA1_Stream3, &DMA1->LIFCR, 22, 3, STM32_DMA1_CH3_NUMBER},
{DMA1_Stream4, &DMA1->HIFCR, 0, 4, STM32_DMA1_CH4_NUMBER},
{DMA1_Stream5, &DMA1->HIFCR, 6, 5, STM32_DMA1_CH5_NUMBER},
{DMA1_Stream6, &DMA1->HIFCR, 16, 6, STM32_DMA1_CH6_NUMBER},
{DMA1_Stream7, &DMA1->HIFCR, 22, 7, STM32_DMA1_CH7_NUMBER},
{DMA2_Stream0, &DMA2->LIFCR, 0, 8, STM32_DMA2_CH0_NUMBER},
{DMA2_Stream1, &DMA2->LIFCR, 6, 9, STM32_DMA2_CH1_NUMBER},
{DMA2_Stream2, &DMA2->LIFCR, 16, 10, STM32_DMA2_CH2_NUMBER},
{DMA2_Stream3, &DMA2->LIFCR, 22, 11, STM32_DMA2_CH3_NUMBER},
{DMA2_Stream4, &DMA2->HIFCR, 0, 12, STM32_DMA2_CH4_NUMBER},
{DMA2_Stream5, &DMA2->HIFCR, 6, 13, STM32_DMA2_CH5_NUMBER},
{DMA2_Stream6, &DMA2->HIFCR, 16, 14, STM32_DMA2_CH6_NUMBER},
{DMA2_Stream7, &DMA2->HIFCR, 22, 15, STM32_DMA2_CH7_NUMBER},
{DMA1_Stream0, &DMA1->LIFCR, 0, DMAMUX1_Channel0, 0, STM32_DMA1_CH0_NUMBER},
{DMA1_Stream1, &DMA1->LIFCR, 6, DMAMUX1_Channel1, 1, STM32_DMA1_CH1_NUMBER},
{DMA1_Stream2, &DMA1->LIFCR, 16, DMAMUX1_Channel2, 2, STM32_DMA1_CH2_NUMBER},
{DMA1_Stream3, &DMA1->LIFCR, 22, DMAMUX1_Channel3, 3, STM32_DMA1_CH3_NUMBER},
{DMA1_Stream4, &DMA1->HIFCR, 0, DMAMUX1_Channel4, 4, STM32_DMA1_CH4_NUMBER},
{DMA1_Stream5, &DMA1->HIFCR, 6, DMAMUX1_Channel5, 5, STM32_DMA1_CH5_NUMBER},
{DMA1_Stream6, &DMA1->HIFCR, 16, DMAMUX1_Channel6, 6, STM32_DMA1_CH6_NUMBER},
{DMA1_Stream7, &DMA1->HIFCR, 22, DMAMUX1_Channel7, 7, STM32_DMA1_CH7_NUMBER},
{DMA2_Stream0, &DMA2->LIFCR, 0, DMAMUX1_Channel8, 8, STM32_DMA2_CH0_NUMBER},
{DMA2_Stream1, &DMA2->LIFCR, 6, DMAMUX1_Channel9, 9, STM32_DMA2_CH1_NUMBER},
{DMA2_Stream2, &DMA2->LIFCR, 16, DMAMUX1_Channel10, 10, STM32_DMA2_CH2_NUMBER},
{DMA2_Stream3, &DMA2->LIFCR, 22, DMAMUX1_Channel11, 11, STM32_DMA2_CH3_NUMBER},
{DMA2_Stream4, &DMA2->HIFCR, 0, DMAMUX1_Channel12, 12, STM32_DMA2_CH4_NUMBER},
{DMA2_Stream5, &DMA2->HIFCR, 6, DMAMUX1_Channel13, 13, STM32_DMA2_CH5_NUMBER},
{DMA2_Stream6, &DMA2->HIFCR, 16, DMAMUX1_Channel14, 14, STM32_DMA2_CH6_NUMBER},
{DMA2_Stream7, &DMA2->HIFCR, 22, DMAMUX1_Channel15, 15, STM32_DMA2_CH7_NUMBER},
};
/*===========================================================================*/
@ -481,6 +481,23 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
return false;
}
/**
* @brief Associates a peripheral request to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] per peripheral identifier
*
* @special
*/
void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per) {
osalDbgCheck(per < 256U);
dmastp->mux->CCR = per;
}
/**
* @brief Releases a DMA stream.
* @details The stream is freed and, if required, the DMA clock disabled.

26
os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h
View File

@ -25,6 +25,8 @@
#ifndef STM32_DMA_H
#define STM32_DMA_H
#include "stm32_dmamux.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@ -50,6 +52,16 @@
*/
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
/**
* @brief Checks if a DMA channel is within the valid range.
* @param[in] ch DMA channel
*
* @retval The check result.
* @retval FALSE invalid DMA channel.
* @retval TRUE correct DMA channel.
*/
#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && ((ch) <= 15U))
/**
* @name DMA streams identifiers
* @{
@ -82,7 +94,7 @@
/** @} */
/**
* @name CR register constants common to all DMA types
* @name CR register constants
* @{
*/
#define STM32_DMA_CR_RESET_VALUE 0x00000000U
@ -307,12 +319,13 @@
* @brief STM32 DMA stream descriptor structure.
*/
typedef struct {
DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
uint8_t ishift; /**< @brief Bits offset in xIFCR
DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
uint8_t ishift; /**< @brief Bits offset in xIFCR
register. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
DMAMUX_Channel_TypeDef *mux; /**< @brief Associated DMA stream. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
} stm32_dma_stream_t;
/**
@ -624,6 +637,7 @@ extern "C" {
uint32_t priority,
stm32_dmaisr_t func,
void *param);
void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
#ifdef __cplusplus
}

95
os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
View File

@ -76,12 +76,38 @@ static uint32_t dummyrx;
/*===========================================================================*/
/**
* @brief Shared DMA service routine.
* @brief Shared end-of-rx service routine.
*
* @param[in] spip pointer to the @p SPIDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void spi_serve_dma_interrupt(SPIDriver *spip, uint32_t flags) {
static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
/* DMA errors handling.*/
#if defined(STM32_SPI_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_SPI_DMA_ERROR_HOOK(spip);
}
#else
(void)flags;
#endif
/* Stop everything.*/
dmaStreamDisable(spip->dmatx);
dmaStreamDisable(spip->dmarx);
/* Portable SPI ISR code defined in the high level driver, note, it is
a macro.*/
_spi_isr_code(spip);
}
/**
* @brief Shared end-of-tx service routine.
*
* @param[in] spip pointer to the @p SPIDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
/* DMA errors handling.*/
#if defined(STM32_SPI_DMA_ERROR_HOOK)
@ -106,17 +132,8 @@ static void spi_lld_serve_interrupt(SPIDriver *spip) {
sr = spip->spi->SR & spip->spi->IER;
spip->spi->IFCR = sr;
if ((sr & SPI_SR_EOT) != 0U) {
/* Stop everything.*/
dmaStreamDisable(spip->dmatx);
dmaStreamDisable(spip->dmarx);
/* Portable SPI ISR code defined in the high level driver, note, it is
a macro.*/
_spi_isr_code(spip);
}
else if ((sr & SPI_SR_OVR) != 0U) {
/* TODO: faut notification.*/
if ((sr & SPI_SR_OVR) != 0U) {
/* TODO: fault notification.*/
}
}
@ -393,15 +410,17 @@ void spi_lld_start(SPIDriver *spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI1(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI1_RX);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI1_TX);
}
#endif
#if STM32_SPI_USE_SPI2
@ -409,15 +428,17 @@ void spi_lld_start(SPIDriver *spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI2(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI2_RX);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI2_TX);
}
#endif
#if STM32_SPI_USE_SPI3
@ -425,15 +446,17 @@ void spi_lld_start(SPIDriver *spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI3(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI3_RX);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI3_TX);
}
#endif
#if STM32_SPI_USE_SPI4
@ -441,15 +464,17 @@ void spi_lld_start(SPIDriver *spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI4(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI4_RX);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI4_TX);
}
#endif
#if STM32_SPI_USE_SPI5
@ -457,15 +482,17 @@ void spi_lld_start(SPIDriver *spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI5(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI5_RX);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX1_SPI5_TX);
}
#endif
#if STM32_SPI_USE_SPI6
@ -473,23 +500,23 @@ void spi_lld_start(SPIDriver *spip) {
bool b;
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_serve_dma_interrupt,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(!b, "stream already allocated");
rccEnableSPI6(false);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX2_SPI6_RX);
dmaSetRequestSource(spip->dmarx, STM32_DMAMUX2_SPI6_TX);
}
#endif
/* DMA setup.*/
dmaStreamSetPeripheral(spip->dmarx, &spip->spi->RXDR);
dmaStreamSetPeripheral(spip->dmatx, &spip->spi->TXDR);
dmaStreamSetTransactionSize(spip->dmarx, 0U);
dmaStreamSetTransactionSize(spip->dmatx, 0U);
}
/* Configuration-specific DMA setup.*/
@ -532,7 +559,7 @@ void spi_lld_start(SPIDriver *spip) {
spip->spi->CR2 = 0U;
spip->spi->CFG1 = cfg1;
spip->spi->CFG2 = spip->config->cfg2 | SPI_CFG2_MASTER;
spip->spi->IER = SPI_IER_OVRIE | SPI_IER_EOTIE;
spip->spi->IER = SPI_IER_OVRIE;
spip->spi->IFCR = 0xFFFFFFFFU;
spip->spi->CR1 |= SPI_CR1_SPE;
}
@ -629,15 +656,16 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
spip->spi->CR2 = (uint32_t)n;
spip->spi->CR1 |= SPI_CR1_CSTART;
}
@ -662,15 +690,16 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
spip->spi->CR2 = (uint32_t)n;
spip->spi->CR1 |= SPI_CR1_CSTART;
}
@ -692,15 +721,16 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
spip->spi->CR2 = (uint32_t)n;
spip->spi->CR1 |= SPI_CR1_CSTART;
}
@ -722,15 +752,16 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
osalDbgAssert(n < 65536, "unsupported DMA transfer size");
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
spip->spi->CR2 = (uint32_t)n;
spip->spi->CR1 |= SPI_CR1_CSTART;
}

144
os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h
View File

@ -142,6 +142,90 @@
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#endif
/**
* @brief SPI1 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI1_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_RX_DMA_CHANNEL 10
#endif
/**
* @brief SPI1 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI1_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_TX_DMA_CHANNEL 11
#endif
/**
* @brief SPI2 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI2_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_RX_DMA_CHANNEL 12
#endif
/**
* @brief SPI2 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI2_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_TX_DMA_CHANNEL 13
#endif
/**
* @brief SPI3 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI3_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_RX_DMA_CHANNEL 10
#endif
/**
* @brief SPI3 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI3_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_TX_DMA_CHANNEL 11
#endif
/**
* @brief SPI4 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI4_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI4_RX_DMA_CHANNEL 12
#endif
/**
* @brief SPI4 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI4_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI4_TX_DMA_CHANNEL 13
#endif
/**
* @brief SPI5 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI5_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI5_RX_DMA_CHANNEL 12
#endif
/**
* @brief SPI5 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI5_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI5_TX_DMA_CHANNEL 13
#endif
/**
* @brief SPI6 RX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI6_RX_BDMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI6_RX_BDMA_CHANNEL 2
#endif
/**
* @brief SPI6 TX DMA channel setting.
*/
#if !defined(STM32_SPI_SPI6_TX_BDMA_CHANNEL) || defined(__DOXYGEN__)
#define STM32_SPI_SPI6_TX_BDMA_CHANNEL 3
#endif
/**
* @brief SPI1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
@ -273,6 +357,66 @@
#error "Invalid IRQ priority assigned to SPI6"
#endif
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI1 RX"
#endif
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI1 TX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI2 RX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI2 TX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI3 RX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI3 TX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI4 RX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI4 TX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_RX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI5 RX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_TX_DMA_CHANNEL)
#error "Invalid DMA channel assigned to SPI5 TX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_RX_BDMA_CHANNEL)
#error "Invalid BDMA channel assigned to SPI6 RX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_TX_BDMA_CHANNEL)
#error "Invalid BDMA channel assigned to SPI1 TX"
#endif
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI1"