diff --git a/demos/STM32/RT-STM32H755I-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H755I-NUCLEO144/cfg/mcuconf.h
index 0f0dca6b3..de36f80ca 100644
--- a/demos/STM32/RT-STM32H755I-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32H755I-NUCLEO144/cfg/mcuconf.h
@@ -61,7 +61,7 @@
 #define STM32_VOS                           STM32_VOS_SCALE1
 #define STM32_PWR_CR1                       (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
 #define STM32_PWR_CR2                       (PWR_CR2_BREN)
-#define STM32_PWR_CR3                       (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
+#define STM32_PWR_CR3                       (PWR_CR3_SMPSEN | PWR_CR3_USB33DEN)
 #define STM32_PWR_CPUCR                     0
 
 /*
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index 011c13731..8ea0d7d50 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -97,16 +97,22 @@ static inline void init_pwr(void) {
   (void)pwr;
 #endif
 
+  /* Lower C3 byte, it must be programmed at very first, then waiting for
+     power supply to stabilize.*/
+  PWR->CR3   = STM32_PWR_CR3 & 0x000000FFU;
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0)
+    ; /* CHTODO timeout handling.*/
+
   PWR->CR1   = STM32_PWR_CR1 | 0xF0000000U;
   PWR->CR2   = STM32_PWR_CR2;
-  PWR->CR3   = STM32_PWR_CR3 | 0x00000004U;     /* SCUEN enforced.          */
+  PWR->CR3   = STM32_PWR_CR3;   /* Other bits, lower byte is not changed.   */
   PWR->CPUCR = STM32_PWR_CPUCR;
   PWR->D3CR  = STM32_VOS;
 #if !defined(STM32_ENFORCE_H7_REV_V)
   SYSCFG->PWRCR = STM32_ODEN;
 #endif
   while ((PWR->D3CR & PWR_D3CR_VOSRDY) == 0)
-    ;
+    ; /* CHTODO timeout handling.*/
 #if STM32_PWR_CR2 & PWR_CR2_BREN
 //  while ((PWR->CR2 & PWR_CR2_BRRDY) == 0)
 //    ;