From 089892eb2c66ae7da173ac20ead82ff5d277486f Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Mon, 13 Jul 2020 07:36:30 +0000 Subject: [PATCH] Stand-alone ARMv6-M port. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13752 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- demos/STM32/RT-STM32G071RB-NUCLEO64/Makefile | 2 +- os/common/ports/ARMv6-M/chcore.c | 113 +++- os/common/ports/ARMv6-M/chcore.h | 549 +++++++++++++++--- .../ports/ARMv6-M/compilers/GCC/chcoreasm.S | 32 +- .../ports/ARMv6-M/compilers/GCC/mk/port.mk | 13 + .../ARMv6-M/compilers/GCC/mk/port_v6m.mk | 13 - .../ARMv6-M/compilers/GCC/mk/port_v7m.mk | 13 - .../ARMv6-M/compilers/GCC/mk/port_v8m-ml.mk | 13 - readme.txt | 3 + 9 files changed, 604 insertions(+), 147 deletions(-) create mode 100644 os/common/ports/ARMv6-M/compilers/GCC/mk/port.mk delete mode 100644 os/common/ports/ARMv6-M/compilers/GCC/mk/port_v6m.mk delete mode 100644 os/common/ports/ARMv6-M/compilers/GCC/mk/port_v7m.mk delete mode 100644 os/common/ports/ARMv6-M/compilers/GCC/mk/port_v8m-ml.mk diff --git a/demos/STM32/RT-STM32G071RB-NUCLEO64/Makefile b/demos/STM32/RT-STM32G071RB-NUCLEO64/Makefile index aec3369aa..ed21bc913 100644 --- a/demos/STM32/RT-STM32G071RB-NUCLEO64/Makefile +++ b/demos/STM32/RT-STM32G071RB-NUCLEO64/Makefile @@ -105,7 +105,7 @@ include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G071RB/board.mk include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk +include $(CHIBIOS)/os/common/ports/ARMv6-M/compilers/GCC/mk/port.mk # Auto-build files in ./source recursively. include $(CHIBIOS)/tools/mk/autobuild.mk # Other files (optional). diff --git a/os/common/ports/ARMv6-M/chcore.c b/os/common/ports/ARMv6-M/chcore.c index 06a0ca8fa..3ea79fb3a 100644 --- a/os/common/ports/ARMv6-M/chcore.c +++ b/os/common/ports/ARMv6-M/chcore.c @@ -18,10 +18,10 @@ */ /** - * @file ARMCMx/chcore.c - * @brief ARM Cortex-Mx port code. + * @file ARMv6-M/chcore.c + * @brief ARMv6-M port code. * - * @addtogroup ARMCMx_CORE + * @addtogroup ARMv6_M_CORE * @{ */ @@ -47,8 +47,115 @@ /* Module local functions. */ /*===========================================================================*/ +/*===========================================================================*/ +/* Module interrupt handlers. */ +/*===========================================================================*/ + +#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__) +/** + * @brief NMI vector. + * @details The NMI vector is used for exception mode re-entering after a + * context switch. + */ +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void NMI_Handler(void) { +/*lint -restore*/ + + /* The port_extctx structure is pointed by the PSP register.*/ + struct port_extctx *ctxp = (struct port_extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ctxp); + + /* Restoring the normal interrupts status.*/ + port_unlock_from_isr(); +} +#endif /* !CORTEX_ALTERNATE_SWITCH */ + +#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + */ +/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/ +void PendSV_Handler(void) { +/*lint -restore*/ + + /* The port_extctx structure is pointed by the PSP register.*/ + struct port_extctx *ctxp = (struct port_extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ctxp); +} +#endif /* CORTEX_ALTERNATE_SWITCH */ + /*===========================================================================*/ /* Module exported functions. */ /*===========================================================================*/ +/** + * @brief Port-related initialization code. + * + * @param[in, out] oip pointer to the @p os_instance_t structure + * + * @notapi + */ +void port_init(os_instance_t *oip) { + + (void)oip; + + NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV); +} + +/** + * @brief IRQ epilogue code. + * + * @param[in] lr value of the @p LR register on ISR entry + */ +void __port_irq_epilogue(uint32_t lr) { + + if (lr != 0xFFFFFFF1U) { + struct port_extctx *ectxp; + + port_lock_from_isr(); + + /* The extctx structure is pointed by the PSP register.*/ + ectxp = (struct port_extctx *)__get_PSP(); + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ectxp--; + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ectxp); + + /* Setting up a fake XPSR register value.*/ + ectxp->xpsr = 0x01000000U; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ectxp->pc = (uint32_t)__port_switch_from_isr; + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ectxp->pc = (uint32_t)__port_exit_from_isr; + } + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + } +} + /** @} */ diff --git a/os/common/ports/ARMv6-M/chcore.h b/os/common/ports/ARMv6-M/chcore.h index c93aa86f7..ec3752213 100644 --- a/os/common/ports/ARMv6-M/chcore.h +++ b/os/common/ports/ARMv6-M/chcore.h @@ -18,29 +18,23 @@ */ /** - * @file ARMCMx/chcore.h - * @brief ARM Cortex-Mx port macros and structures. + * @file ARMv6-M/chcore.h + * @brief ARMv6-M port macros and structures. * - * @addtogroup ARMCMx_CORE + * @addtogroup ARMv6_M_CORE * @{ */ #ifndef CHCORE_H #define CHCORE_H +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + /*===========================================================================*/ /* Module constants. */ /*===========================================================================*/ -/** - * @name Architecture and Compiler - * @{ - */ -/** - * @brief Macro defining a generic ARM architecture. - */ -#define PORT_ARCHITECTURE_ARM - /* The following code is not processed when the file is included from an asm module because those intrinsic macros are not necessarily defined by the assembler too.*/ @@ -63,79 +57,41 @@ #endif #endif /* !defined(_FROM_ASM_) */ - /** @} */ -/* Inclusion of the Cortex-Mx implementation specific parameters.*/ -#include "cmparams.h" - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ +/** + * @name Port Capabilities and Constants + * @{ + */ +#define PORT_SUPPORTS_RT FALSE /** - * @brief Enables an alternative timer implementation. - * @details Usually the port uses a timer interface defined in the file - * @p chcore_timer.h, if this option is enabled then the file - * @p chcore_timer_alt.h is included instead. + * @brief Natural alignment constant. + * @note It is the minimum alignment for pointer-size variables. */ -#if !defined(PORT_USE_ALT_TIMER) -#define PORT_USE_ALT_TIMER FALSE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/* The following code is not processed when the file is included from an - asm module.*/ -#if !defined(_FROM_ASM_) +#define PORT_NATURAL_ALIGN sizeof (void *) /** - * @brief Type of stack and memory alignment enforcement. - * @note In this architecture the stack alignment is enforced to 64 bits, - * 32 bits alignment is supported by hardware but deprecated by ARM, - * the implementation choice is to not offer the option. + * @brief Stack alignment constant. + * @note It is the alignment required for the stack pointer. */ -typedef uint64_t stkalign_t; - -/* The following declarations are there just for Doxygen documentation, the - real declarations are inside the sub-headers being specific for the - sub-architectures.*/ -#if defined(__DOXYGEN__) -/** - * @brief Interrupt saved context. - * @details This structure represents the stack frame saved during a - * preemption-capable interrupt handler. - * @note It is implemented to match the Cortex-Mx exception context. - */ -struct port_extctx {}; +#define PORT_STACK_ALIGN sizeof (stkalign_t) /** - * @brief System saved context. - * @details This structure represents the inner stack frame during a context - * switch. + * @brief Working Areas alignment constant. + * @note It is the alignment to be enforced for thread working areas. */ -struct port_intctx {}; +#define PORT_WORKING_AREA_ALIGN PORT_STACK_ALIGN +/** @} */ /** - * @brief Platform dependent part of the @p thread_t structure. - * @details In this port the structure just holds a pointer to the - * @p port_intctx structure representing the stack pointer - * at context switch time. + * @name Priority Ranges + * @{ */ -struct port_context {}; -#endif /* defined(__DOXYGEN__) */ - -#endif /* !defined(_FROM_ASM_) */ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0U /** * @brief Total priority levels. @@ -155,11 +111,218 @@ struct port_context {}; */ #define CORTEX_MAXIMUM_PRIORITY 0U +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always has the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + /** * @brief Priority level to priority mask conversion macro. */ #define CORTEX_PRIO_MASK(n) \ ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS)) +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * @note In this port this value is conservatively set to 64 because the + * function @p chSchDoReschedule() can have a stack frame, especially + * with compiler optimizations disabled. The value can be reduced + * when compiler optimizations are enabled. + */ +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 64 +#endif + +/** + * @brief Enables an alternative timer implementation. + * @details Usually the port uses a timer interface defined in the file + * @p chcore_timer.h, if this option is enabled then the file + * @p chcore_timer_alt.h is included instead. + */ +#if !defined(PORT_USE_ALT_TIMER) +#define PORT_USE_ALT_TIMER FALSE +#endif + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#if !defined(CORTEX_ENABLE_WFI_IDLE) +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief Alternate preemption method. + * @details Activating this option will make the Kernel use the PendSV + * handler for preemption instead of the NMI handler. + */ +#ifndef CORTEX_ALTERNATE_SWITCH +#define CORTEX_ALTERNATE_SWITCH FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(CH_CUSTOMER_LIC_PORT_CM0) + #error "CH_CUSTOMER_LIC_PORT_CM0 not defined" +#endif + +#if CH_CUSTOMER_LIC_PORT_CM0 == FALSE + #error "ChibiOS Cortex-M0 port not licensed" +#endif + +/* Handling a GCC problem impacting ARMv6-M.*/ +#if defined(__GNUC__) && !defined(PORT_IGNORE_GCC_VERSION_CHECK) + #if ( __GNUC__ > 5 ) && ( __GNUC__ < 10 ) + #define GCC_VERSION ( __GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ ) + #if ( __GNUC__ == 7 ) && ( GCC_VERSION >= 70500 ) + #elif ( __GNUC__ == 8 ) && ( GCC_VERSION >= 80400 ) + #elif ( __GNUC__ == 9 ) && ( GCC_VERSION >= 90300 ) + #else + #warning "This compiler has a know problem with Cortex-M0, see GCC bugs: 88167, 88656." + #endif + #endif +#endif + +/** + * @name Architecture + * @{ + */ +/** + * @brief Macro defining a generic ARM architecture. + */ +#define PORT_ARCHITECTURE_ARM + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define PORT_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define PORT_ARCHITECTURE_NAME "ARMv6-M" + +#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) || \ + defined(__DOXYGEN__) + + /** + * @brief Name of the architecture variant. + */ + #define PORT_CORE_VARIANT_NAME "Cortex-M0" + +#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT) + #define PORT_CORE_VARIANT_NAME "Cortex-M0+" + +#else + #error "unknown ARMv6-M variant" +#endif + +/** + * @brief Port-specific information string. + */ +#if (CORTEX_ALTERNATE_SWITCH == FALSE) || defined(__DOXYGEN__) + #define PORT_INFO "Preemption through NMI" +#else + #define PORT_INFO "Preemption through PendSV" +#endif +/** @} */ + +/** + * @brief Maximum usable priority for normal ISRs. + */ +#if (CORTEX_ALTERNATE_SWITCH == TRUE) || defined(__DOXYGEN__) + #define CORTEX_MAX_KERNEL_PRIORITY 1 +#else + #define CORTEX_MAX_KERNEL_PRIORITY 0 +#endif + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/** + * @brief Type of stack and memory alignment enforcement. + * @note In this architecture the stack alignment is enforced to 64 bits, + * 32 bits alignment is supported by hardware but deprecated by ARM, + * the implementation choice is to not offer the option. + */ +typedef uint64_t stkalign_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct port_extctx { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr_thd; + uint32_t pc; + uint32_t xpsr; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switch. + */ +struct port_intctx { + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t lr; +}; + +/** + * @brief Platform dependent part of the @p thread_t structure. + * @details In this port the structure just holds a pointer to the + * @p port_intctx structure representing the stack pointer + * at context switch time. + */ +struct port_context { + struct port_intctx *sp; +}; + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ /** * @brief Priority level verification macro. @@ -173,28 +336,121 @@ struct port_context {}; #define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \ (((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS)) +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p port_intctx structure. + */ +#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) do { \ + (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \ + sizeof (struct port_intctx)); \ + (tp)->ctx.sp->r4 = (uint32_t)(pf); \ + (tp)->ctx.sp->r5 = (uint32_t)(arg); \ + (tp)->ctx.sp->lr = (uint32_t)__port_thread_start; \ +} while (0) + +/** + * @brief Computes the thread working area global size. + * @note There is no need to perform alignments in this macro. + */ +#define PORT_WA_SIZE(n) (sizeof (struct port_intctx) + \ + sizeof (struct port_extctx) + \ + ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK))) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + * + * @param[in] s the name to be assigned to the stack array + * @param[in] n the stack size to be assigned to the thread + */ +#define PORT_WORKING_AREA(s, n) \ + stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)] + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#if defined(__GNUC__) || defined(__DOXYGEN__) + #define PORT_IRQ_PROLOGUE() \ + uint32_t _saved_lr = (uint32_t)__builtin_return_address(0) +#elif defined(__ICCARM__) + #define PORT_IRQ_PROLOGUE() \ + uint32_t _saved_lr = (uint32_t)__get_LR() +#elif defined(__CC_ARM) + #define PORT_IRQ_PROLOGUE() \ + uint32_t _saved_lr = (uint32_t)__return_address() +#endif + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() __port_irq_epilogue(_saved_lr) + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#ifdef __cplusplus + #define PORT_IRQ_HANDLER(id) extern "C" void id(void) +#else + #define PORT_IRQ_HANDLER(id) void id(void) +#endif + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#ifdef __cplusplus + #define PORT_FAST_IRQ_HANDLER(id) extern "C" void id(void) +#else + #define PORT_FAST_IRQ_HANDLER(id) void id(void) +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__) + #define port_switch(ntp, otp) __port_switch(ntp, otp) +#else + #define port_switch(ntp, otp) do { \ + struct port_intctx *r13 = (struct port_intctx *)__get_PSP(); \ + if ((stkalign_t *)(r13 - 1) < (otp)->wabase) { \ + chSysHalt("stack overflow"); \ + } \ + __port_switch(ntp, otp); \ + } while (0) +#endif + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -/* Includes the sub-architecture-specific part.*/ -#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1) -#include "chcore_v6m.h" -#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4) || (CORTEX_MODEL == 7) -#include "mpu.h" -#include "chcore_v7m.h" -#elif (CORTEX_MODEL == 33) || (CORTEX_MODEL == 55) -#include "mpu_v8m.h" -#include "chcore_v8m-ml.h" -#else -#error "unknown Cortex-M variant" +#ifdef __cplusplus +extern "C" { +#endif + void port_init(os_instance_t *oip); + void __port_irq_epilogue(uint32_t lr); + void __port_switch(thread_t *ntp, thread_t *otp); + void __port_thread_start(void); + void __port_switch_from_isr(void); + void __port_exit_from_isr(void); +#ifdef __cplusplus +} #endif - -#if !defined(_FROM_ASM_) #if CH_CFG_ST_TIMEDELTA > 0 #if PORT_USE_ALT_TIMER == FALSE @@ -204,6 +460,123 @@ struct port_context {}; #endif /* PORT_USE_ALT_TIMER != FALSE */ #endif /* CH_CFG_ST_TIMEDELTA > 0 */ +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns a word encoding the current interrupts status. + * + * @return The interrupts status. + */ +static inline syssts_t port_get_irq_status(void) { + + return (syssts_t)__get_PRIMASK(); +} + +/** + * @brief Checks the interrupt status. + * + * @param[in] sts the interrupt status word + * + * @return The interrupt status. + * @retval false the word specified a disabled interrupts status. + * @retval true the word specified an enabled interrupts status. + */ +static inline bool port_irq_enabled(syssts_t sts) { + + return (sts & (syssts_t)1) == (syssts_t)0; +} + +/** + * @brief Determines the current execution context. + * + * @return The execution context. + * @retval false not running in ISR mode. + * @retval true running in ISR mode. + */ +static inline bool port_is_isr_context(void) { + + return (bool)((__get_IPSR() & 0x1FFU) != 0U); +} + +/** + * @brief Kernel-lock action. + * @details In this port this function disables interrupts globally. + */ +static inline void port_lock(void) { + + __disable_irq(); +} + +/** + * @brief Kernel-unlock action. + * @details In this port this function enables interrupts globally. + */ +static inline void port_unlock(void) { + + __enable_irq(); +} + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details In this port this function disables interrupts globally. + * @note Same as @p port_lock() in this port. + */ +static inline void port_lock_from_isr(void) { + + port_lock(); +} + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details In this port this function enables interrupts globally. + * @note Same as @p port_lock() in this port. + */ +static inline void port_unlock_from_isr(void) { + + port_unlock(); +} + +/** + * @brief Disables all the interrupt sources. + */ +static inline void port_disable(void) { + + __disable_irq(); +} + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +static inline void port_suspend(void) { + + __disable_irq(); +} + +/** + * @brief Enables all the interrupt sources. + */ +static inline void port_enable(void) { + + __enable_irq(); +} + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +static inline void port_wait_for_interrupt(void) { + +#if CORTEX_ENABLE_WFI_IDLE == TRUE + __WFI(); +#endif +} + #endif /* !defined(_FROM_ASM_) */ #endif /* CHCORE_H */ diff --git a/os/common/ports/ARMv6-M/compilers/GCC/chcoreasm.S b/os/common/ports/ARMv6-M/compilers/GCC/chcoreasm.S index a62b6596c..c17bcb2cc 100644 --- a/os/common/ports/ARMv6-M/compilers/GCC/chcoreasm.S +++ b/os/common/ports/ARMv6-M/compilers/GCC/chcoreasm.S @@ -74,8 +74,8 @@ * Performs a context switch between two threads. *--------------------------------------------------------------------------*/ .thumb_func - .globl _port_switch -_port_switch: + .globl __port_switch +__port_switch: push {r4, r5, r6, r7, lr} mov r4, r8 mov r5, r9 @@ -104,20 +104,20 @@ _port_switch: * called on thread function return. *--------------------------------------------------------------------------*/ .thumb_func - .globl _port_thread_start -_port_thread_start: + .globl __port_thread_start +__port_thread_start: #if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock + bl __dbg_check_unlock #endif #if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd + bl __stats_stop_measure_crit_thd #endif cpsie i mov r0, r5 blx r4 movs r0, #0 /* MSG_OK */ bl chThdExit -_zombies: b _zombies +.zombies: b .zombies /*--------------------------------------------------------------------------* * Post-IRQ switch code. @@ -125,23 +125,23 @@ _zombies: b _zombies * Exception handlers return here for context switching. *--------------------------------------------------------------------------*/ .thumb_func - .globl _port_switch_from_isr -_port_switch_from_isr: + .globl __port_switch_from_isr +__port_switch_from_isr: #if CH_DBG_STATISTICS - bl _stats_start_measure_crit_thd + bl __stats_start_measure_crit_thd #endif #if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_lock + bl __dbg_check_lock #endif - bl chSchDoReschedule + bl chSchDoPreemption #if CH_DBG_SYSTEM_STATE_CHECK - bl _dbg_check_unlock + bl __dbg_check_unlock #endif #if CH_DBG_STATISTICS - bl _stats_stop_measure_crit_thd + bl __stats_stop_measure_crit_thd #endif - .globl _port_exit_from_isr -_port_exit_from_isr: + .globl __port_exit_from_isr +__port_exit_from_isr: ldr r2, .L2 ldr r3, .L3 str r3, [r2, #0] diff --git a/os/common/ports/ARMv6-M/compilers/GCC/mk/port.mk b/os/common/ports/ARMv6-M/compilers/GCC/mk/port.mk new file mode 100644 index 000000000..024a499ce --- /dev/null +++ b/os/common/ports/ARMv6-M/compilers/GCC/mk/port.mk @@ -0,0 +1,13 @@ +# List of the ChibiOS/RT Cortex-M0 port files. +PORTSRC = $(CHIBIOS)/os/common/ports/ARMv6-M/chcore.c + +PORTASM = $(CHIBIOS)/os/common/ports/ARMv6-M/compilers/GCC/chcoreasm.S + +PORTINC = $(CHIBIOS)/os/common/ports/ARMv6-M \ + $(CHIBIOS)/os/common/ports/ARMv6-M/compilers/GCC + +# Shared variables +ALLXASMSRC += $(PORTASM) +ALLCSRC += $(PORTSRC) +ALLINC += $(PORTINC) + diff --git a/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v6m.mk b/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v6m.mk deleted file mode 100644 index 1fefa0441..000000000 --- a/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v6m.mk +++ /dev/null @@ -1,13 +0,0 @@ -# List of the ChibiOS/RT Cortex-M0 STM32F0xx port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/chcore.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/chcore_v6m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S - -PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC - -# Shared variables -ALLXASMSRC += $(PORTASM) -ALLCSRC += $(PORTSRC) -ALLINC += $(PORTINC) diff --git a/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v7m.mk b/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v7m.mk deleted file mode 100644 index fb89795e8..000000000 --- a/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v7m.mk +++ /dev/null @@ -1,13 +0,0 @@ -# List of the ChibiOS/RT ARMv7M generic port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/chcore.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/chcore_v7m.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S - -PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC - -# Shared variables -ALLXASMSRC += $(PORTASM) -ALLCSRC += $(PORTSRC) -ALLINC += $(PORTINC) diff --git a/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v8m-ml.mk b/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v8m-ml.mk deleted file mode 100644 index 27b7b74eb..000000000 --- a/os/common/ports/ARMv6-M/compilers/GCC/mk/port_v8m-ml.mk +++ /dev/null @@ -1,13 +0,0 @@ -# List of the ChibiOS/RT ARMv8M-mainline generic port files. -PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/chcore.c \ - $(CHIBIOS)/os/common/ports/ARMCMx/chcore_v8m-ml.c - -PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v8m-ml.S - -PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \ - $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC - -# Shared variables -ALLXASMSRC += $(PORTASM) -ALLCSRC += $(PORTSRC) -ALLINC += $(PORTINC) diff --git a/readme.txt b/readme.txt index 762f6c7b4..ca5dc03b4 100644 --- a/readme.txt +++ b/readme.txt @@ -74,6 +74,9 @@ ***************************************************************************** *** Next *** +- NEW: Stand-alone ARMv6-M port. +- NEW: Stand-alone ARMv7-M port. +- NEW: Merged RT7. - RT: New API for high resolution monotonic time stamps. - NEW: Updated FatFS to version 0.14. - NEW: Added a new setting to STM32 USBv1 allowing for some clock deviation