Fixed Bug #779.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9789 35acf78f-673a-0410-8e92-d51de3d6d3f4

os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h

@@ -403,10 +403,11 @@
 #endif
 
 #if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE)) ||                                 \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) ||                              \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2) ||                              \
+    (((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                             \
+		  (STM32_MCOSEL == STM32_MCOSEL_PLL2) ||                                \
+			(STM32_MCOSEL == STM32_MCOSEL_PLL3) ||                                \
+			(STM32_MCOSEL == STM32_MCOSEL_PLL3DIV2)) &&                           \
+		 (STM32_PLLSRC == STM32_PLLSRC_HSE)) ||                                 \
     (STM32_MCOSEL == STM32_MCOSEL_XT1)
 #error "HSE not enabled, required by STM32_MCOSEL"
 #endif
@@ -465,8 +466,7 @@
 
 /* PLL2 activation conditions.*/
 #if ((STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) && STM32_ACTIVATE_PLL1) || \
-    (STM32_MCOSEL == STM32_MCOSEL_PLL2DIV2) ||                              \
-    defined(__DOXYGEN__)
+    (STM32_MCOSEL == STM32_MCOSEL_PLL2) || defined(__DOXYGEN__)
 /**
  * @brief   PLL2 activation flag.
  */

readme.txt

@@ -126,6 +126,8 @@
 - RT:  Merged RT4.
 - NIL: Merged NIL2.
 - NIL: Added STM32F7 demo.
+- HAL: Fixed wrong HSE checks and PLL2 enable switch in STM32F105 and
+       STM32F107 port (bug #779)(backported to 16.1.6, 3.0.6, 2.6.10).
 - HAL: Fixed wrong SRAM2_BASE in STM32F7xx port (bug #778)
        (backported to 16.1.6).
 - HAL: Added DAC configs in RT-STM32F051-DISCOVERY\mcuconf.h (bug #777)