git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@142 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
430010715e
commit
0bb20d36f4
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@ -162,19 +162,11 @@ void chSysPuts(char *msg) {
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__attribute__((naked, weak))
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void IrqHandler(void) {
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asm(".code 32 \n\t" \
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"stmfd sp!, {r0-r3, r12, lr} \n\t");
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#ifdef THUMB
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t");
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VICVectAddr = 0;
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asm("ldr r0, =IrqCommon \n\t" \
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"bx r0 \n\t");
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#else
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VICVectAddr = 0;
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asm("b IrqCommon \n\t");
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#endif
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chSysIRQEnterI();
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/* nothing */
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chSysIRQExitI();
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}
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/*
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@ -183,21 +175,148 @@ void IrqHandler(void) {
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__attribute__((naked, weak))
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void T0IrqHandler(void) {
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asm(".code 32 \n\t" \
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"stmfd sp!, {r0-r3, r12, lr} \n\t");
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chSysIRQEnterI();
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T0IR = 1; /* Clear interrupt on match MR0. */
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chSysTimerHandlerI();
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chSysIRQExitI();
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}
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/*
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* Common IRQ exit code, \p chSysIRQExitI() just jumps here.
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*
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* System stack frame structure after a context switch in the
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* interrupt handler:
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*
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* High +------------+
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* | LR_USR | -+
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* | R12 | |
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* | R3 | |
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* | R2 | | External context: IRQ handler frame
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* | R1 | |
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* | R0 | |
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* | LR_IRQ | | (user code return address)
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* | SPSR | -+ (user code status)
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* | .... | <- chSchDoRescheduleI() stack frame, optimize it for space
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* | LR | -+ (system code return address)
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* | R11 | |
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* | R10 | |
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* | R9 | |
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* | R8 | | Internal context: chSysSwitchI() frame
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* | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
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* | R6 | |
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* | R5 | |
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* SP-> | R4 | -+
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* Low +------------+
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*/
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__attribute__((naked, weak))
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void IrqCommon(void) {
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register BOOL b asm("r0");
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VICVectAddr = 0;
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b = chSchRescRequiredI();
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#ifdef THUMB
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t");
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T0IR = 1; /* Clear interrupt on match MR0. */
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chSysTimerHandlerI();
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VICVectAddr = 0;
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asm("ldr r0, =IrqCommon \n\t" \
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"bx r0 \n\t");
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asm(".p2align 2,, \n\t" \
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"mov lr, pc \n\t" \
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"bx lr \n\t" \
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".code 32 \n\t");
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#endif
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/*
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* If a reschedulation is not required then just returns from the IRQ.
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*/
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asm("cmp r0, #0 \n\t" \
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"ldmeqfd sp!, {r0-r3, r12, lr} \n\t" \
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"subeqs pc, lr, #4 \n\t");
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/*
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* Reschedulation required, saves the external context on the
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* system/user stack and empties the IRQ stack.
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*/
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asm(".set MODE_IRQ, 0x12 \n\t" \
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".set MODE_SYS, 0x1F \n\t" \
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".set I_BIT, 0x80 \n\t" \
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"ldmfd sp!, {r0-r3, r12, lr} \n\t" \
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"msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
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"stmfd sp!, {r0-r3, r12, lr} \n\t" \
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"msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
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"mrs r0, SPSR \n\t" \
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"mov r1, lr \n\t" \
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"msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
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"stmfd sp!, {r0, r1} \n\t");
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#ifdef THUMB_NO_INTERWORKING
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t" \
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"bl chSchDoRescheduleI \n\t" \
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".p2align 2,, \n\t" \
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"mov lr, pc \n\t" \
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"bx lr \n\t" \
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".code 32 \n\t");
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#else
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T0IR = 1; /* Clear interrupt on match MR0. */
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chSysTimerHandlerI();
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VICVectAddr = 0;
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asm("b IrqCommon \n\t");
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asm("bl chSchDoRescheduleI \n\t");
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#endif
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/*
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* Restores the external context.
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*/
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asm("ldmfd sp!, {r0, r1} \n\t" \
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"msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
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"msr SPSR_fsxc, r0 \n\t" \
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"mov lr, r1 \n\t" \
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"msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
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"ldmfd sp!, {r0-r3, r12, lr} \n\t" \
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"msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
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"subs pc, lr, #4 \n\t");
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/*
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* Threads entry/exit code. It is declared weak so you can easily replace it.
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* NOTE: It is always invoked in ARM mode, it does the mode switching.
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* NOTE: It is included into IrqCommon to make sure the symbol refers to
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* 32 bit code.
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*/
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asm(".set F_BIT, 0x40 \n\t" \
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".weak threadstart \n\t" \
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".globl threadstart \n\t" \
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"threadstart: \n\t" \
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"msr CPSR_c, #MODE_SYS \n\t");
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#ifndef THUMB_NO_INTERWORKING
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asm("mov r0, r5 \n\t" \
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"mov lr, pc \n\t" \
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"bx r4 \n\t" \
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"bl chThdExit \n\t");
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#else
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t" \
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"mov r0, r5 \n\t" \
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"bl jmpr4 \n\t" \
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"bl chThdExit \n\t" \
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"jmpr4: \n\t" \
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"bx r4 \n\t");
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#endif
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}
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/*
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* System halt.
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*/
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__attribute__((naked, weak))
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void chSysHalt(void) {
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asm(".set F_BIT, 0x40 \n\t" \
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".set I_BIT, 0x80 \n\t");
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#ifdef THUMB
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asm(".p2align 2,, \n\t" \
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"mov r0, pc \n\t" \
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"bx r0 \n\t");
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#endif
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asm(".code 32 \n\t" \
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".weak _halt32 \n\t" \
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".globl _halt32 \n\t" \
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"_halt32: \n\t" \
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"mrs r0, CPSR \n\t" \
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"orr r0, #I_BIT | F_BIT \n\t" \
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"msr CPSR_c, r0 \n\t" \
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".loop: \n\t" \
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"b .loop \n\t");
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}
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@ -92,7 +92,7 @@ extern void chSysUnlock(void);
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#define INT_REQUIRED_STACK 0x10
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#else /* !THUMB */
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#define INT_REQUIRED_STACK 0
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#endif /* THUMB */
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#endif /* !THUMB */
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#define StackAlign(n) ((((n) - 1) | 3) + 1)
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#define UserStackSize(n) StackAlign(sizeof(Thread) + \
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sizeof(struct intctx) + \
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@ -101,16 +101,37 @@ extern void chSysUnlock(void);
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INT_REQUIRED_STACK)
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#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2];
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#ifdef THUMB
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#define chSysIRQEnterI() { \
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asm(".code 32 \n\t" \
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"stmfd sp!, {r0-r3, r12, lr} \n\t" \
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"add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t"); \
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}
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#define chSysIRQExitI() { \
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VICVectAddr = 0; \
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asm("ldr r0, =IrqCommon \n\t" \
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"bx r0 \n\t"); \
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}
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#else /* !THUMB */
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#define chSysIRQEnterI() { \
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asm("stmfd sp!, {r0-r3, r12, lr} \n\t"); \
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}
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#define chSysIRQExitI() { \
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asm("b IrqCommon \n\t"); \
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}
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#endif /* !THUMB */
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/* It requires zero bytes, but better be safe.*/
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#define IDLE_THREAD_STACK_SIZE 8
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void _IdleThread(void *p) __attribute__((noreturn));
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void chSysHalt(void) __attribute__((noreturn));
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void chSysHalt(void);
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void chSysSwitchI(Context *oldp, Context *newp);
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void chSysPuts(char *msg);
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void threadstart(void);
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void DefFiqHandler(void);
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void DefIrqHandler(void);
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void SpuriousHandler(void);
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#endif /* _CHCORE_H_ */
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@ -34,73 +34,15 @@
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.code 32
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.balign 4
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.globl threadstart
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threadstart:
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msr CPSR_c, #MODE_SYS
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#ifndef THUMB_NO_INTERWORKING
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mov r0, r5
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mov lr, pc
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bx r4
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bl chThdExit
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#else
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add r0, pc, #1
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bx r0
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.code 16
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mov r0, r5
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bl jmpr4
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bl chThdExit
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jmpr4: bx r4
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.code 32
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#endif
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.weak UndHandler
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.globl UndHandler
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UndHandler:
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.weak SwiHandler
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.globl SwiHandler
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SwiHandler:
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.weak PrefetchHandler
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.globl PrefetchHandler
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PrefetchHandler:
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.weak AbortHandler
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.globl AbortHandler
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AbortHandler:
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.weak FiqHandler
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.globl FiqHandler
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FiqHandler:
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b halt32
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.weak chSysHalt
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#ifdef THUMB_NO_INTERWORKING
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.code 16
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.globl chSysHalt
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chSysHalt:
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mov r0, pc
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bx r0
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.code 32
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#else
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.globl chSysHalt
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chSysHalt:
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#endif
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halt32:
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mrs r0, CPSR
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orr r0, #I_BIT | F_BIT
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msr CPSR_c, r0
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.loop: b .loop
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#ifdef THUMB
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.globl chSysLock
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chSysLock:
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msr CPSR_c, #0x9F
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msr CPSR_c, #MODE_SYS | I_BIT
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bx lr
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.globl chSysUnlock
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chSysUnlock:
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msr CPSR_c, #0x1F
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msr CPSR_c, #MODE_SYS
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bx lr
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#endif
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@ -127,80 +69,3 @@ chSysSwitchI:
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ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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#endif
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#endif /* CH_CURRP_REGISTER_CACHE */
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/*
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* Common exit point for all IRQ routines, it performs the rescheduling if
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* required.
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* System stack frame structure after a context switch in the
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* interrupt handler:
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*
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* High +------------+
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* | LR_USR | -+
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* | R12 | |
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* | R3 | |
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* | R2 | | External context: IRQ handler frame
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* | R1 | |
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* | R0 | |
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* | LR_IRQ | | (user code return address)
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* | SPSR | -+ (user code status)
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* | .... | <- mk_DoRescheduleI() stack frame, optimize it for space
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* | LR | -+ (system code return address)
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* | R11 | |
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* | R10 | |
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* | R9 | |
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* | R8 | | Internal context: mk_SwitchI() frame
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* | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
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* | R6 | |
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* | R5 | |
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* SP-> | R4 | -+
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* Low +------------+
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*/
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#ifdef THUMB_NO_INTERWORKING
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.code 16
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.globl IrqCommon
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IrqCommon:
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bl chSchRescRequiredI
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mov lr, pc
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bx lr
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.code 32
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#else
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.globl IrqCommon
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IrqCommon:
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bl chSchRescRequiredI
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#endif
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cmp r0, #0 // Simply returns if a
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ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not
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subeqs pc, lr, #4 // required.
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// Saves the IRQ mode registers in the system stack.
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ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty.
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msr CPSR_c, #MODE_SYS | I_BIT
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stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack.
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msr CPSR_c, #MODE_IRQ | I_BIT
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mrs r0, SPSR
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mov r1, lr
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msr CPSR_c, #MODE_SYS | I_BIT
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stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
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// Context switch.
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#ifdef THUMB_NO_INTERWORKING
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add r0, pc, #1
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bx r0
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.code 16
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bl chSchDoRescheduleI
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mov lr, pc
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bx lr
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.code 32
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#else
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bl chSchDoRescheduleI
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#endif
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// Re-establish the IRQ conditions again.
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ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
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msr CPSR_c, #MODE_IRQ | I_BIT
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msr SPSR_fsxc, r0
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mov lr, r1
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msr CPSR_c, #MODE_SYS | I_BIT
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ldmfd sp!, {r0-r3, r12, lr}
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msr CPSR_c, #MODE_IRQ | I_BIT
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subs pc, lr, #4
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@ -147,3 +147,24 @@ bssloop:
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bl chSysHalt
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.code 32
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#endif
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.weak UndHandler
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.globl UndHandler
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UndHandler:
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.weak SwiHandler
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.globl SwiHandler
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SwiHandler:
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.weak PrefetchHandler
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.globl PrefetchHandler
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PrefetchHandler:
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.weak AbortHandler
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.globl AbortHandler
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AbortHandler:
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.weak FiqHandler
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.globl FiqHandler
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FiqHandler:
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b _halt32
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@ -60,6 +60,8 @@ typedef struct {
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#define chSysLock()
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#define chSysUnlock()
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#define chSysPuts(msg) {}
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#define chSysIRQEnterI()
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#define chSysIRQExitI()
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#define INT_REQUIRED_STACK 0
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#define StackAlign(n) ((((n) - 1) | 3) + 1)
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@ -60,6 +60,8 @@ typedef struct {
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#define chSysLock()
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#define chSysUnlock()
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#define chSysPuts(msg) {}
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#define chSysIRQEnterI()
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#define chSysIRQExitI()
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#define INT_REQUIRED_STACK 0
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#define StackAlign(n) ((((n) - 1) | 3) + 1)
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@ -55,7 +55,6 @@ static void ServeInterrupt(UART *u, FullDuplexDriver *com) {
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switch (u->UART_IIR & IIR_SRC_MASK) {
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case IIR_SRC_NONE:
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VICVectAddr = 0;
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return;
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case IIR_SRC_ERROR:
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SetError(u->UART_LSR, com);
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@ -98,37 +97,21 @@ static void ServeInterrupt(UART *u, FullDuplexDriver *com) {
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__attribute__((naked, weak))
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void UART0IrqHandler(void) {
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asm(".code 32 \n\t" \
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"stmfd sp!, {r0-r3, r12, lr} \n\t");
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#ifdef THUMB
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t");
|
||||
chSysIRQEnterI();
|
||||
|
||||
ServeInterrupt(U0Base, &COM1);
|
||||
asm("ldr r0, =IrqCommon \n\t" \
|
||||
"bx r0 \n\t");
|
||||
#else
|
||||
ServeInterrupt(U0Base, &COM1);
|
||||
asm("b IrqCommon \n\t");
|
||||
#endif
|
||||
|
||||
chSysIRQExitI();
|
||||
}
|
||||
|
||||
__attribute__((naked, weak))
|
||||
void UART1IrqHandler(void) {
|
||||
|
||||
asm(".code 32 \n\t" \
|
||||
"stmfd sp!, {r0-r3, r12, lr} \n\t");
|
||||
#ifdef THUMB
|
||||
asm("add r0, pc, #1 \n\t" \
|
||||
"bx r0 \n\t" \
|
||||
".code 16 \n\t");
|
||||
chSysIRQEnterI();
|
||||
|
||||
ServeInterrupt(U1Base, &COM2);
|
||||
asm("ldr r0, =IrqCommon \n\t" \
|
||||
"bx r0 \n\t");
|
||||
#else
|
||||
ServeInterrupt(U1Base, &COM2);
|
||||
asm("b IrqCommon \n\t");
|
||||
#endif
|
||||
|
||||
chSysIRQExitI();
|
||||
}
|
||||
|
||||
#ifdef FIFO_PRELOAD
|
||||
|
|
|
|||
13
readme.txt
13
readme.txt
|
|
@ -43,13 +43,20 @@ AVR-AT90CANx-GCC - Port on AVR AT90CAN128, not complete yet.
|
|||
- NEW: Binary Mutexes, the new mechanism provides a complete implementation
|
||||
of the "priority inheritance" algorithm as a tool for work around the
|
||||
priority inversion problem.
|
||||
The Mutexes are not meant to replace the Semaphores that are still the best
|
||||
mechanism for synchronization between interrupt handlers and high level
|
||||
code, something Mutexes cannot do.
|
||||
The Mutexes are not meant to replace the Semaphores that still are the best
|
||||
synchronization mechanism between interrupt handlers and high level
|
||||
code, something that Mutexes cannot do.
|
||||
Soon an article will be added to the wiki describing pro and cons of the
|
||||
various mechanisms and the correct use cases.
|
||||
- RT Semaphores subsystem removed, the Mutexes implements a better solution
|
||||
for the same problem.
|
||||
- Modified the test suite in order to have each test case to have the same
|
||||
alignment enforced on functions. This is done to reduce MAM/Cache alignment
|
||||
effects on the measurement.
|
||||
- IRQ entry/exit code is now encapsulated into two new macros, see chcore.h
|
||||
for details.
|
||||
- Most of the asm code previously in chcore2.s is now inline asm code in
|
||||
chcore.c (ARM port).
|
||||
|
||||
*** 0.4.5 ***
|
||||
- Moved the serial IRQ handlers and VIC vectors initialization inside the
|
||||
|
|
|
|||
12
src/chmtx.c
12
src/chmtx.c
|
|
@ -56,15 +56,15 @@ static void prio_enq(Thread *tp, ThreadsQueue *tqp) {
|
|||
}
|
||||
|
||||
/*
|
||||
* 0 +++BA++------------------2+++--8++++++++++BR0----------------------------
|
||||
* 1 .......++AA++--2+++++++++BA....8..........++++++++BR8++++AR1-------------
|
||||
* 2 .............++AA..............................................----++AR++
|
||||
* 8 .............................++AA........................++++++AR++......
|
||||
* 0 +++BL++------------------2+++--8++++++++++BU0----------------------------
|
||||
* 1 .......++AL++--2+++++++++BL....8..........++++++++BU8++++AU1-------------
|
||||
* 2 .............++AL..............................................----++AU++
|
||||
* 8 .............................++AL........................++++++AU++......
|
||||
*
|
||||
*
|
||||
* 5 ++++++++++++++++++AA+....9++++++++++++++AR5------------------------------
|
||||
* 5 ++++++++++++++++++AL+....9++++++++++++++AU5------------------------------
|
||||
* 7 .....................++--------------------------------------------------
|
||||
* 9 .......................++AA.............+++++++++AR++++++++++++++++++++++
|
||||
* 9 .......................++AL.............+++++++++AU++++++++++++++++++++++
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -100,6 +100,21 @@ typedef struct {
|
|||
*/
|
||||
#define chSysUnlock()
|
||||
|
||||
/**
|
||||
* IRQ handler enter code.
|
||||
* @note Usually IRQ handlers function are also declared naked.
|
||||
* @note On some architectures this macro can be empty.
|
||||
*/
|
||||
#define chSysIRQEnterI()
|
||||
|
||||
/**
|
||||
* IRQ handler exit code.
|
||||
* @note Usually IRQ handlers function are also declared naked.
|
||||
* @note This macro must perform the final reschedulation by using
|
||||
* \p chSchRescRequiredI() and \p chSchDoRescheduleI().
|
||||
*/
|
||||
#define chSysIRQExitI()
|
||||
|
||||
void _IdleThread(void *p);
|
||||
void chSysHalt(void);
|
||||
void chSysSwitchI(Context *oldp, Context *newp);
|
||||
|
|
|
|||
Loading…
Reference in New Issue