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Documentation related change. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1944 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2010-05-20 12:19:18 +00:00
parent 622b7a9359
commit 0c56def75e
1 changed files with 1 additions and 2 deletions
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3
os/hal/platforms/STM32/hal_lld_f105_f107.h
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@ -255,7 +255,7 @@
/* The following values are only used if PLL2 clock is selected as source
for the PLL clock */
#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2)
#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__)
/**
* @brief PLL2 input frequency.
*/
@ -275,7 +275,6 @@
#if (STM32_PLL2CLKOUT < 40000000) || (STM32_PLL2CLKOUT > 74000000)
#error "STM32_PLL2CLKOUT outside acceptable range (40...74MHz)"
#endif
#endif /* STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2 */
/**