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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5155 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-02-12 08:47:41 +00:00
parent 095677dfa3
commit 0c9df1d3fd
2 changed files with 18 additions and 23 deletions
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16
os/hal/platforms/SPC56ELxx/hal_lld.c
View File

@ -128,7 +128,6 @@ void spc_early_init(void) {
#endif /* SPC5_OSC_BYPASS */
/* Setting the various dividers and source selectors.*/
CGM.SC_SS.R = SPC5_CGM_SC_SS;
CGM.SC_DC0.R = SPC5_CGM_SC_DC0;
/*CGM.AC0_DC0_3.R = 0x80808080;
@ -210,16 +209,21 @@ void spc_early_init(void) {
*/
bool_t halSPCSetRunMode(spc5_runmode_t mode) {
/* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
ME.IS.R = 5;
/* Starts a transition process.*/
ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
/* Waits for the mode switch.
TODO: Check for errors during the switch procedure.*/
while (ME.GS.B.S_CURRENT_MODE != mode)
;
/* Waits for the mode switch.*/
while (TRUE) {
uint32_t r = ME.IS.R;
if (r & 1)
return CH_SUCCESS;
if (r & 4)
return CH_FAILED;
}
}
/**

23
os/hal/platforms/SPC56ELxx/hal_lld.h
View File

@ -303,13 +303,6 @@
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
#endif
/**
* @brief System clock source.
*/
#if !defined(SPC5_SYSCLK_SRC) || defined(__DOXYGEN__)
#define SPC5_SYSCLK_SRC SPC5_CGM_SS_FMPLL0
#endif
/**
* @brief System clock divider value.
* @note Zero means disabled clock.
@ -318,6 +311,13 @@
#define SPC5_SYSCLK_DIVIDER_VALUE 1
#endif
/**
* @brief System clock source.
*/
/*#if !defined(SPC5_SYSCLK_SRC) || defined(__DOXYGEN__)
#define SPC5_SYSCLK_SRC SPC5_CGM_SS_FMPLL0
#endif*/
/**
* @brief Active run modes in ME_ME register.
* @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
@ -729,15 +729,6 @@
#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
#endif
/* Check on the system clock selector settings.*/
#if (SPC5_SYSCLK_SRC == SPC5_CGM_SS_IRC) || \
(SPC5_SYSCLK_SRC == SPC5_CGM_SS_XOSC) || \
(SPC5_SYSCLK_SRC == SPC5_CGM_SS_FMPLL0)
#define SPC5_CGM_SC_SS SPC5_SYSCLK_SRC
#else
#error "invalid SPC5_SYSCLK_SRC value specified"
#endif
/* Check on the system divider settings.*/
#if SPC5_SYSCLK_DIVIDER_VALUE == 0
#define SPC5_CGM_SC_DC0 0