git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5155 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -128,7 +128,6 @@ void spc_early_init(void) {
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#endif /* SPC5_OSC_BYPASS */
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/* Setting the various dividers and source selectors.*/
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CGM.SC_SS.R = SPC5_CGM_SC_SS;
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CGM.SC_DC0.R = SPC5_CGM_SC_DC0;
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/*CGM.AC0_DC0_3.R = 0x80808080;
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@ -210,16 +209,21 @@ void spc_early_init(void) {
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*/
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bool_t halSPCSetRunMode(spc5_runmode_t mode) {
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/* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
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ME.IS.R = 5;
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/* Starts a transition process.*/
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ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
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ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
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/* Waits for the mode switch.
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TODO: Check for errors during the switch procedure.*/
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while (ME.GS.B.S_CURRENT_MODE != mode)
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;
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return CH_SUCCESS;
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/* Waits for the mode switch.*/
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while (TRUE) {
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uint32_t r = ME.IS.R;
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if (r & 1)
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return CH_SUCCESS;
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if (r & 4)
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return CH_FAILED;
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}
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}
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/**
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@ -303,13 +303,6 @@
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#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
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#endif
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/**
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* @brief System clock source.
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*/
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#if !defined(SPC5_SYSCLK_SRC) || defined(__DOXYGEN__)
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#define SPC5_SYSCLK_SRC SPC5_CGM_SS_FMPLL0
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#endif
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/**
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* @brief System clock divider value.
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* @note Zero means disabled clock.
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@ -318,6 +311,13 @@
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#define SPC5_SYSCLK_DIVIDER_VALUE 1
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#endif
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/**
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* @brief System clock source.
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*/
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/*#if !defined(SPC5_SYSCLK_SRC) || defined(__DOXYGEN__)
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#define SPC5_SYSCLK_SRC SPC5_CGM_SS_FMPLL0
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#endif*/
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/**
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* @brief Active run modes in ME_ME register.
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* @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
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@ -729,15 +729,6 @@
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#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
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#endif
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/* Check on the system clock selector settings.*/
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#if (SPC5_SYSCLK_SRC == SPC5_CGM_SS_IRC) || \
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(SPC5_SYSCLK_SRC == SPC5_CGM_SS_XOSC) || \
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(SPC5_SYSCLK_SRC == SPC5_CGM_SS_FMPLL0)
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#define SPC5_CGM_SC_SS SPC5_SYSCLK_SRC
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#else
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#error "invalid SPC5_SYSCLK_SRC value specified"
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#endif
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/* Check on the system divider settings.*/
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#if SPC5_SYSCLK_DIVIDER_VALUE == 0
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#define SPC5_CGM_SC_DC0 0
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