git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6028 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
b21e9a01e5
commit
0ca0bc18f9
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@ -206,16 +206,15 @@ void chSysTimerHandlerI(void) {
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* is known.
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* is known.
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*
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*
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* @return The previous system status, the encoding of this
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* @return The previous system status, the encoding of this
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* status word is architecture-dependent but zero is
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* status word is architecture-dependent and opaque.
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* assumed to mean not-locked.
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*
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*
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* @special
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* @special
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*/
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*/
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syssts_t chSysGetAndLockX(void) {
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syssts_t chSysGetAndLockX(void) {
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syssts_t sts = port_get_status();
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syssts_t sts = port_get_irq_status();
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if (!sts) {
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if (port_irq_enabled(sts)) {
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if (port_get_context())
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if (port_is_isr_context())
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chSysLockFromISR();
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chSysLockFromISR();
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else
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else
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chSysLock();
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chSysLock();
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@ -232,8 +231,8 @@ syssts_t chSysGetAndLockX(void) {
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*/
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*/
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void chSysRestoreLockX(syssts_t sts) {
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void chSysRestoreLockX(syssts_t sts) {
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if (!sts) {
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if (port_irq_enabled(sts)) {
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if (port_get_context())
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if (port_is_isr_context())
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chSysUnlockFromISR();
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chSysUnlockFromISR();
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else
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else
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chSysUnlock();
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chSysUnlock();
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@ -28,19 +28,41 @@
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#include "ch.h"
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#include "ch.h"
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/**
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/*===========================================================================*/
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* @brief Halts the system.
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/* Module local definitions. */
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* @note The function is declared as a weak symbol, it is possible
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/*===========================================================================*/
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* to redefine it in your application code.
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*/
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#if !defined(__DOXYGEN__)
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__attribute__((weak))
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#endif
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void port_halt(void) {
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port_disable();
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/*===========================================================================*/
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while (TRUE) {
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/* Module exported variables. */
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}
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module exported functions. */
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/*===========================================================================*/
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/**
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* @brief Start a thread by invoking its work function.
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* @details If the work function returns @p chThdExit() is automatically
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* invoked.
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*/
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void _port_thread_start(void) {
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chSysUnlock();
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asm volatile ("mov r0, r5 \n\t"
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"blx r4 \n\t"
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"bl chThdExit");
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}
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}
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/** @} */
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/** @} */
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@ -30,25 +30,55 @@
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#define _CHCORE_H_
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#define _CHCORE_H_
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/*===========================================================================*/
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/*===========================================================================*/
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/* Port constants (common). */
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/* Module constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Added to make the header stand-alone when included from asm.*/
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/**
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#ifndef FALSE
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* @name Architecture and Compiler
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* @{
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*/
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/**
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* @brief Macro defining a generic ARM architecture.
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*/
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#define CH_ARCHITECTURE_ARM
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/**
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* @brief Name of the compiler supported by this port.
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*/
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#define CH_COMPILER_NAME "GCC " __VERSION__
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/** @} */
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/*
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* Added to make the header stand-alone when included from asm.
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*/
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#if !defined(FALSE)
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#define FALSE 0
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#define FALSE 0
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#endif
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#endif
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#ifndef TRUE
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#if !defined(TRUE)
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#define TRUE (!FALSE)
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#define TRUE (!FALSE)
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#endif
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#endif
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/**
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* @name Cortex-M variants
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* @{
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*/
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#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
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#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
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#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
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#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
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#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
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#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
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#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
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#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
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/** @} */
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/* Inclusion of the Cortex-Mx implementation specific parameters.*/
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/* Inclusion of the Cortex-Mx implementation specific parameters.*/
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#include "cmparams.h"
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#include "cmparams.h"
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Cortex model check, only M0 and M3 supported right now.*/
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/* Cortex model check, only M0 and M3 supported right now.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \
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(CORTEX_MODEL == CORTEX_M4)
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(CORTEX_MODEL == CORTEX_M4)
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@ -58,79 +88,10 @@
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#error "unknown or unsupported Cortex-M model"
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#error "unknown or unsupported Cortex-M model"
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#endif
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#endif
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/**
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* @brief Total priority levels.
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*/
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#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
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/**
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* @brief Minimum priority level.
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* @details This minimum priority level is calculated from the number of
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* priority bits supported by the specific Cortex-Mx implementation.
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*/
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#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
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/**
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* @brief Maximum priority level.
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* @details The maximum allowed priority level is always zero.
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*/
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#define CORTEX_MAXIMUM_PRIORITY 0
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/*===========================================================================*/
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/*===========================================================================*/
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/* Port macros (common). */
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/* Module data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_PRIORITY(n) \
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(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \
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(((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level to priority mask conversion macro.
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*/
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#define CORTEX_PRIORITY_MASK(n) \
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((n) << (8 - CORTEX_PRIORITY_BITS))
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/*===========================================================================*/
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/* Port configurable parameters (common). */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Port derived parameters (common). */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Port exported info (common). */
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/*===========================================================================*/
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/**
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* @brief Macro defining a generic ARM architecture.
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*/
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#define CH_ARCHITECTURE_ARM
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/**
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* @brief Name of the compiler supported by this port.
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*/
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#define CH_COMPILER_NAME "GCC " __VERSION__
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/*===========================================================================*/
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/* Port implementation part (common). */
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/*===========================================================================*/
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/* Includes the sub-architecture-specific part.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
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#include "chcore_v6m.h"
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#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
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#include "chcore_v7m.h"
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#endif
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#if !defined(_FROM_ASM_)
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#if !defined(_FROM_ASM_)
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#include "nvic.h"
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#include "nvic.h"
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@ -138,7 +99,6 @@
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/* The following declarations are there just for Doxygen documentation, the
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/* The following declarations are there just for Doxygen documentation, the
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real declarations are inside the sub-headers.*/
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real declarations are inside the sub-headers.*/
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#if defined(__DOXYGEN__)
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#if defined(__DOXYGEN__)
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/**
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/**
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* @brief Stack and memory alignment enforcement.
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* @brief Stack and memory alignment enforcement.
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* @note In this architecture the stack alignment is enforced to 64 bits,
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* @note In this architecture the stack alignment is enforced to 64 bits,
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@ -161,11 +121,65 @@ struct extctx {};
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* switching.
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* switching.
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*/
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*/
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struct intctx {};
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struct intctx {};
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#endif /* defined(__DOXYGEN__) */
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#endif /* defined(__DOXYGEN__) */
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#endif /* _FROM_ASM_ */
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#endif /* _FROM_ASM_ */
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/*===========================================================================*/
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/* Module macros. */
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/*===========================================================================*/
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/**
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* @brief Total priority levels.
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*/
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#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
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/**
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* @brief Minimum priority level.
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* @details This minimum priority level is calculated from the number of
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* priority bits supported by the specific Cortex-Mx implementation.
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*/
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#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
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/**
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* @brief Maximum priority level.
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* @details The maximum allowed priority level is always zero.
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*/
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#define CORTEX_MAXIMUM_PRIORITY 0
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_PRIORITY(n) \
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(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \
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(((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level to priority mask conversion macro.
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*/
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#define CORTEX_PRIORITY_MASK(n) \
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((n) << (8 - CORTEX_PRIORITY_BITS))
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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/* Includes the sub-architecture-specific part.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
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#include "chcore_v6m.h"
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#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
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#include "chcore_v7m.h"
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#endif
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/*===========================================================================*/
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/* Module inline functions. */
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/*===========================================================================*/
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#endif /* _CHCORE_H_ */
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#endif /* _CHCORE_H_ */
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/** @} */
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/** @} */
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@ -29,7 +29,27 @@
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#include "ch.h"
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#include "ch.h"
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/*===========================================================================*/
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/*===========================================================================*/
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/* Port interrupt handlers. */
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/* Module local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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/**
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@ -84,7 +104,7 @@ void PendSVVector(void) {
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#endif /* CORTEX_ALTERNATE_SWITCH */
|
#endif /* CORTEX_ALTERNATE_SWITCH */
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|
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/*===========================================================================*/
|
/*===========================================================================*/
|
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/* Port exported functions. */
|
/* Module exported functions. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
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/**
|
/**
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@ -183,17 +203,4 @@ void _port_switch(Thread *ntp, Thread *otp) {
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"pop {r4, r5, r6, r7, pc}" : : "r" (r13) : "memory");
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"pop {r4, r5, r6, r7, pc}" : : "r" (r13) : "memory");
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}
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}
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/**
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* @brief Start a thread by invoking its work function.
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* @details If the work function returns @p chThdExit() is automatically
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* invoked.
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*/
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void _port_thread_start(void) {
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chSysUnlock();
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asm volatile ("mov r0, r5 \n\t"
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"blx r4 \n\t"
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"bl chThdExit");
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}
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/** @} */
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/** @} */
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@ -359,7 +359,6 @@ struct context {
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#ifdef __cplusplus
|
#ifdef __cplusplus
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extern "C" {
|
extern "C" {
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#endif
|
#endif
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void port_halt(void);
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|
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void _port_irq_epilogue(regarm_t lr);
|
void _port_irq_epilogue(regarm_t lr);
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void _port_switch_from_isr(void);
|
void _port_switch_from_isr(void);
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void _port_exit_from_isr(void);
|
void _port_exit_from_isr(void);
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|
@ -29,7 +29,27 @@
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#include "ch.h"
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#include "ch.h"
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/*===========================================================================*/
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/*===========================================================================*/
|
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/* Port interrupt handlers. */
|
/* Module local definitions. */
|
||||||
|
/*===========================================================================*/
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|
|
||||||
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/*===========================================================================*/
|
||||||
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/* Module exported variables. */
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||||||
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/*===========================================================================*/
|
||||||
|
|
||||||
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/*===========================================================================*/
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/* Module local types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module local functions. */
|
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
|
||||||
|
|
||||||
#if CH_CFG_TIMEDELTA == 0
|
#if CH_CFG_TIMEDELTA == 0
|
||||||
|
|
@ -104,43 +124,9 @@ void PendSVVector(void) {
|
||||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Port exported functions. */
|
/* Module exported functions. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Port-related initialization code.
|
|
||||||
*/
|
|
||||||
void _port_init(void) {
|
|
||||||
|
|
||||||
/* Initialization of the vector table and priority related settings.*/
|
|
||||||
SCB_VTOR = CORTEX_VTOR_INIT;
|
|
||||||
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT);
|
|
||||||
|
|
||||||
/* Initialization of the system vectors used by the port.*/
|
|
||||||
nvicSetSystemHandlerPriority(HANDLER_SVCALL,
|
|
||||||
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
|
|
||||||
nvicSetSystemHandlerPriority(HANDLER_PENDSV,
|
|
||||||
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
|
|
||||||
#if CH_CFG_TIMEDELTA == 0
|
|
||||||
nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
|
|
||||||
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
|
|
||||||
#else
|
|
||||||
port_timer_init();
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#if !CH_CFG_OPTIMIZE_SPEED
|
|
||||||
void _port_lock(void) {
|
|
||||||
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL;
|
|
||||||
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
|
|
||||||
}
|
|
||||||
|
|
||||||
void _port_unlock(void) {
|
|
||||||
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED;
|
|
||||||
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory");
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Exception exit redirection to _port_switch_from_isr().
|
* @brief Exception exit redirection to _port_switch_from_isr().
|
||||||
*/
|
*/
|
||||||
|
|
@ -250,17 +236,4 @@ void _port_switch(thread_t *ntp, thread_t *otp) {
|
||||||
: : : "memory");
|
: : : "memory");
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Start a thread by invoking its work function.
|
|
||||||
* @details If the work function returns @p chThdExit() is automatically
|
|
||||||
* invoked.
|
|
||||||
*/
|
|
||||||
void _port_thread_start(void) {
|
|
||||||
|
|
||||||
chSysUnlock();
|
|
||||||
asm volatile ("mov r0, r5 \n\t"
|
|
||||||
"blx r4 \n\t"
|
|
||||||
"bl chThdExit");
|
|
||||||
}
|
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
|
||||||
|
|
@ -30,20 +30,56 @@
|
||||||
#define _CHCORE_V7M_H_
|
#define _CHCORE_V7M_H_
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Port constants. */
|
/* Module constants. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Architecture and Compiler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief Macro defining the specific ARM architecture.
|
||||||
|
*/
|
||||||
|
#define CH_ARCHITECTURE_ARM_v7M
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Name of the implemented architecture.
|
||||||
|
*/
|
||||||
|
#define CH_ARCHITECTURE_NAME "ARMv7-M"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Name of the architecture variant.
|
||||||
|
*/
|
||||||
|
#define CH_CORE_VARIANT_NAME "Cortex-M3"
|
||||||
|
|
||||||
|
#elif (CORTEX_MODEL == CORTEX_M4)
|
||||||
|
#define CH_ARCHITECTURE_ARM_v7ME
|
||||||
|
#define CH_ARCHITECTURE_NAME "ARMv7-ME"
|
||||||
|
#if CORTEX_USE_FPU
|
||||||
|
#define CH_CORE_VARIANT_NAME "Cortex-M4F"
|
||||||
|
#else
|
||||||
|
#define CH_CORE_VARIANT_NAME "Cortex-M4"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Port-specific information string.
|
||||||
|
*/
|
||||||
|
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
||||||
|
#define CH_PORT_INFO "Advanced kernel mode"
|
||||||
|
#else
|
||||||
|
#define CH_PORT_INFO "Compact kernel mode"
|
||||||
|
#endif
|
||||||
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Disabled value for BASEPRI register.
|
* @brief Disabled value for BASEPRI register.
|
||||||
*/
|
*/
|
||||||
#define CORTEX_BASEPRI_DISABLED 0
|
#define CORTEX_BASEPRI_DISABLED 0
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Port macros. */
|
/* Module pre-compile time settings. */
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Port configurable parameters. */
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -142,7 +178,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Port derived parameters. */
|
/* Derived constants and error checks. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
||||||
|
|
@ -172,46 +208,7 @@
|
||||||
#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
|
#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Port exported info. */
|
/* Module data structures and types. */
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
|
|
||||||
/**
|
|
||||||
* @brief Macro defining the specific ARM architecture.
|
|
||||||
*/
|
|
||||||
#define CH_ARCHITECTURE_ARM_v7M
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Name of the implemented architecture.
|
|
||||||
*/
|
|
||||||
#define CH_ARCHITECTURE_NAME "ARMv7-M"
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Name of the architecture variant.
|
|
||||||
*/
|
|
||||||
#define CH_CORE_VARIANT_NAME "Cortex-M3"
|
|
||||||
|
|
||||||
#elif (CORTEX_MODEL == CORTEX_M4)
|
|
||||||
#define CH_ARCHITECTURE_ARM_v7ME
|
|
||||||
#define CH_ARCHITECTURE_NAME "ARMv7-ME"
|
|
||||||
#if CORTEX_USE_FPU
|
|
||||||
#define CH_CORE_VARIANT_NAME "Cortex-M4F"
|
|
||||||
#else
|
|
||||||
#define CH_CORE_VARIANT_NAME "Cortex-M4"
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Port-specific information string.
|
|
||||||
*/
|
|
||||||
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
|
||||||
#define CH_PORT_INFO "Advanced kernel mode"
|
|
||||||
#else
|
|
||||||
#define CH_PORT_INFO "Compact kernel mode"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Port implementation part. */
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
#if !defined(_FROM_ASM_)
|
#if !defined(_FROM_ASM_)
|
||||||
|
|
@ -299,6 +296,10 @@ struct context {
|
||||||
struct intctx *r13;
|
struct intctx *r13;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module macros. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Platform dependent part of the @p chThdCreateI() API.
|
* @brief Platform dependent part of the @p chThdCreateI() API.
|
||||||
* @details This code usually setup the context switching frame represented
|
* @details This code usually setup the context switching frame represented
|
||||||
|
|
@ -361,124 +362,6 @@ struct context {
|
||||||
*/
|
*/
|
||||||
#define PORT_FAST_IRQ_HANDLER(id) void id(void)
|
#define PORT_FAST_IRQ_HANDLER(id) void id(void)
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Port-related initialization code.
|
|
||||||
*/
|
|
||||||
#define port_init() _port_init()
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Kernel-lock action.
|
|
||||||
* @details Usually this function just disables interrupts but may perform
|
|
||||||
* more actions.
|
|
||||||
* @note In this port this it raises the base priority to kernel level.
|
|
||||||
*/
|
|
||||||
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
|
||||||
#if CH_CFG_OPTIMIZE_SPEED || defined(__DOXYGEN__)
|
|
||||||
#define port_lock() { \
|
|
||||||
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
|
|
||||||
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
|
|
||||||
}
|
|
||||||
#else /* !CH_CFG_OPTIMIZE_SPEED */
|
|
||||||
#define port_lock() { \
|
|
||||||
asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \
|
|
||||||
}
|
|
||||||
#endif /* !CH_CFG_OPTIMIZE_SPEED */
|
|
||||||
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
|
||||||
#define port_lock() asm volatile ("cpsid i" : : : "memory")
|
|
||||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Kernel-unlock action.
|
|
||||||
* @details Usually this function just enables interrupts but may perform
|
|
||||||
* more actions.
|
|
||||||
* @note In this port this it lowers the base priority to user level.
|
|
||||||
*/
|
|
||||||
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
|
||||||
#if CH_CFG_OPTIMIZE_SPEED || defined(__DOXYGEN__)
|
|
||||||
#define port_unlock() { \
|
|
||||||
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
|
|
||||||
asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
|
|
||||||
}
|
|
||||||
#else /* !CH_CFG_OPTIMIZE_SPEED */
|
|
||||||
#define port_unlock() { \
|
|
||||||
asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \
|
|
||||||
}
|
|
||||||
#endif /* !CH_CFG_OPTIMIZE_SPEED */
|
|
||||||
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
|
||||||
#define port_unlock() asm volatile ("cpsie i" : : : "memory")
|
|
||||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Kernel-lock action from an interrupt handler.
|
|
||||||
* @details This function is invoked before invoking I-class APIs from
|
|
||||||
* interrupt handlers. The implementation is architecture dependent,
|
|
||||||
* in its simplest form it is void.
|
|
||||||
* @note Same as @p port_lock() in this port.
|
|
||||||
*/
|
|
||||||
#define port_lock_from_isr() port_lock()
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Kernel-unlock action from an interrupt handler.
|
|
||||||
* @details This function is invoked after invoking I-class APIs from interrupt
|
|
||||||
* handlers. The implementation is architecture dependent, in its
|
|
||||||
* simplest form it is void.
|
|
||||||
* @note Same as @p port_unlock() in this port.
|
|
||||||
*/
|
|
||||||
#define port_unlock_from_isr() port_unlock()
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables all the interrupt sources.
|
|
||||||
* @note Of course non-maskable interrupt sources are not included.
|
|
||||||
* @note In this port it disables all the interrupt sources by raising
|
|
||||||
* the priority mask to level 0.
|
|
||||||
*/
|
|
||||||
#define port_disable() asm volatile ("cpsid i" : : : "memory")
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables the interrupt sources below kernel-level priority.
|
|
||||||
* @note Interrupt sources above kernel level remains enabled.
|
|
||||||
* @note In this port it raises/lowers the base priority to kernel level.
|
|
||||||
*/
|
|
||||||
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
|
||||||
#define port_suspend() { \
|
|
||||||
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
|
|
||||||
asm volatile ("msr BASEPRI, %0 \n\t" \
|
|
||||||
"cpsie i" : : "r" (tmp) : "memory"); \
|
|
||||||
}
|
|
||||||
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
|
||||||
#define port_suspend() asm volatile ("cpsid i" : : : "memory")
|
|
||||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables all the interrupt sources.
|
|
||||||
* @note In this port it lowers the base priority to user level.
|
|
||||||
*/
|
|
||||||
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
|
||||||
#define port_enable() { \
|
|
||||||
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
|
|
||||||
asm volatile ("msr BASEPRI, %0 \n\t" \
|
|
||||||
"cpsie i" : : "r" (tmp) : "memory"); \
|
|
||||||
}
|
|
||||||
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
|
||||||
#define port_enable() asm volatile ("cpsie i" : : : "memory")
|
|
||||||
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enters an architecture-dependent IRQ-waiting mode.
|
|
||||||
* @details The function is meant to return when an interrupt becomes pending.
|
|
||||||
* The simplest implementation is an empty function or macro but this
|
|
||||||
* would not take advantage of architecture-specific power saving
|
|
||||||
* modes.
|
|
||||||
* @note Implemented as an inlined @p WFI instruction.
|
|
||||||
*/
|
|
||||||
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
|
|
||||||
#define port_wait_for_interrupt() { \
|
|
||||||
asm volatile ("wfi" : : : "memory"); \
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
#define port_wait_for_interrupt()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Performs a context switch between two threads.
|
* @brief Performs a context switch between two threads.
|
||||||
* @details This is the most critical code in any port, this function
|
* @details This is the most critical code in any port, this function
|
||||||
|
|
@ -500,20 +383,18 @@ struct context {
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* External declarations. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
void port_halt(void);
|
|
||||||
void _port_init(void);
|
|
||||||
void _port_irq_epilogue(void);
|
void _port_irq_epilogue(void);
|
||||||
void _port_switch_from_isr(void);
|
void _port_switch_from_isr(void);
|
||||||
void _port_exit_from_isr(void);
|
void _port_exit_from_isr(void);
|
||||||
void _port_switch(thread_t *ntp, thread_t *otp);
|
void _port_switch(thread_t *ntp, thread_t *otp);
|
||||||
void _port_thread_start(void);
|
void _port_thread_start(void);
|
||||||
#if !CH_CFG_OPTIMIZE_SPEED
|
|
||||||
void _port_lock(void);
|
|
||||||
void _port_unlock(void);
|
|
||||||
#endif
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -522,6 +403,189 @@ extern "C" {
|
||||||
#include "chtimer.h"
|
#include "chtimer.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Module inline functions. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Port-related initialization code.
|
||||||
|
*/
|
||||||
|
static inline void port_init(void) {
|
||||||
|
|
||||||
|
/* Initialization of the vector table and priority related settings.*/
|
||||||
|
SCB_VTOR = CORTEX_VTOR_INIT;
|
||||||
|
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT);
|
||||||
|
|
||||||
|
/* Initialization of the system vectors used by the port.*/
|
||||||
|
nvicSetSystemHandlerPriority(HANDLER_SVCALL,
|
||||||
|
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
|
||||||
|
nvicSetSystemHandlerPriority(HANDLER_PENDSV,
|
||||||
|
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
|
||||||
|
#if CH_CFG_TIMEDELTA == 0
|
||||||
|
nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
|
||||||
|
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
|
||||||
|
#else
|
||||||
|
port_timer_init();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns a word encoding the current interrupts status.
|
||||||
|
*
|
||||||
|
* @return The interrupts status.
|
||||||
|
*/
|
||||||
|
static inline syssts_t port_get_irq_status(void) {
|
||||||
|
register uint32_t sts;
|
||||||
|
|
||||||
|
#if !CORTEX_SIMPLIFIED_PRIORITY
|
||||||
|
asm volatile ("mrs %0, BASEPRI" : "=r" (sts) : : "memory");
|
||||||
|
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||||
|
asm volatile ("mrs %0, PRIMASK" : "=r" (sts) : : "memory");
|
||||||
|
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||||
|
return sts;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks the interrupt status.
|
||||||
|
*
|
||||||
|
* @param[in] sts the interrupt status word
|
||||||
|
*
|
||||||
|
* @return The interrupt status.
|
||||||
|
* @retvel false the word specified a disabled interrupts status.
|
||||||
|
* @retvel true the word specified an enabled interrupts status.
|
||||||
|
*/
|
||||||
|
static inline bool port_irq_enabled(syssts_t sts) {
|
||||||
|
|
||||||
|
return sts >= CORTEX_BASEPRI_KERNEL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Determines the current execution context.
|
||||||
|
*
|
||||||
|
* @return The execution context.
|
||||||
|
* @retval false not running in ISR mode.
|
||||||
|
* @retval true running in ISR mode.
|
||||||
|
*/
|
||||||
|
static inline bool port_is_isr_context(void) {
|
||||||
|
uint32_t ipsr;
|
||||||
|
|
||||||
|
asm volatile ("MRS %0, ipsr" : "=r" (ipsr));
|
||||||
|
return (bool)((ipsr & 0x1FF) != 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Kernel-lock action.
|
||||||
|
* @details Usually this function just disables interrupts but may perform
|
||||||
|
* more actions.
|
||||||
|
* @note In this port this it raises the base priority to kernel level.
|
||||||
|
*/
|
||||||
|
static inline void port_lock(void) {
|
||||||
|
|
||||||
|
#if !CORTEX_SIMPLIFIED_PRIORITY
|
||||||
|
register uint32_t basepri = CORTEX_BASEPRI_KERNEL;
|
||||||
|
asm volatile ("msr BASEPRI, %0" : : "r" (basepri) : "memory");
|
||||||
|
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||||
|
asm volatile ("cpsid i" : : : "memory");
|
||||||
|
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Kernel-unlock action.
|
||||||
|
* @details Usually this function just enables interrupts but may perform
|
||||||
|
* more actions.
|
||||||
|
* @note In this port this it lowers the base priority to user level.
|
||||||
|
*/
|
||||||
|
static inline void port_unlock(void) {
|
||||||
|
|
||||||
|
#if !CORTEX_SIMPLIFIED_PRIORITY
|
||||||
|
register uint32_t basepri = CORTEX_BASEPRI_DISABLED;
|
||||||
|
asm volatile ("msr BASEPRI, %0" : : "r" (basepri) : "memory");
|
||||||
|
#else /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||||
|
asm volatile ("cpsie i" : : : "memory");
|
||||||
|
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Kernel-lock action from an interrupt handler.
|
||||||
|
* @details This function is invoked before invoking I-class APIs from
|
||||||
|
* interrupt handlers. The implementation is architecture dependent,
|
||||||
|
* in its simplest form it is void.
|
||||||
|
* @note Same as @p port_lock() in this port.
|
||||||
|
*/
|
||||||
|
static inline void port_lock_from_isr(void) {
|
||||||
|
|
||||||
|
port_lock();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Kernel-unlock action from an interrupt handler.
|
||||||
|
* @details This function is invoked after invoking I-class APIs from interrupt
|
||||||
|
* handlers. The implementation is architecture dependent, in its
|
||||||
|
* simplest form it is void.
|
||||||
|
* @note Same as @p port_unlock() in this port.
|
||||||
|
*/
|
||||||
|
static inline void port_unlock_from_isr(void) {
|
||||||
|
|
||||||
|
port_unlock();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables all the interrupt sources.
|
||||||
|
* @note Of course non-maskable interrupt sources are not included.
|
||||||
|
* @note In this port it disables all the interrupt sources by raising
|
||||||
|
* the priority mask to level 0.
|
||||||
|
*/
|
||||||
|
static inline void port_disable(void) {
|
||||||
|
|
||||||
|
asm volatile ("cpsid i" : : : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables the interrupt sources below kernel-level priority.
|
||||||
|
* @note Interrupt sources above kernel level remains enabled.
|
||||||
|
* @note In this port it raises/lowers the base priority to kernel level.
|
||||||
|
*/
|
||||||
|
static inline void port_suspend(void) {
|
||||||
|
|
||||||
|
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
||||||
|
register uint32_t basepri = CORTEX_BASEPRI_KERNEL;
|
||||||
|
asm volatile ("msr BASEPRI, %0 \n\t"
|
||||||
|
"cpsie i" : : "r" (basepri) : "memory");
|
||||||
|
#else
|
||||||
|
asm volatile ("cpsid i" : : : "memory");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables all the interrupt sources.
|
||||||
|
* @note In this port it lowers the base priority to user level.
|
||||||
|
*/
|
||||||
|
static inline void port_enable(void) {
|
||||||
|
|
||||||
|
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
|
||||||
|
register uint32_t basepri = CORTEX_BASEPRI_DISABLED;
|
||||||
|
asm volatile ("msr BASEPRI, %0 \n\t"
|
||||||
|
"cpsie i" : : "r" (basepri) : "memory");
|
||||||
|
#else
|
||||||
|
asm volatile ("cpsie i" : : : "memory");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enters an architecture-dependent IRQ-waiting mode.
|
||||||
|
* @details The function is meant to return when an interrupt becomes pending.
|
||||||
|
* The simplest implementation is an empty function or macro but this
|
||||||
|
* would not take advantage of architecture-specific power saving
|
||||||
|
* modes.
|
||||||
|
* @note Implemented as an inlined @p WFI instruction.
|
||||||
|
*/
|
||||||
|
static inline void port_wait_for_interrupt(void) {
|
||||||
|
|
||||||
|
#if CORTEX_ENABLE_WFI_IDLE
|
||||||
|
asm volatile ("wfi" : : : "memory");
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
#endif /* _FROM_ASM_ */
|
#endif /* _FROM_ASM_ */
|
||||||
|
|
||||||
#endif /* _CHCORE_V7M_H_ */
|
#endif /* _CHCORE_V7M_H_ */
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue