diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h index 3f2fb0519..6f3e269e6 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h @@ -469,7 +469,6 @@ #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) /** @} */ - /** * @name CAN peripherals specific RCC operations * @{ diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index 5393e508a..0e076a22d 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -120,9 +120,6 @@ void hal_lld_init(void) { rccResetAPB1(~RCC_APB1RSTR_PWRRST); rccResetAPB2(~0); - /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); - /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); @@ -162,8 +159,15 @@ void hal_lld_init(void) { void stm32_clock_init(void) { #if !STM32_NO_INIT - /* PWR clock enable.*/ + /* PWR clock enabled.*/ +#if defined(HAL_USE_RTC) && \ + (defined(STM32F765xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined (STM32F779xx)) + RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCEN; +#else RCC->APB1ENR = RCC_APB1ENR_PWREN; +#endif /* PWR initialization.*/ PWR->CR1 = STM32_VOS; diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index 76aa1ee60..d55e4afa5 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -469,7 +469,6 @@ #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) /** @} */ - /** * @name CAN peripherals specific RCC operations * @{ diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h index 83dfdffd1..8905c6b59 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -413,7 +413,6 @@ #define rccResetPWRInterface() rccResetAPB1R1(RCC_APB1RSTR1_PWRRST) /** @} */ - /** * @name CAN peripherals specific RCC operations * @{