diff --git a/testhal/STM32/multi/ADC/.cproject b/testhal/STM32/multi/ADC/.cproject index 07eba767f..dc83a5373 100644 --- a/testhal/STM32/multi/ADC/.cproject +++ b/testhal/STM32/multi/ADC/.cproject @@ -104,7 +104,7 @@ - + @@ -116,11 +116,11 @@ - + - + @@ -137,6 +137,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -144,13 +178,23 @@ + + + + + + + + + + @@ -163,5 +207,8 @@ + + + diff --git a/testhal/STM32/multi/ADC/Makefile b/testhal/STM32/multi/ADC/Makefile index a5368aa98..f41f08292 100644 --- a/testhal/STM32/multi/ADC/Makefile +++ b/testhal/STM32/multi/ADC/Makefile @@ -4,8 +4,12 @@ all: @echo - @echo === Building for STM32H743-Nucleo144 =============================== - @make --no-print-directory -f ./make/stm32h743_nucleo144.make all + @echo === Building for STM32H743ZI-Nucleo144 =============================== + @make --no-print-directory -f ./make/stm32h743zi_nucleo144.make all + @echo ==================================================================== + @echo + @echo === Building for STM32L053R8-Nucleo64 ============================== + +@make --no-print-directory -f ./make/stm32l053r8_nucleo64.make all @echo ==================================================================== @echo @echo === Building for STM32L476-Discovery =============================== @@ -21,6 +25,8 @@ clean: @echo -@make --no-print-directory -f ./make/stm32h743_nucleo144.make clean @echo + +@make --no-print-directory -f ./make/stm32l053r8_nucleo64.make clean + @echo +@make --no-print-directory -f ./make/stm32l476_discovery.make clean @echo +@make --no-print-directory -f ./make/stm32l4r5zi_nucleo144.make clean diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h deleted file mode 100644 index 0530714a9..000000000 --- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h +++ /dev/null @@ -1,481 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * STM32H7xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32H7xx_MCUCONF -#define STM32H742_MCUCONF -#define STM32H743_MCUCONF -#define STM32H753_MCUCONF -#define STM32H745_MCUCONF -#define STM32H755_MCUCONF -#define STM32H747_MCUCONF -#define STM32H757_MCUCONF - -/* - * General settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_TARGET_CORE 1 - -/* - * Memory attributes settings. - */ -#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 -#define STM32_NOCACHE_SRAM1_SRAM2 FALSE -#define STM32_NOCACHE_SRAM3 TRUE - -/* - * PWR system settings. - * Reading STM32 Reference Manual is required, settings in PWR_CR3 are - * very critical. - * Register constants are taken from the ST header. - */ -#define STM32_VOS STM32_VOS_SCALE1 -#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) -#define STM32_PWR_CR2 (PWR_CR2_BREN) -#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN) -#define STM32_PWR_CPUCR 0 - -/* - * Clock tree static settings. - * Reading STM32 Reference Manual is required. - */ -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_CSI_ENABLED TRUE -#define STM32_HSI48_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED TRUE -#define STM32_HSIDIV STM32_HSIDIV_DIV1 - -/* - * PLLs static settings. - * Reading STM32 Reference Manual is required. - */ -#define STM32_PLLSRC STM32_PLLSRC_HSE_CK -#define STM32_PLLCFGR_MASK ~0 -#define STM32_PLL1_ENABLED TRUE -#define STM32_PLL1_P_ENABLED TRUE -#define STM32_PLL1_Q_ENABLED TRUE -#define STM32_PLL1_R_ENABLED TRUE -#define STM32_PLL1_DIVM_VALUE 4 -#define STM32_PLL1_DIVN_VALUE 400 -#define STM32_PLL1_FRACN_VALUE 0 -#define STM32_PLL1_DIVP_VALUE 2 -#define STM32_PLL1_DIVQ_VALUE 8 -#define STM32_PLL1_DIVR_VALUE 8 -#define STM32_PLL2_ENABLED TRUE -#define STM32_PLL2_P_ENABLED TRUE -#define STM32_PLL2_Q_ENABLED TRUE -#define STM32_PLL2_R_ENABLED TRUE -#define STM32_PLL2_DIVM_VALUE 4 -#define STM32_PLL2_DIVN_VALUE 400 -#define STM32_PLL2_FRACN_VALUE 0 -#define STM32_PLL2_DIVP_VALUE 40 -#define STM32_PLL2_DIVQ_VALUE 8 -#define STM32_PLL2_DIVR_VALUE 8 -#define STM32_PLL3_ENABLED TRUE -#define STM32_PLL3_P_ENABLED TRUE -#define STM32_PLL3_Q_ENABLED TRUE -#define STM32_PLL3_R_ENABLED TRUE -#define STM32_PLL3_DIVM_VALUE 4 -#define STM32_PLL3_DIVN_VALUE 400 -#define STM32_PLL3_FRACN_VALUE 0 -#define STM32_PLL3_DIVP_VALUE 8 -#define STM32_PLL3_DIVQ_VALUE 8 -#define STM32_PLL3_DIVR_VALUE 8 - -/* - * Core clocks dynamic settings (can be changed at runtime). - * Reading STM32 Reference Manual is required. - */ -#define STM32_SW STM32_SW_PLL1_P_CK -#define STM32_RTCSEL STM32_RTCSEL_LSE_CK -#define STM32_D1CPRE STM32_D1CPRE_DIV1 -#define STM32_D1HPRE STM32_D1HPRE_DIV2 -#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2 -#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2 -#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2 -#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2 - -/* - * Peripherals clocks static settings. - * Reading STM32 Reference Manual is required. - */ -#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK -#define STM32_MCO1PRE_VALUE 4 -#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK -#define STM32_MCO2PRE_VALUE 4 -#define STM32_TIMPRE_ENABLE TRUE -#define STM32_HRTIMSEL 0 -#define STM32_STOPKERWUCK 0 -#define STM32_STOPWUCK 0 -#define STM32_RTCPRE_VALUE 8 -#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK -#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK -#define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK -#define STM32_SWPSEL STM32_SWPSEL_PCLK1 -#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK -#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 -#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK -#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2 -#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK -#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK -#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK -#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 -#define STM32_CECSEL STM32_CECSEL_LSE_CK -#define STM32_USBSEL STM32_USBSEL_PLL1_Q_CK -#define STM32_I2C123SEL STM32_I2C123SEL_PCLK1 -#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK -#define STM32_USART16SEL STM32_USART16SEL_PCLK2 -#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1 -#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4 -#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK -#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK -#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK -#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4 -#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4 -#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4 -#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4 - -/* - * IRQ system settings. - */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_21_PRIORITY 6 - -#define STM32_IRQ_MDMA_PRIORITY 9 - -#define STM32_IRQ_QUADSPI1_PRIORITY 10 - -#define STM32_IRQ_SDMMC1_PRIORITY 9 -#define STM32_IRQ_SDMMC2_PRIORITY 9 - -#define STM32_IRQ_TIM1_UP_PRIORITY 7 -#define STM32_IRQ_TIM1_CC_PRIORITY 7 -#define STM32_IRQ_TIM2_PRIORITY 7 -#define STM32_IRQ_TIM3_PRIORITY 7 -#define STM32_IRQ_TIM4_PRIORITY 7 -#define STM32_IRQ_TIM5_PRIORITY 7 -#define STM32_IRQ_TIM6_PRIORITY 7 -#define STM32_IRQ_TIM7_PRIORITY 7 -#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 -#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 -#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 -#define STM32_IRQ_TIM8_CC_PRIORITY 7 -#define STM32_IRQ_TIM15_PRIORITY 7 -#define STM32_IRQ_TIM16_PRIORITY 7 -#define STM32_IRQ_TIM17_PRIORITY 7 - -#define STM32_IRQ_USART1_PRIORITY 12 -#define STM32_IRQ_USART2_PRIORITY 12 -#define STM32_IRQ_USART3_PRIORITY 12 -#define STM32_IRQ_UART4_PRIORITY 12 -#define STM32_IRQ_UART5_PRIORITY 12 -#define STM32_IRQ_USART6_PRIORITY 12 -#define STM32_IRQ_UART7_PRIORITY 12 -#define STM32_IRQ_UART8_PRIORITY 12 - -/* - * ADC driver system settings. - */ -#define STM32_ADC_DUAL_MODE FALSE -#define STM32_ADC_COMPACT_SAMPLES FALSE -#define STM32_ADC_USE_ADC12 TRUE -#define STM32_ADC_USE_ADC3 TRUE -#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_ADC_ADC12_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_ADC12_IRQ_PRIORITY 5 -#define STM32_ADC_ADC3_IRQ_PRIORITY 5 -#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 -#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_FDCAN1 FALSE -#define STM32_CAN_USE_FDCAN2 FALSE - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 TRUE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM13 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_USE_TIM15 FALSE -#define STM32_GPT_USE_TIM16 FALSE -#define STM32_GPT_USE_TIM17 FALSE - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_USE_I2C4 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C4_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_I2C4_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM12 FALSE -#define STM32_ICU_USE_TIM13 FALSE -#define STM32_ICU_USE_TIM14 FALSE -#define STM32_ICU_USE_TIM15 FALSE -#define STM32_ICU_USE_TIM16 FALSE -#define STM32_ICU_USE_TIM17 FALSE - -/* - * MAC driver system settings. - */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM12 FALSE -#define STM32_PWM_USE_TIM13 FALSE -#define STM32_PWM_USE_TIM14 FALSE -#define STM32_PWM_USE_TIM15 FALSE -#define STM32_PWM_USE_TIM16 FALSE -#define STM32_PWM_USE_TIM17 FALSE - -/* - * RTC driver system settings. - */ -#define STM32_RTC_PRESA_VALUE 32 -#define STM32_RTC_PRESS_VALUE 1024 -#define STM32_RTC_CR_INIT 0 -#define STM32_RTC_TAMPCR_INIT 0 - -/* - * SDC driver system settings. - */ -#define STM32_SDC_USE_SDMMC1 FALSE -#define STM32_SDC_USE_SDMMC2 FALSE -#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 -#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 -#define STM32_SDC_SDMMC_CLOCK_DELAY 10 -#define STM32_SDC_SDMMC_PWRSAV TRUE - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USE_USART3 TRUE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USE_UART7 FALSE -#define STM32_SERIAL_USE_UART8 FALSE - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_USE_SPI4 FALSE -#define STM32_SPI_USE_SPI5 FALSE -#define STM32_SPI_USE_SPI6 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#define STM32_SPI_SPI5_DMA_PRIORITY 1 -#define STM32_SPI_SPI6_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#define STM32_SPI_SPI5_IRQ_PRIORITY 10 -#define STM32_SPI_SPI6_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 - -/* - * TRNG driver system settings. - */ -#define STM32_TRNG_USE_RNG1 FALSE - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USE_UART7 FALSE -#define STM32_UART_USE_UART8 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_UART7_DMA_PRIORITY 0 -#define STM32_UART_UART8_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_OTG1 FALSE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_HOST_WAKEUP_DURATION 2 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -/* - * WSPI driver system settings. - */ -#define STM32_WSPI_USE_QUADSPI1 FALSE -#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 -#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY -#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1 -#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure") - -#endif /* MCUCONF_H */ diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/chconf.h b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/chconf.h similarity index 96% rename from testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/chconf.h rename to testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/chconf.h index dd19aae80..9b60c2e43 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/chconf.h +++ b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/chconf.h @@ -43,7 +43,7 @@ * @note Allowed values are 16 or 32 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) -#define CH_CFG_ST_RESOLUTION 32 +#define CH_CFG_ST_RESOLUTION 16 #endif /** @@ -52,7 +52,7 @@ * setting also defines the system tick time unit. */ #if !defined(CH_CFG_ST_FREQUENCY) -#define CH_CFG_ST_FREQUENCY 10000 +#define CH_CFG_ST_FREQUENCY 1000 #endif /** @@ -157,7 +157,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE +#define CH_CFG_USE_TM FALSE #endif /** diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/halconf.h b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/halconf.h similarity index 96% rename from testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/halconf.h rename to testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/halconf.h index ff0feb1e4..c7862f60d 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/halconf.h +++ b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/halconf.h @@ -79,7 +79,7 @@ * @brief Enables the GPT subsystem. */ #if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT TRUE +#define HAL_USE_GPT FALSE #endif /** diff --git a/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/mcuconf.h new file mode 100644 index 000000000..2c74f3b1e --- /dev/null +++ b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/mcuconf.h @@ -0,0 +1,207 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32L0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32L0xx_MCUCONF +#define STM32L052_MCUCONF +#define STM32L053_MCUCONF +#define STM32L062_MCUCONF +#define STM32L063_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_VOS STM32_VOS_1P8 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI16_ENABLED TRUE +#define STM32_HSI16_DIVIDER_ENABLED FALSE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_ADC_CLOCK_ENABLED TRUE +#define STM32_USB_CLOCK_ENABLED TRUE +#define STM32_MSIRANGE STM32_MSIRANGE_2M +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI16 +#define STM32_PLLMUL_VALUE 4 +#define STM32_PLLDIV_VALUE 2 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 + +/* + * Peripherals clock sources. + */ +#define STM32_USART1SEL STM32_USART1SEL_APB +#define STM32_USART2SEL STM32_USART2SEL_APB +#define STM32_LPUART1SEL STM32_LPUART1SEL_APB +#define STM32_I2C1SEL STM32_I2C1SEL_APB +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_APB +#define STM32_HSI48SEL STM32_HSI48SEL_HSI48 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE STM32_RTCPRE_DIV2 + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_1_PRIORITY 3 +#define STM32_IRQ_EXTI2_3_PRIORITY 3 +#define STM32_IRQ_EXTI4_15_PRIORITY 3 +#define STM32_IRQ_EXTI16_PRIORITY 3 +#define STM32_IRQ_EXTI17_20_PRIORITY 3 +#define STM32_IRQ_EXTI21_22_PRIORITY 3 + +#define STM32_IRQ_USART1_PRIORITY 3 +#define STM32_IRQ_USART2_PRIORITY 3 +#define STM32_IRQ_LPUART1_PRIORITY 3 + +#define STM32_IRQ_TIM2_PRIORITY 1 +#define STM32_IRQ_TIM6_PRIORITY 1 +#define STM32_IRQ_TIM21_PRIORITY 1 +#define STM32_IRQ_TIM22_PRIORITY 1 + +/* + * ADC driver system settings. + * Note, IRQ is shared with EXT channels 21 and 22. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_PRESCALER_VALUE 1 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 3 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM21 FALSE +#define STM32_GPT_USE_TIM22 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_IRQ_PRIORITY 3 +#define STM32_I2C_I2C2_IRQ_PRIORITY 3 +#define STM32_I2C_USE_DMA TRUE +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM21 FALSE +#define STM32_ICU_USE_TIM22 FALSE + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM21 FALSE +#define STM32_PWM_USE_TIM22 FALSE + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_LPUART1 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 1 +#define STM32_SPI_SPI2_IRQ_PRIORITY 1 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 2 +#define STM32_ST_USE_TIMER 21 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/portab.c similarity index 64% rename from testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c rename to testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/portab.c index 2e16ae935..589c4ed60 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.c +++ b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/portab.c @@ -45,8 +45,7 @@ const GPTConfig portab_gptcfg1 = { }; const ADCConfig portab_adccfg1 = { - .difsel = 0U, - .calibration = 0U + .dummy = 0U }; void adccallback(ADCDriver *adcp); @@ -58,69 +57,40 @@ void adcerrorcallback(ADCDriver *adcp, adcerror_t err); /* * ADC conversion group 1. - * Mode: One shot, 2 channels, SW triggered. - * Channels: IN0, IN5. + * Mode: Linear buffer, 1 channel, SW triggered. + * Channels: IN10. */ -const ADCConversionGroup portab_adcgrpcfg1 = { - .circular = false, +static const ADCConversionGroup adcgrpcfg1 = { + .circular = true, .num_channels = ADC_GRP1_NUM_CHANNELS, .end_cb = NULL, .error_cb = adcerrorcallback, - .cfgr = 0U, - .cfgr2 = 0U, - .ccr = 0U, - .pcsel = ADC_SELMASK_IN0 | ADC_SELMASK_IN5, - .ltr1 = 0x00000000U, - .htr1 = 0x03FFFFFFU, - .ltr2 = 0x00000000U, - .htr2 = 0x03FFFFFFU, - .ltr3 = 0x00000000U, - .htr3 = 0x03FFFFFFU, - .smpr = { - ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_384P5) | - ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_384P5), - 0U - }, - .sqr = { - ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN5), - 0U, - 0U, - 0U - } + .cfgr1 = ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGR1 */ + .cfgr2 = 0, /* CFGR2 */ + .tr = ADC_TR(0, 0), /* TR */ + .smpr = ADC_SMPR_SMP_1P5, /* SMPR */ + .chselr = ADC_CHSELR_CHSEL10 /* CHSELR */ }; /* - * ADC conversion group 2. - * Mode: Continuous, 2 channels, HW triggered by GPT4-TRGO. - * Channels: IN0, IN5. + * ADC conversion group2. + * Mode: Continuous, 4 channels, HW triggered by GPT6-TRGO. + * Channels: IN10, IN11, VRef, Sensor. */ -const ADCConversionGroup portab_adcgrpcfg2 = { +static const ADCConversionGroup adcgrpcfg2 = { .circular = true, .num_channels = ADC_GRP2_NUM_CHANNELS, .end_cb = adccallback, .error_cb = adcerrorcallback, - .cfgr = ADC_CFGR_EXTEN_RISING | - ADC_CFGR_EXTSEL_SRC(12), /* TIM4_TRGO */ - .cfgr2 = 0U, - .ccr = 0U, - .pcsel = ADC_SELMASK_IN0 | ADC_SELMASK_IN5, - .ltr1 = 0x00000000U, - .htr1 = 0x03FFFFFFU, - .ltr2 = 0x00000000U, - .htr2 = 0x03FFFFFFU, - .ltr3 = 0x00000000U, - .htr3 = 0x03FFFFFFU, - .smpr = { - ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_384P5) | - ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_384P5), - 0U - }, - .sqr = { - ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN5), - 0U, - 0U, - 0U - } + .cfgr1 = ADC_CFGR1_CONT | + ADC_CFGR1_RES_12BIT | + ADC_CFGR1_EXTEN_RISING | + ADC_CFGR1_EXTSEL_SRC(0) /* CFGR1 */ + .cfgr2 = 0, /* CFGR2 */ + .tr = ADC_TR(0, 0), /* TR */ + .smpr = ADC_SMPR_SMP_39P5, /* SMPR */ + .chselr = ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL11 | + ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL18 /* CHSELR */ }; /*===========================================================================*/ diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.h b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/portab.h similarity index 88% rename from testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.h rename to testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/portab.h index 500e4f2ab..1bdf4aa76 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/portab.h +++ b/testhal/STM32/multi/ADC/cfg/stm32l053r8_nucleo64/portab.h @@ -29,20 +29,20 @@ /* Module constants. */ /*===========================================================================*/ -#define PORTAB_LINE_LED1 LINE_LED1 -#define PORTAB_LINE_LED2 LINE_LED2 +#define PORTAB_LINE_LED1 GPIOA_LED_GREEN +//#define PORTAB_LINE_LED2 LINE_LED2 #define PORTAB_LED_OFF PAL_LOW #define PORTAB_LED_ON PAL_HIGH #define PORTAB_LINE_BUTTON LINE_BUTTON -#define PORTAB_BUTTON_PRESSED PAL_HIGH +#define PORTAB_BUTTON_PRESSED PAL_LOW -#define PORTAB_SD1 SD2 +#define PORTAB_SD1 LPSD1 -#define PORTAB_GPT1 GPTD4 +#define PORTAB_GPT1 GPTD6 #define PORTAB_ADC1 ADCD1 -#define ADC_GRP1_NUM_CHANNELS 2 -#define ADC_GRP2_NUM_CHANNELS 2 +#define ADC_GRP1_NUM_CHANNELS 1 +#define ADC_GRP2_NUM_CHANNELS 4 /*===========================================================================*/ /* Module pre-compile time settings. */ diff --git a/testhal/STM32/multi/ADC/make/stm32h743zi_nucleo144.make b/testhal/STM32/multi/ADC/make/stm32h743zi_nucleo144.make new file mode 100644 index 000000000..347c0e688 --- /dev/null +++ b/testhal/STM32/multi/ADC/make/stm32h743zi_nucleo144.make @@ -0,0 +1,191 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m7 + +# Imported source files and paths. +CHIBIOS := ../../../.. +CONFDIR := ./cfg/stm32h743zi_nucleo144 +BUILDDIR := ./build/stm32h743zi_nucleo144 +DEPDIR := ./.dep/stm32h743zi_nucleo144 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/test/lib/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk +#include $(CHIBIOS)/os/hal/lib/streams/streams.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32H743xI.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DSTM32_ENFORCE_H7_REV_V # Must be removed for non-Rev-V devices. + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/STM32/multi/ADC/make/stm32h743_nucleo144.make b/testhal/STM32/multi/ADC/make/stm32l053r8_nucleo64.make similarity index 85% rename from testhal/STM32/multi/ADC/make/stm32h743_nucleo144.make rename to testhal/STM32/multi/ADC/make/stm32l053r8_nucleo64.make index 4a4d49452..9846f4cd5 100644 --- a/testhal/STM32/multi/ADC/make/stm32h743_nucleo144.make +++ b/testhal/STM32/multi/ADC/make/stm32l053r8_nucleo64.make @@ -60,7 +60,7 @@ endif # Stack size to be allocated to the Cortex-M process stack. This stack is # the stack used by the main() thread. ifeq ($(USE_PROCESS_STACKSIZE),) - USE_PROCESS_STACKSIZE = 0x400 + USE_PROCESS_STACKSIZE = 0x200 endif # Stack size to the allocated to the Cortex-M main/exceptions stack. This @@ -74,11 +74,6 @@ ifeq ($(USE_FPU),) USE_FPU = no endif -# FPU-related options. -ifeq ($(USE_FPU_OPT),) - USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 -fsingle-precision-constant -endif - # # Architecture or project specific options ############################################################################## @@ -92,32 +87,29 @@ PROJECT = ch # Imported source files and paths CHIBIOS := ../../../.. -CONFDIR := ./cfg/stm32h743_nucleo144 -BUILDDIR := ./build/stm32h743_nucleo144 -DEPDIR := ./.dep/stm32h743_nucleo144 +CONFDIR := ./cfg/stm32l053r8_nucleo64 +BUILDDIR := ./build/stm32l063r8_nucleo64 +DEPDIR := ./.dep/stm32l053r8_nucleo64 # Licensing files. include $(CHIBIOS)/os/license/license.mk # Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk -include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H743ZI/board.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L053R8/board.mk include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk -# Auto-build files in ./source recursively. -include $(CHIBIOS)/tools/mk/autobuild.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk # Other files (optional). #include $(CHIBIOS)/test/lib/test.mk #include $(CHIBIOS)/test/rt/rt_test.mk #include $(CHIBIOS)/test/oslib/oslib_test.mk -#include $(CHIBIOS)/os/hal/lib/streams/streams.mk # Define linker script file here -LDSCRIPT= $(STARTUPLD)/STM32H743xI.ld +LDSCRIPT= $(STARTUPLD)/STM32L053x8.ld # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -154,40 +146,17 @@ TCPPSRC = ASMSRC = $(ALLASMSRC) ASMXSRC = $(ALLXASMSRC) -INCDIR = $(ALLINC) $(TESTINC) $(CONFDIR) +INCDIR = $(ALLINC) $(TESTINC) # # Project, sources and paths ############################################################################## -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user section -############################################################################## - ############################################################################## # Compiler settings # -MCU = cortex-m7 +MCU = cortex-m0 #TRGT = arm-elf- TRGT = arm-none-eabi- @@ -222,5 +191,28 @@ CPPWARN = -Wall -Wextra -Wundef # Compiler settings ############################################################################## +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk include $(RULESPATH)/rules.mk