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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13471 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2020-03-24 11:14:00 +00:00
parent 8a2e2c9779
commit 0cfd870354
8 changed files with 1145 additions and 675 deletions
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7
os/hal/ports/STM32/LLD/RCCv1/driver.mk Normal file
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@ -0,0 +1,7 @@
ifeq ($(USE_SMART_BUILD),yes)
PLATFORMSRC +=
else
PLATFORMSRC +=
endif
PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1

346
os/hal/ports/STM32/LLD/RCCv1/stm32_pll.inc Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RCCv1/stm32_pll.inc
* @brief Shared PLL handler.
*
* @addtogroup STM32_PLL_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_PLL)
#define STM32_HAS_PLL FALSE
#endif
#if STM32_HAS_PLL
/* Checks on configurations.*/
#if !defined(STM32_PLLSRC)
#error "STM32_PLLSRC not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLM_VALUE)
#error "STM32_PLLM_VALUE not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLN_VALUE)
#error "STM32_PLLN_VALUE not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLPDIV_VALUE)
#error "STM32_PLLPDIV_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLL_HAS_P && !defined(STM32_PLLP_VALUE)
#error "STM32_PLLP_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLL_HAS_Q && !defined(STM32_PLLQ_VALUE)
#error "STM32_PLLQ_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLL_HAS_R && !defined(STM32_PLLR_VALUE)
#error "STM32_PLLR_VALUE not defined in mcuconf.h"
#endif
/* Check on limits.*/
#if !defined(STM32_PLLIN_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLIN_MIN)
#error "STM32_PLLIN_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLVCO_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLVCO_MIN)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLP_MAX)
#error "STM32_PLLP_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLP_MIN)
#error "STM32_PLLP_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLQ_MAX)
#error "STM32_PLLQ_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLQ_MIN)
#error "STM32_PLLQ_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLR_MAX)
#error "STM32_PLLR_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLR_MIN)
#error "STM32_PLLR_MIN not defined in hal_lld.h"
#endif
/* Input checks.*/
#if !defined(STM32_ACTIVATE_PLL)
#error "STM32_ACTIVATE_PLL not defined in hal_lld.h"
#endif
#if STM32_PLL_HAS_P && !defined(STM32_PLLPEN)
#error "STM32_PLLPEN not defined in hal_lld.h"
#endif
#if STM32_PLL_HAS_Q && !defined(STM32_PLLQEN)
#error "STM32_PLLQEN not defined in hal_lld.h"
#endif
#if STM32_PLL_HAS_R && !defined(STM32_PLLREN)
#error "STM32_PLLREN not defined in hal_lld.h"
#endif
#if (STM32_PLLCLKIN != 0) && \
((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/**
* @brief STM32_PLLM field.
*/
#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
#else
#error "invalid STM32_PLLM_VALUE value specified"
#endif
/**
* @brief STM32_PLLN field.
*/
#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) || \
defined(__DOXYGEN__)
#define STM32_PLLN (STM32_PLLN_VALUE << 8)
#else
#error "invalid STM32_PLLN_VALUE value specified"
#endif
/**
* @brief PLL VCO frequency.
*/
#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
/*
* PLL VCO frequency range check.
*/
#if STM32_ACTIVATE_PLL && \
((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/*---------------------------------------------------------------------------*/
/* P output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLL_HAS_P || defined(__DOXYGEN__)
/**
* @brief PLL P output clock frequency.
*/
#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
#else
#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
#endif
/**
* @brief STM32_PLLP field.
*/
#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
#define STM32_PLLP (0 << 17)
#elif STM32_PLLP_VALUE == 17
#define STM32_PLLP (1 << 17)
#else
#error "invalid STM32_PLLP_VALUE value specified"
#endif
/**
* @brief STM32_PLLPDIV field.
*/
#if (STM32_PLLPDIV_VALUE == 0) || \
((STM32_PLLPDIV_VALUE >= 2) && (STM32_PLLPDIV_VALUE <= 31)) || \
defined(__DOXYGEN__)
#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
#else
#error "invalid STM32_PLLPDIV_VALUE value specified"
#endif
/*
* PLL-P output frequency range check.
*/
#if STM32_ACTIVATE_PLL && \
((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif
#else /* !STM32_PLL_HAS_P */
#define STM32_PLLP 0
#define STM32_PLLPEN 0
#endif /* !STM32_PLL_HAS_P */
/*---------------------------------------------------------------------------*/
/* Q output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLL_HAS_Q || defined(__DOXYGEN__)
/**
* @brief STM32_PLLQ field.
*/
#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLQ (0 << 21)
#elif STM32_PLLQ_VALUE == 4
#define STM32_PLLQ (1 << 21)
#elif STM32_PLLQ_VALUE == 6
#define STM32_PLLQ (2 << 21)
#elif STM32_PLLQ_VALUE == 8
#define STM32_PLLQ (3 << 21)
#else
#error "invalid STM32_PLLQ_VALUE value specified"
#endif
/**
* @brief PLL Q output clock frequency.
*/
#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
/*
* PLL-Q output frequency range check.
*/
#if STM32_ACTIVATE_PLL && \
((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif
#else /* !STM32_PLL_HAS_Q */
#define STM32_PLLQ 0
#define STM32_PLLQEN 0
#endif /* !STM32_PLL_HAS_Q */
/*---------------------------------------------------------------------------*/
/* R output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLL_HAS_R || defined(__DOXYGEN__)
/**
* @brief STM32_PLLR field.
*/
#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLR (0 << 25)
#elif STM32_PLLR_VALUE == 4
#define STM32_PLLR (1 << 25)
#elif STM32_PLLR_VALUE == 6
#define STM32_PLLR (2 << 25)
#elif STM32_PLLR_VALUE == 8
#define STM32_PLLR (3 << 25)
#else
#error "invalid STM32_PLLR_VALUE value specified"
#endif
/**
* @brief PLL R output clock frequency.
*/
#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
/*
* PLL-R output frequency range check.
*/
#if STM32_ACTIVATE_PLL && \
((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
#else /* !STM32_PLL_HAS_R */
#define STM32_PLLR 0
#define STM32_PLLREN 0
#endif /* !STM32_PLL_HAS_R */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void pll_init(void) {
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->PLLCFGR = STM32_PLLPDIV | STM32_PLLR |
STM32_PLLREN | STM32_PLLQ |
STM32_PLLQEN | STM32_PLLP |
STM32_PLLPEN | STM32_PLLN |
STM32_PLLM;
RCC->CR |= RCC_CR_PLLON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLRDY) == 0)
;
#endif
}
static inline void pll_deinit(void) {
/* PLL de-activation.*/
RCC->PLLCFGR &= ~RCC_CR_PLLON;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
#endif /* STM32_HAS_PLL */
/** @} */

334
os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai1.inc Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RCCv1/stm32_pllsai1.inc
* @brief Shared PLLSAI1 handler.
*
* @addtogroup STM32_PLLSAI1_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_PLLSAI1)
#define STM32_HAS_PLLSAI1 FALSE
#endif
#if STM32_HAS_PLLSAI1
/* Checks on configurations.*/
#if !defined(STM32_PLLSRC)
#error "STM32_PLLSRC not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLSAI1M_VALUE)
#error "STM32_PLLSAI1M_VALUE not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLSAI1N_VALUE)
#error "STM32_PLLSAI1N_VALUE not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLSAI1PDIV_VALUE)
#error "STM32_PLLSAI1PDIV_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLLSAI1_HAS_P && !defined(STM32_PLLSAI1P_VALUE)
#error "STM32_PLLSAI1P_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLLSAI1_HAS_Q && !defined(STM32_PLLSAI1Q_VALUE)
#error "STM32_PLLSAI1Q_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLLSAI1_HAS_R && !defined(STM32_PLLSAI1R_VALUE)
#error "STM32_PLLSAI1R_VALUE not defined in mcuconf.h"
#endif
/* Check on limits.*/
#if !defined(STM32_PLLIN_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLIN_MIN)
#error "STM32_PLLIN_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLVCO_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLVCO_MIN)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLP_MAX)
#error "STM32_PLLP_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLP_MIN)
#error "STM32_PLLP_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLQ_MAX)
#error "STM32_PLLQ_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLQ_MIN)
#error "STM32_PLLQ_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLR_MAX)
#error "STM32_PLLR_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLR_MIN)
#error "STM32_PLLR_MIN not defined in hal_lld.h"
#endif
/* Input checks.*/
#if !defined(STM32_ACTIVATE_PLLSAI1)
#error "STM32_ACTIVATE_PLLSAI1 not defined in hal_lld.h"
#endif
#if STM32_PLLSAI1_HAS_P && !defined(STM32_PLLSAI1PEN)
#error "STM32_PLLSAI1PEN not defined in hal_lld.h"
#endif
#if STM32_PLLSAI1_HAS_Q && !defined(STM32_PLLSAI1QEN)
#error "STM32_PLLSAI1QEN not defined in hal_lld.h"
#endif
#if STM32_PLLSAI1_HAS_R && !defined(STM32_PLLSAI1REN)
#error "STM32_PLLSAI1REN not defined in hal_lld.h"
#endif
#if (STM32_PLLSAI1CLKIN != 0) && \
((STM32_PLLSAI1CLKIN < STM32_PLLIN_MIN) || (STM32_PLLSAI1CLKIN > STM32_PLLIN_MAX))
#error "STM32_PLLSAI1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/**
* @brief STM32_PLLSAI1M field.
*/
#if ((STM32_PLLSAI1M_VALUE >= 1) && (STM32_PLLSAI1M_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1M ((STM32_PLLSAI1M_VALUE - 1) << 4)
#else
#error "invalid STM32_PLLSAI1M_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI1N field.
*/
#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 127)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << 8)
#else
#error "invalid STM32_PLLSAI1N_VALUE value specified"
#endif
/**
* @brief PLLSAI1 VCO frequency.
*/
#define STM32_PLLSAI1VCO (STM32_PLLSAI1CLKIN * STM32_PLLSAI1N_VALUE)
/*
* PLLSAI1 VCO frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI1VCO > STM32_PLLVCO_MAX))
#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/*---------------------------------------------------------------------------*/
/* P output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLLSAI1_HAS_P || defined(__DOXYGEN__)
/**
* @brief PLLSAI1 P output clock frequency.
*/
#if (STM32_PLLSAI1PDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
#else
#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE)
#endif
/**
* @brief STM32_PLLSAI1P field.
*/
#if (STM32_PLLSAI1P_VALUE == 7) || defined(__DOXYGEN__)
#define STM32_PLLSAI1P (0 << 17)
#elif STM32_PLLSAI1P_VALUE == 17
#define STM32_PLLSAI1P (1 << 17)
#else
#error "invalid STM32_PLLSAI1P_VALUE value specified"
#endif
/*
* PLLSAI1-P output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif
#else /* !STM32_PLLSAI1_HAS_P */
#define STM32_PLLSAI1P 0
#define STM32_PLLSAI1PEN 0
#endif /* !STM32_PLLSAI1_HAS_P */
/*---------------------------------------------------------------------------*/
/* Q output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLLSAI1_HAS_Q || defined(__DOXYGEN__)
/**
* @brief STM32_PLLSAI1Q field.
*/
#if (STM32_PLLSAI1Q_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLSAI1Q (0 << 21)
#elif STM32_PLLSAI1Q_VALUE == 4
#define STM32_PLLSAI1Q (1 << 21)
#elif STM32_PLLSAI1Q_VALUE == 6
#define STM32_PLLSAI1Q (2 << 21)
#elif STM32_PLLSAI1Q_VALUE == 8
#define STM32_PLLSAI1Q (3 << 21)
#else
#error "invalid STM32_PLLSAI1Q_VALUE value specified"
#endif
/**
* @brief PLLSAI1 Q output clock frequency.
*/
#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
/*
* PLLSAI1-Q output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif
#else /* !STM32_PLLSAI1_HAS_Q */
#define STM32_PLLSAI1Q 0
#define STM32_PLLSAI1QEN 0
#endif /* !STM32_PLLSAI1_HAS_Q */
/*---------------------------------------------------------------------------*/
/* R output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLLSAI1_HAS_R || defined(__DOXYGEN__)
/**
* @brief STM32_PLLSAI1R field.
*/
#if (STM32_PLLSAI1R_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLSAI1R (0 << 25)
#elif STM32_PLLSAI1R_VALUE == 4
#define STM32_PLLSAI1R (1 << 25)
#elif STM32_PLLSAI1R_VALUE == 6
#define STM32_PLLSAI1R (2 << 25)
#elif STM32_PLLSAI1R_VALUE == 8
#define STM32_PLLSAI1R (3 << 25)
#else
#error "invalid STM32_PLLSAI1R_VALUE value specified"
#endif
/**
* @brief PLLSAI1 R output clock frequency.
*/
#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE)
/*
* PLLSAI1-R output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
#else /* !STM32_PLLSAI1_HAS_R */
#define STM32_PLLSAI1R 0
#define STM32_PLLSAI1REN 0
#endif /* !STM32_PLLSAI1_HAS_R */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void pllsai1_init(void) {
#if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/
RCC->PLLSAI1CFGR = STM32_PLLSAI1PDIV | STM32_PLLSAI1R |
STM32_PLLSAI1REN | STM32_PLLSAI1Q |
STM32_PLLSAI1QEN | STM32_PLLSAI1P |
STM32_PLLSAI1PEN | STM32_PLLSAI1N |
STM32_PLLSAI1M;
RCC->CR |= RCC_CR_PLLSAI1ON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0)
;
#endif
}
static inline void pllsai1_deinit(void) {
/* PLLSAI1 de-activation.*/
RCC->PLLSAI1CFGR &= ~RCC_CR_PLLSAI1ON;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
#endif /* STM32_HAS_PLLSAI1 */
/** @} */

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os/hal/ports/STM32/LLD/RCCv1/stm32_pllsai2.inc Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file RCCv1/stm32_pllsai2.inc
* @brief Shared PLLSAI2 handler.
*
* @addtogroup STM32_PLLSAI2_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_PLLSAI2)
#define STM32_HAS_PLLSAI2 FALSE
#endif
#if STM32_HAS_PLLSAI2
/* Checks on configurations.*/
#if !defined(STM32_PLLSRC)
#error "STM32_PLLSRC not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLSAI2M_VALUE)
#error "STM32_PLLSAI2M_VALUE not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLSAI2N_VALUE)
#error "STM32_PLLSAI2N_VALUE not defined in mcuconf.h"
#endif
#if !defined(STM32_PLLSAI2PDIV_VALUE)
#error "STM32_PLLSAI2PDIV_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLLSAI2_HAS_P && !defined(STM32_PLLSAI2P_VALUE)
#error "STM32_PLLSAI2P_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLLSAI2_HAS_Q && !defined(STM32_PLLSAI2Q_VALUE)
#error "STM32_PLLSAI2Q_VALUE not defined in mcuconf.h"
#endif
#if STM32_PLLSAI2_HAS_R && !defined(STM32_PLLSAI2R_VALUE)
#error "STM32_PLLSAI2R_VALUE not defined in mcuconf.h"
#endif
/* Check on limits.*/
#if !defined(STM32_PLLIN_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLIN_MIN)
#error "STM32_PLLIN_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLVCO_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLVCO_MIN)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLP_MAX)
#error "STM32_PLLP_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLP_MIN)
#error "STM32_PLLP_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLQ_MAX)
#error "STM32_PLLQ_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLQ_MIN)
#error "STM32_PLLQ_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLR_MAX)
#error "STM32_PLLR_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLLR_MIN)
#error "STM32_PLLR_MIN not defined in hal_lld.h"
#endif
/* Input checks.*/
#if !defined(STM32_ACTIVATE_PLLSAI2)
#error "STM32_ACTIVATE_PLLSAI2 not defined in hal_lld.h"
#endif
#if STM32_PLLSAI2_HAS_P && !defined(STM32_PLLSAI2PEN)
#error "STM32_PLLSAI2PEN not defined in hal_lld.h"
#endif
#if STM32_PLLSAI2_HAS_Q && !defined(STM32_PLLSAI2QEN)
#error "STM32_PLLSAI2QEN not defined in hal_lld.h"
#endif
#if STM32_PLLSAI2_HAS_R && !defined(STM32_PLLSAI2REN)
#error "STM32_PLLSAI2REN not defined in hal_lld.h"
#endif
#if (STM32_PLLSAI2CLKIN != 0) && \
((STM32_PLLSAI2CLKIN < STM32_PLLIN_MIN) || (STM32_PLLSAI2CLKIN > STM32_PLLIN_MAX))
#error "STM32_PLLSAI2CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/**
* @brief STM32_PLLSAI2M field.
*/
#if ((STM32_PLLSAI2M_VALUE >= 1) && (STM32_PLLSAI2M_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI2M ((STM32_PLLSAI2M_VALUE - 1) << 4)
#else
#error "invalid STM32_PLLSAI2M_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI2N field.
*/
#if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 127)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI2N (STM32_PLLSAI2N_VALUE << 8)
#else
#error "invalid STM32_PLLSAI2N_VALUE value specified"
#endif
/**
* @brief PLLSAI2 VCO frequency.
*/
#define STM32_PLLSAI2VCO (STM32_PLLSAI2CLKIN * STM32_PLLSAI2N_VALUE)
/*
* PLLSAI2 VCO frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI2 && \
((STM32_PLLSAI2VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI2VCO > STM32_PLLVCO_MAX))
#error "STM32_PLLSAI2VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/*---------------------------------------------------------------------------*/
/* P output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLLSAI2_HAS_P || defined(__DOXYGEN__)
/**
* @brief PLLSAI2 P output clock frequency.
*/
#if (STM32_PLLSAI2PDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
#else
#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE)
#endif
/**
* @brief STM32_PLLSAI2P field.
*/
#if (STM32_PLLSAI2P_VALUE == 7) || defined(__DOXYGEN__)
#define STM32_PLLSAI2P (0 << 17)
#elif STM32_PLLSAI2P_VALUE == 17
#define STM32_PLLSAI2P (1 << 17)
#else
#error "invalid STM32_PLLSAI2P_VALUE value specified"
#endif
/*
* PLLSAI2-P output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI2 && \
((STM32_PLLSAI2_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI2_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLLSAI2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif
#else /* !STM32_PLLSAI2_HAS_P */
#define STM32_PLLSAI2P 0
#define STM32_PLLSAI2PEN 0
#endif /* !STM32_PLLSAI2_HAS_P */
/*---------------------------------------------------------------------------*/
/* Q output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLLSAI2_HAS_Q || defined(__DOXYGEN__)
/**
* @brief STM32_PLLSAI2Q field.
*/
#if (STM32_PLLSAI2Q_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLSAI2Q (0 << 21)
#elif STM32_PLLSAI2Q_VALUE == 4
#define STM32_PLLSAI2Q (1 << 21)
#elif STM32_PLLSAI2Q_VALUE == 6
#define STM32_PLLSAI2Q (2 << 21)
#elif STM32_PLLSAI2Q_VALUE == 8
#define STM32_PLLSAI2Q (3 << 21)
#else
#error "invalid STM32_PLLSAI2Q_VALUE value specified"
#endif
/**
* @brief PLLSAI2 Q output clock frequency.
*/
#define STM32_PLLSAI2_Q_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2Q_VALUE)
/*
* PLLSAI2-Q output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI2 && \
((STM32_PLLSAI2_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI2_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLLSAI2_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif
#else /* !STM32_PLLSAI2_HAS_Q */
#define STM32_PLLSAI2Q 0
#define STM32_PLLSAI2QEN 0
#endif /* !STM32_PLLSAI2_HAS_Q */
/*---------------------------------------------------------------------------*/
/* R output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_PLLSAI2_HAS_R || defined(__DOXYGEN__)
/**
* @brief STM32_PLLSAI2R field.
*/
#if (STM32_PLLSAI2R_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLSAI2R (0 << 25)
#elif STM32_PLLSAI2R_VALUE == 4
#define STM32_PLLSAI2R (1 << 25)
#elif STM32_PLLSAI2R_VALUE == 6
#define STM32_PLLSAI2R (2 << 25)
#elif STM32_PLLSAI2R_VALUE == 8
#define STM32_PLLSAI2R (3 << 25)
#else
#error "invalid STM32_PLLSAI2R_VALUE value specified"
#endif
/**
* @brief PLLSAI2 R output clock frequency.
*/
#define STM32_PLLSAI2_R_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2R_VALUE)
/*
* PLLSAI2-R output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI2 && \
((STM32_PLLSAI2_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI2_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLLSAI2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
#else /* !STM32_PLLSAI2_HAS_R */
#define STM32_PLLSAI2R 0
#define STM32_PLLSAI2REN 0
#endif /* !STM32_PLLSAI2_HAS_R */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void pllsai2_init(void) {
#if STM32_ACTIVATE_PLLSAI2
/* PLLSAI2 activation.*/
RCC->PLLSAI2CFGR = STM32_PLLSAI2PDIV | STM32_PLLSAI2R |
STM32_PLLSAI2REN | STM32_PLLSAI2Q |
STM32_PLLSAI2QEN | STM32_PLLSAI2P |
STM32_PLLSAI2PEN | STM32_PLLSAI2N |
STM32_PLLSAI2M;
RCC->CR |= RCC_CR_PLLSAI2ON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLSAI2RDY) == 0)
;
#endif
}
static inline void pllsai2_deinit(void) {
/* PLLSAI2 de-activation.*/
RCC->PLLSAI2CFGR &= ~RCC_CR_PLLSAI2ON;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
#endif /* STM32_HAS_PLLSAI2 */
/** @} */

8
os/hal/ports/STM32/STM32L5xx/hal_lld.c
View File

@ -269,14 +269,8 @@ void stm32_clock_init(void) {
STM32_PLLM | STM32_PLLSRC;
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CR |= RCC_CR_PLLON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLRDY) == 0)
;
#endif
pll_init();
#if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/

774
os/hal/ports/STM32/STM32L5xx/hal_lld.h
View File

@ -481,57 +481,17 @@
#endif
/**
* @brief PLLM divider value.
* @note The allowed values are 1..16.
* @note The default value is calculated for a 120MHz system clock from
* the internal 4MHz MSI clock.
* @brief Clock source for the PLLSAL1.
*/
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLM_VALUE 1
#if !defined(STM32_PLLSAI1SRC) || defined(__DOXYGEN__)
#define STM32_PLLSAI1SRC STM32_PLLSAI1SRC_MSI
#endif
/**
* @brief PLLN multiplier value.
* @note The allowed values are 8..127.
* @note The default value is calculated for a 120MHz system clock from
* the internal 4MHz MSI clock.
* @brief Clock source for the PLLSAL2.
*/
#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLN_VALUE 55
#endif
/**
* @brief PLLPDIV divider value or zero if disabled.
* @note The allowed values are 0, 2..31.
*/
#if !defined(STM32_PLLPDIV_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLPDIV_VALUE 0
#endif
/**
* @brief PLLP divider value.
* @note The allowed values are 7, 17.
*/
#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLP_VALUE 7
#endif
/**
* @brief PLLQ divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLQ_VALUE 4
#endif
/**
* @brief PLLR divider value.
* @note The allowed values are 2, 4, 6, 8.
* @note The default value is calculated for a 120MHz system clock from
* the internal 4MHz MSI clock.
*/
#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLR_VALUE 2
#if !defined(STM32_PLLSAI2SRC) || defined(__DOXYGEN__)
#define STM32_PLLSAI2SRC STM32_PLLSAI2SRC_MSI
#endif
/**
@ -585,120 +545,6 @@
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
#endif
/**
* @brief Clock source for the PLLSAL1.
*/
#if !defined(STM32_PLLSAI1SRC) || defined(__DOXYGEN__)
#define STM32_PLLSAI1SRC STM32_PLLSAI1SRC_MSI
#endif
/**
* @brief PLLSAI1M divider value.
* @note The allowed values are 1..16.
* @note The default value is calculated for a 120MHz system clock from
* the internal 4MHz MSI clock.
*/
#if !defined(STM32_PLLSAI1M_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1M_VALUE 1
#endif
/**
* @brief PLLSAI1N multiplier value.
* @note The allowed values are 8..127.
*/
#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1N_VALUE 72
#endif
/**
* @brief PLLSAI1PDIV divider value or zero if disabled.
* @note The allowed values are 0, 2..31.
*/
#if !defined(STM32_PLLSAI1PDIV_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1PDIV_VALUE 6
#endif
/**
* @brief PLLSAI1P divider value.
* @note The allowed values are 7, 17.
*/
#if !defined(STM32_PLLSAI1P_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1P_VALUE 7
#endif
/**
* @brief PLLSAI1Q divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLSAI1Q_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1Q_VALUE 6
#endif
/**
* @brief PLLSAI1R divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLSAI1R_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1R_VALUE 6
#endif
/**
* @brief Clock source for the PLLSAL2.
*/
#if !defined(STM32_PLLSAI2SRC) || defined(__DOXYGEN__)
#define STM32_PLLSAI2SRC STM32_PLLSAI2SRC_MSI
#endif
/**
* @brief PLLSAI2M divider value.
* @note The allowed values are 1..16.
* @note The default value is calculated for a 120MHz system clock from
* the internal 4MHz MSI clock.
*/
#if !defined(STM32_PLLSAI2M_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2M_VALUE 1
#endif
/**
* @brief PLLSAI2N multiplier value.
* @note The allowed values are 8..127.
*/
#if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2N_VALUE 72
#endif
/**
* @brief PLLSAI2PDIV divider value or zero if disabled.
* @note The allowed values are 0, 2..31.
*/
#if !defined(STM32_PLLSAI2PDIV_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2PDIV_VALUE 6
#endif
/**
* @brief PLLSAI2P divider value.
* @note The allowed values are 7, 17.
*/
#if !defined(STM32_PLLSAI2P_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2P_VALUE 7
#endif
/**
* @brief PLLSAI2Q divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLSAI2Q_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2Q_VALUE 6
#endif
/**
* @brief PLLSAI2R divider value.
* @note The allowed values are 2, 4, 6, 8.
*/
#if !defined(STM32_PLLSAI2R_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2R_VALUE 6
#endif
/**
* @brief USART1 clock source.
*/
@ -1395,16 +1241,6 @@
#warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED"
#endif
/**
* @brief STM32_PLLM field.
*/
#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
#else
#error "invalid STM32_PLLM_VALUE value specified"
#endif
/**
* @brief PLL input clock frequency.
*/
@ -1424,12 +1260,42 @@
#error "invalid STM32_PLLSRC value specified"
#endif
/*
* PLL input frequency range check.
/**
* @brief PLLSAI1 input clock frequency.
*/
#if (STM32_PLLCLKIN != 0) && \
((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#if (STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1CLKIN (STM32_HSECLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_MSI
#define STM32_PLLSAI1CLKIN (STM32_MSICLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSI16
#define STM32_PLLSAI1CLKIN (STM32_HSI16CLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSSAI1RC == STM32_PLLSAI1SRC_NOCLOCK
#define STM32_PLLSAI1CLKIN 0
#else
#error "invalid STM32_PLLSAI1SRC value specified"
#endif
/**
* @brief PLLSAI2 input clock frequency.
*/
#if (STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2CLKIN (STM32_HSECLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_MSI
#define STM32_PLLSAI2CLKIN (STM32_MSICLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSI16
#define STM32_PLLSAI2CLKIN (STM32_HSI16CLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_NOCLOCK
#define STM32_PLLSAI2CLKIN 0
#else
#error "invalid STM32_PLLSAI2SRC value specified"
#endif
/*
@ -1449,81 +1315,50 @@
/**
* @brief PLL activation flag.
*/
#define STM32_ACTIVATE_PLL TRUE
#define STM32_ACTIVATE_PLL TRUE
#else
#define STM32_ACTIVATE_PLL FALSE
#define STM32_ACTIVATE_PLL FALSE
#endif
/**
* @brief STM32_PLLN field.
/*
* PLLSAI1 enable check.
*/
#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) || \
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
(STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
defined(__DOXYGEN__)
#define STM32_PLLN (STM32_PLLN_VALUE << 8)
#else
#error "invalid STM32_PLLN_VALUE value specified"
#endif
#if STM32_PLLSAI1CLKIN == 0
#error "PLLSAI1 activation required but no PLL clock selected"
#endif
/**
* @brief STM32_PLLP field.
* @brief PLLSAI1 activation flag.
*/
#if (STM32_PLLP_VALUE == 7) || defined(__DOXYGEN__)
#define STM32_PLLP (0 << 17)
#elif STM32_PLLP_VALUE == 17
#define STM32_PLLP (1 << 17)
#define STM32_ACTIVATE_PLLSAI1 TRUE
#else
#error "invalid STM32_PLLP_VALUE value specified"
#define STM32_ACTIVATE_PLLSAI1 FALSE
#endif
/**
* @brief STM32_PLLQ field.
/*
* PLLSAI2 enable check.
*/
#if (STM32_PLLQ_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLQ (0 << 21)
#elif STM32_PLLQ_VALUE == 4
#define STM32_PLLQ (1 << 21)
#elif STM32_PLLQ_VALUE == 6
#define STM32_PLLQ (2 << 21)
#elif STM32_PLLQ_VALUE == 8
#define STM32_PLLQ (3 << 21)
#else
#error "invalid STM32_PLLQ_VALUE value specified"
#endif
/**
* @brief STM32_PLLR field.
*/
#if (STM32_PLLR_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLR (0 << 25)
#elif STM32_PLLR_VALUE == 4
#define STM32_PLLR (1 << 25)
#elif STM32_PLLR_VALUE == 6
#define STM32_PLLR (2 << 25)
#elif STM32_PLLR_VALUE == 8
#define STM32_PLLR (3 << 25)
#else
#error "invalid STM32_PLLR_VALUE value specified"
#endif
/**
* @brief STM32_PLLPDIV field.
*/
#if (STM32_PLLPDIV_VALUE == 0) || \
((STM32_PLLPDIV_VALUE != 1) && (STM32_PLLPDIV_VALUE <= 31)) || \
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
defined(__DOXYGEN__)
#define STM32_PLLPDIV (STM32_PLLPDIV_VALUE << 27)
#if STM32_PLLSAI2CLKIN == 0
#error "PLLSAI2 activation required but no PLL clock selected"
#endif
/**
* @brief PLLSAI2 activation flag.
*/
#define STM32_ACTIVATE_PLLSAI2 TRUE
#else
#error "invalid STM32_PLLPDIV_VALUE value specified"
#define STM32_ACTIVATE_PLLSAI2 FALSE
#endif
/**
@ -1532,18 +1367,18 @@
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLL) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLL) || \
defined(__DOXYGEN__)
#define STM32_PLLPEN (1 << 16)
#define STM32_PLLPEN (1 << 16)
#else
#define STM32_PLLPEN (0 << 16)
#define STM32_PLLPEN (0 << 16)
#endif
/**
* @brief STM32_PLLQEN field.
*/
#if (STM32_CLK48SEL == STM32_CLK48SEL_PLL) || defined(__DOXYGEN__)
#define STM32_PLLQEN (1 << 20)
#define STM32_PLLQEN (1 << 20)
#else
#define STM32_PLLQEN (0 << 20)
#define STM32_PLLQEN (0 << 20)
#endif
/**
@ -1552,66 +1387,55 @@
#if (STM32_SW == STM32_SW_PLL) || \
(STM32_MCOSEL == STM32_MCOSEL_PLL) || \
defined(__DOXYGEN__)
#define STM32_PLLREN (1 << 24)
#define STM32_PLLREN (1 << 24)
#else
#define STM32_PLLREN (0 << 24)
#define STM32_PLLREN (0 << 24)
#endif
/**
* @brief PLL VCO frequency.
* @brief STM32_PLLSAI1PEN field.
*/
#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
/*
* PLL VCO frequency range check.
*/
#if STM32_ACTIVATE_PLL && \
((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/**
* @brief PLL P output clock frequency.
*/
#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1PEN (1 << 16)
#else
#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
#define STM32_PLLSAI1PEN (0 << 16)
#endif
/**
* @brief PLL Q output clock frequency.
* @brief STM32_PLLSAI1QEN field.
*/
#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || defined(__DOXYGEN__)
#define STM32_PLLSAI1QEN (1 << 20)
#else
#define STM32_PLLSAI1QEN (0 << 20)
#endif
/**
* @brief PLL R output clock frequency.
* @brief STM32_PLLSAI1REN field.
*/
#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
/*
* PLL-P output frequency range check.
*/
#if STM32_ACTIVATE_PLL && \
((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || defined(__DOXYGEN__)
#define STM32_PLLSAI1REN (1 << 24)
#else
#define STM32_PLLSAI1REN (0 << 24)
#endif
/*
* PLL-Q output frequency range check.
/**
* @brief STM32_PLLSAI2PEN field.
*/
#if STM32_ACTIVATE_PLL && \
((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI2PEN (1 << 16)
#else
#define STM32_PLLSAI2PEN (0 << 16)
#endif
/*
* PLL-R output frequency range check.
*/
#if STM32_ACTIVATE_PLL && \
((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
/* Inclusion of PLL-related checks and calculations.*/
#include <stm32_pll.inc>
#include "stm32_pllsai1.inc"
#include "stm32_pllsai2.inc"
/**
* @brief System clock source.
@ -1739,392 +1563,6 @@
#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
#endif
/**
* @brief STM32_PLLSAI1M field.
*/
#if ((STM32_PLLSAI1M_VALUE >= 1) && (STM32_PLLSAI1M_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1M ((STM32_PLLSAI1M_VALUE - 1) << 4)
#else
#error "invalid STM32_PLLSAI1M_VALUE value specified"
#endif
/**
* @brief PLLSAI1 input clock frequency.
*/
#if (STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLSAI1CLKIN (STM32_HSECLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_MSI
#define STM32_PLLSAI1CLKIN (STM32_MSICLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSAI1SRC == STM32_PLLSAI1SRC_HSI16
#define STM32_PLLSAI1CLKIN (STM32_HSI16CLK / STM32_PLLSAI1M_VALUE)
#elif STM32_PLLSSAI1RC == STM32_PLLSAI1SRC_NOCLOCK
#define STM32_PLLSAI1CLKIN 0
#else
#error "invalid STM32_PLLSAI1SRC value specified"
#endif
/*
* PLLSAI1 input frequency range check.
*/
#if (STM32_PLLSAI1CLKIN != 0) && \
((STM32_PLLSAI1CLKIN < STM32_PLLIN_MIN) || \
(STM32_PLLSAI1CLKIN > STM32_PLLIN_MAX))
#error "STM32_PLLSAI1CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/*
* PLLSAI1 enable check.
*/
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
(STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
defined(__DOXYGEN__)
#if STM32_PLLSAI1CLKIN == 0
#error "PLLSAI1 activation required but no PLL clock selected"
#endif
/**
* @brief PLLSAI1 activation flag.
*/
#define STM32_ACTIVATE_PLLSAI1 TRUE
#else
#define STM32_ACTIVATE_PLLSAI1 FALSE
#endif
/**
* @brief STM32_PLLSAI1N field.
*/
#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 127)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << 8)
#else
#error "invalid STM32_PLLSAI1N_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI1P field.
*/
#if (STM32_PLLSAI1P_VALUE == 7) || defined(__DOXYGEN__)
#define STM32_PLLSAI1P (0 << 17)
#elif STM32_PLLSAI1P_VALUE == 17
#define STM32_PLLSAI1P (1 << 17)
#else
#error "invalid STM32_PLLSAI1P_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI1Q field.
*/
#if (STM32_PLLSAI1Q_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLSAI1Q (0 << 21)
#elif STM32_PLLSAI1Q_VALUE == 4
#define STM32_PLLSAI1Q (1 << 21)
#elif STM32_PLLSAI1Q_VALUE == 6
#define STM32_PLLSAI1Q (2 << 21)
#elif STM32_PLLSAI1Q_VALUE == 8
#define STM32_PLLSAI1Q (3 << 21)
#else
#error "invalid STM32_PLLSAI1Q_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI1R field.
*/
#if (STM32_PLLSAI1R_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLSAI1R (0 << 25)
#elif STM32_PLLSAI1R_VALUE == 4
#define STM32_PLLSAI1R (1 << 25)
#elif STM32_PLLSAI1R_VALUE == 6
#define STM32_PLLSAI1R (2 << 25)
#elif STM32_PLLSAI1R_VALUE == 8
#define STM32_PLLSAI1R (3 << 25)
#else
#error "invalid STM32_PLLSAI1R_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI1PDIV field.
*/
#if ((STM32_PLLSAI1PDIV_VALUE != 1) && (STM32_PLLSAI1PDIV_VALUE <= 31)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1PDIV (STM32_PLLSAI1PDIV_VALUE << 27)
#else
#error "invalid STM32_PLLSAI1PDIV_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI1PEN field.
*/
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI1PEN (1 << 16)
#else
#define STM32_PLLSAI1PEN (0 << 16)
#endif
/**
* @brief STM32_PLLSAI1QEN field.
*/
#if (STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || defined(__DOXYGEN__)
#define STM32_PLLSAI1QEN (1 << 20)
#else
#define STM32_PLLSAI1QEN (0 << 20)
#endif
/**
* @brief STM32_PLLSAI1REN field.
*/
#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || defined(__DOXYGEN__)
#define STM32_PLLSAI1REN (1 << 24)
#else
#define STM32_PLLSAI1REN (0 << 24)
#endif
/**
* @brief PLLSAI1 VCO frequency.
*/
#define STM32_PLLSAI1VCO (STM32_PLLSAI1CLKIN * STM32_PLLSAI1N_VALUE)
/*
* PLLSAI1 VCO frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI1VCO > STM32_PLLVCO_MAX))
#error "STM32_PLLSAI1VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/**
* @brief PLLSAI1-P output clock frequency.
*/
#if (STM32_PLLSAI1PDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
#else
#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE)
#endif
/**
* @brief PLLSAI1-Q output clock frequency.
*/
#define STM32_PLLSAI1_Q_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
/**
* @brief PLLSAI1-R output clock frequency.
*/
#define STM32_PLLSAI1_R_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1R_VALUE)
/*
* PLLSAI1-P output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI1_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLLSAI1_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif
/*
* PLLSAI1-Q output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLLSAI1_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLLSAI1_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif
/*
* PLLSAI1-R output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI1 && \
((STM32_PLLSAI1_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI1_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLLSAI1_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
/**
* @brief STM32_PLLSAI2M field.
*/
#if ((STM32_PLLSAI2M_VALUE >= 1) && (STM32_PLLSAI2M_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI2M ((STM32_PLLSAI2M_VALUE - 1) << 4)
#else
#error "invalid STM32_PLLSAI2M_VALUE value specified"
#endif
/**
* @brief PLLSAI2 input clock frequency.
*/
#if (STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLSAI2CLKIN (STM32_HSECLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_MSI
#define STM32_PLLSAI2CLKIN (STM32_MSICLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_HSI16
#define STM32_PLLSAI2CLKIN (STM32_HSI16CLK / STM32_PLLSAI2M_VALUE)
#elif STM32_PLLSAI2SRC == STM32_PLLSAI2SRC_NOCLOCK
#define STM32_PLLSAI2CLKIN 0
#else
#error "invalid STM32_PLLSAI2SRC value specified"
#endif
/*
* PLLSAI2 input frequency range check.
*/
#if (STM32_PLLSAI2CLKIN != 0) && \
((STM32_PLLSAI2CLKIN < STM32_PLLIN_MIN) || \
(STM32_PLLSAI2CLKIN > STM32_PLLIN_MAX))
#error "STM32_PLLSAI2CLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/*
* PLLSAI2 enable check.
*/
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
(STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
defined(__DOXYGEN__)
#if STM32_PLLSAI2CLKIN == 0
#error "PLLSAI2 activation required but no PLL clock selected"
#endif
/**
* @brief PLLSAI2 activation flag.
*/
#define STM32_ACTIVATE_PLLSAI2 TRUE
#else
#define STM32_ACTIVATE_PLLSAI2 FALSE
#endif
/**
* @brief STM32_PLLSAI2N field.
*/
#if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 127)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI2N (STM32_PLLSAI2N_VALUE << 8)
#else
#error "invalid STM32_PLLSAI2N_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI2P field.
*/
#if (STM32_PLLSAI2P_VALUE == 7) || defined(__DOXYGEN__)
#define STM32_PLLSAI2P (0 << 17)
#elif STM32_PLLSAI2P_VALUE == 17
#define STM32_PLLSAI2P (1 << 17)
#else
#error "invalid STM32_PLLSAI2P_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI2R field.
*/
#if (STM32_PLLSAI2R_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLLSAI2R (0 << 25)
#elif STM32_PLLSAI2R_VALUE == 4
#define STM32_PLLSAI2R (1 << 25)
#elif STM32_PLLSAI2R_VALUE == 6
#define STM32_PLLSAI2R (2 << 25)
#elif STM32_PLLSAI2R_VALUE == 8
#define STM32_PLLSAI2R (3 << 25)
#else
#error "invalid STM32_PLLSAI2R_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI2PDIV field.
*/
#if ((STM32_PLLSAI2PDIV_VALUE != 1) && (STM32_PLLSAI2PDIV_VALUE <= 31)) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI2PDIV (STM32_PLLSAI2PDIV_VALUE << 27)
#else
#error "invalid STM32_PLLSAI2PDIV_VALUE value specified"
#endif
/**
* @brief STM32_PLLSAI2PEN field.
*/
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \
defined(__DOXYGEN__)
#define STM32_PLLSAI2PEN (1 << 16)
#else
#define STM32_PLLSAI2PEN (0 << 16)
#endif
/**
* @brief STM32_PLLSAI2REN field.
* @note Always enabled.
* @note It should depend on some condition.
*/
#define STM32_PLLSAI2REN (1 << 24)
/**
* @brief PLLSAI2 VCO frequency.
*/
#define STM32_PLLSAI2VCO (STM32_PLLSAI2CLKIN * STM32_PLLSAI2N_VALUE)
/*
* PLLSAI2 VCO frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI2 && \
((STM32_PLLSAI2VCO < STM32_PLLVCO_MIN) || (STM32_PLLSAI2VCO > STM32_PLLVCO_MAX))
#error "STM32_PLLSAI2VCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/**
* @brief PLLSAI2-P output clock frequency.
*/
#if (STM32_PLLSAI2PDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
#else
#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE)
#endif
/**
* @brief PLLSAI2-R output clock frequency.
*/
#define STM32_PLLSAI2_R_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2R_VALUE)
/*
* PLLSAI2-P output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI2 && \
((STM32_PLLSAI2_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLLSAI2_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLLSAI2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif
/*
* PLLSAI2-R output frequency range check.
*/
#if STM32_ACTIVATE_PLLSAI2 && \
((STM32_PLLSAI2_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLLSAI2_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLLSAI2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
/**
* @brief MCO divider clock frequency.
*/

1
os/hal/ports/STM32/STM32L5xx/platform.mk
View File

@ -27,6 +27,7 @@ endif
# Drivers compatible with the platform.
include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk

16
os/hal/ports/STM32/STM32L5xx/stm32_registry.h
View File

@ -77,6 +77,22 @@
#if defined(STM32L552xx) || defined(__DOXYGEN__)
/* RCC attributes.*/
#define STM32_HAS_PLL TRUE
#define STM32_PLL_HAS_P TRUE
#define STM32_PLL_HAS_Q TRUE
#define STM32_PLL_HAS_R TRUE
#define STM32_HAS_PLLSAI1 TRUE
#define STM32_PLLSAI1_HAS_P TRUE
#define STM32_PLLSAI1_HAS_Q TRUE
#define STM32_PLLSAI1_HAS_R TRUE
#define STM32_HAS_PLLSAI2 TRUE
#define STM32_PLLSAI2_HAS_P TRUE
#define STM32_PLLSAI2_HAS_Q FALSE
#define STM32_PLLSAI2_HAS_R FALSE
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE