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Enabled ARM cycle counter 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11246 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
edolomb 2018-01-10 09:31:05 +00:00
parent e669bfa7e6
commit 0da6de11ee
1 changed files with 9 additions and 0 deletions
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9
os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S
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@ -85,6 +85,15 @@ Boot_Handler:
bic r0, r0, #0x1
ldr r1, =SFR_L2CC_HRAMC
str r0, [r1]
/*
* Enabling Cycle counter
*/
mrc p15, 0, r0, c9, c12, 0 // read PMCR register
orr r0, r0, #(0x1) // set E bit 0 to enable counter
mcr p15, 0, r0, c9, c12, 0 // write r0
mrc p15, 0, r0, c9, c12, 1 // read PMCNTENSET register
orr r0, r0, #(0x1 << 31) // set bit 31 to enable counter
mcr p15, 0, r0, c9, c12, 1 // write r0
/*
* Configure the intial catching of the interrupts
*/