diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c index c236ddeb8..8bcc21085 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -114,9 +114,12 @@ static void hal_lld_backup_domain_init(void) { void hal_lld_init(void) { /* Reset of all peripherals. AHB3 is not reseted because it could have - been initialized in the board initialization file (board.c).*/ + been initialized in the board initialization file (board.c) and AHB2 is not + present in STM32F410. */ rccResetAHB1(~0); +#if !defined(STM32F410xx) rccResetAHB2(~0); +#endif rccResetAPB1(~RCC_APB1RSTR_PWRRST); rccResetAPB2(~0); @@ -147,7 +150,11 @@ void stm32_clock_init(void) { #if !STM32_NO_INIT /* PWR clock enable.*/ +#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCAPBEN) + RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCAPBEN; +#else RCC->APB1ENR = RCC_APB1ENR_PWREN; +#endif /* PWR initialization.*/ #if defined(STM32F4XX) || defined(__DOXYGEN__) @@ -173,7 +180,7 @@ void stm32_clock_init(void) { /* Registers finally cleared to reset values.*/ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ RCC->CFGR = 0; /* CFGR reset value. */ - + #if STM32_HSE_ENABLED /* HSE activation.*/ #if defined(STM32_HSE_BYPASS) @@ -220,35 +227,73 @@ void stm32_clock_init(void) { /* Waiting for PLL lock.*/ while (!(RCC->CR & RCC_CR_PLLRDY)) ; -#endif /* STM32_OVERDRIVE_REQUIRED */ +#endif /* STM32_ACTIVATE_PLL */ #if STM32_ACTIVATE_PLLI2S /* PLLI2S activation.*/ - RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; + RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP | + STM32_PLLI2SQ | STM32_PLLI2SM; RCC->CR |= RCC_CR_PLLI2SON; /* Waiting for PLL lock.*/ while (!(RCC->CR & RCC_CR_PLLI2SRDY)) ; -#endif +#endif /* STM32_ACTIVATE_PLLI2S */ #if STM32_ACTIVATE_PLLSAI /* PLLSAI activation.*/ - RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ; + RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP | + STM32_PLLSAIQ | STM32_PLLSAIM; RCC->CR |= RCC_CR_PLLSAION; /* Waiting for PLL lock.*/ while (!(RCC->CR & RCC_CR_PLLSAIRDY)) ; -#endif +#endif /* STM32_ACTIVATE_PLLSAI */ /* Other clock-related settings (dividers, MCO etc).*/ RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL | STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#if defined(STM32F446xx) + /* DCKCFGR register initialization, note, must take care of the _OFF + pseudo settings.*/ + { + uint32_t dckcfgr = 0; +#if STM32_SAI2SEL != STM32_SAI2SEL_OFF + dckcfgr |= STM32_SAI2SEL; +#endif +#if STM32_SAI1SEL != STM32_SAI1SEL_OFF + dckcfgr |= STM32_SAI1SEL; +#endif +#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF + dckcfgr |= STM32_PLLSAIDIVR; +#endif + RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ; + } + RCC->DCKCFGR2 = STM32_CK48MSEL; +#elif defined(STM32F469xx) || defined(STM32F479xx) + /* DCKCFGR register initialization, note, must take care of the _OFF + pseudo settings.*/ + { + uint32_t dckcfgr = 0; + #if STM32_SAI2SEL != STM32_SAI2SEL_OFF + dckcfgr |= STM32_SAI2SEL; + #endif + #if STM32_SAI1SEL != STM32_SAI1SEL_OFF + dckcfgr |= STM32_SAI1SEL; + #endif + #if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF + dckcfgr |= STM32_PLLSAIDIVR; + #endif + RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ | + STM32_CK48MSEL; + } +#endif + /* Flash setup.*/ -#if defined(STM32_USE_REVISION_A_FIX) +#if !defined(STM32_REMOVE_REVISION_A_FIX) /* Some old revisions of F4x MCUs randomly crashes with compiler optimizations enabled AND flash caches enabled. */ if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241)) diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index 877f75698..e9ce800b4 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -26,22 +26,22 @@ * - STM32_VDD (as hundredths of Volt). * . * One of the following macros must also be defined: - * - STM32F2XX for High-performance STM32 F-2 devices. - * - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx for - * High-performance STM32 F-4 devices. - * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx for - * High-performance STM32 F-4 devices. - * - STM32F401xC, STM32F401xE for High-performance STM32 F-4 devices. - * - STM32F411xE for High-performance STM32 F-4 devices. - * - STM32F446xx for High-performance STM32 F-4 devices. + * - STM32F2XX for High-performance STM32F2 devices. + * - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, + * STM32F446xx for High-performance STM32F4 devices of + * Foundation line. + * - STM32F401xC, STM32F401xE, STM32F410Cx, STM32F410Rx, STM32F411xE + * for High-performance STM32F4 devices of Access line. + * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx, + * STM32F479xx for High-performance STM32F4 devices of Advanced line. * . * * @addtogroup HAL * @{ */ -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ +#ifndef HAL_LLD_H +#define HAL_LLD_H #include "stm32_registry.h" @@ -52,17 +52,50 @@ /** * @brief Defines the support for realtime counters in the HAL. */ -#define HAL_IMPLEMENTS_COUNTERS TRUE +#define HAL_IMPLEMENTS_COUNTERS TRUE /** * @name Platform identification macros * @{ */ -#if defined(STM32F439xx) || defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU" +#if defined(STM32F205xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F205 High Performance" -#elif defined(STM32F446xx) -#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU" +#elif defined(STM32F207xx) +#define PLATFORM_NAME "STM32F207 High Performance" + +#elif defined(STM32F215xx) +#define PLATFORM_NAME "STM32F215 High Performance" + +#elif defined(STM32F217xx) +#define PLATFORM_NAME "STM32F217 High Performance" + +#elif defined(STM32F401xx) +#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU" + +#elif defined(STM32F405xx) +#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU" + +#elif defined(STM32F407xx) +#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU" + +#elif defined(STM32F410xx) +#define PLATFORM_NAME "STM32F410 High Performance with DSP and FPU" + +#elif defined(STM32F411xx) +#define PLATFORM_NAME "STM32F411 High Performance with DSP and FPU" + +#elif defined(STM32F412xx) +#define PLATFORM_NAME "STM32F412 High Performance with DSP and FPU" + +#elif defined(STM32F415xx) +#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU" + +#elif defined(STM32F417xx) +#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU" + +#elif defined(STM32F427xx) +#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU" #elif defined(STM32F429xx) #define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU" @@ -70,41 +103,17 @@ #elif defined(STM32F437xx) #define PLATFORM_NAME "STM32F437 High Performance with DSP and FPU" -#elif defined(STM32F427xx) -#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU" +#elif defined(STM32F439xx) +#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU" -#elif defined(STM32F405xx) -#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU" +#elif defined(STM32F446xx) +#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU" -#elif defined(STM32F415xx) -#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU" +#elif defined(STM32F469xx) +#define PLATFORM_NAME "STM32F469 High Performance with DSP and FPU" -#elif defined(STM32F407xx) -#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU" - -#elif defined(STM32F417xx) -#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU" - -#elif defined(STM32F401xC) -#define PLATFORM_NAME "STM32F401xC High Performance with DSP and FPU" - -#elif defined(STM32F401xE) -#define PLATFORM_NAME "STM32F401xE High Performance with DSP and FPU" - -#elif defined(STM32F411xE) -#define PLATFORM_NAME "STM32F411xE High Performance with DSP and FPU" - -#elif defined(STM32F205xx) -#define PLATFORM_NAME "STM32F205 High Performance" - -#elif defined(STM32F215xx) -#define PLATFORM_NAME "STM32F215 High Performance" - -#elif defined(STM32F207xx) -#define PLATFORM_NAME "STM32F207 High Performance" - -#elif defined(STM32F217xx) -#define PLATFORM_NAME "STM32F217 High Performance" +#elif defined(STM32F479xx) +#define PLATFORM_NAME "STM32F479 High Performance with DSP and FPU" #else #error "STM32F2xx/F4xx device not specified" @@ -117,7 +126,7 @@ */ #if defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F446xx) || defined(__DOXYGEN__) + defined(STM32F469xx) || defined(STM32F479xx) || defined(__DOXYGEN__) /** * @brief Absolute maximum system clock. */ @@ -188,10 +197,20 @@ */ #define STM32_PLLOUT_MIN 24000000 +/** + * @brief Maximum PLLI2S output clock frequency. + */ +#define STM32_PLLI2SOUT_MAX 216000000 + +/** + * @brief Maximum PLLSAI output clock frequency. + */ +#define STM32_PLLSAIOUT_MAX 216000000 + /** * @brief Maximum APB1 clock frequency. */ -#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX /4) +#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4) /** * @brief Maximum APB2 clock frequency. @@ -204,7 +223,7 @@ #define STM32_SPII2S_MAX 45000000 #endif -#if defined(STM32F40_41xxx) || defined(__DOXYGEN__) +#if defined(STM32F40_41xxx) #define STM32_SYSCLK_MAX 168000000 #define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_BYP_MAX 50000000 @@ -224,7 +243,7 @@ #define STM32_SPII2S_MAX 42000000 #endif -#if defined(STM32F401xx) || defined(__DOXYGEN__) +#if defined(STM32F401xx) #define STM32_SYSCLK_MAX 84000000 #define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_BYP_MAX 50000000 @@ -244,7 +263,8 @@ #define STM32_SPII2S_MAX 42000000 #endif -#if defined(STM32F411xx) +#if defined(STM32F410xx) || defined(STM32F411xx) || \ + defined(STM32F412xx) #define STM32_SYSCLK_MAX 100000000 #define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_BYP_MAX 50000000 @@ -264,6 +284,28 @@ #define STM32_SPII2S_MAX 50000000 #endif +#if defined(STM32F446xx) +#define STM32_SYSCLK_MAX 180000000 +#define STM32_HSECLK_MAX 26000000 +#define STM32_HSECLK_BYP_MAX 50000000 +#define STM32_HSECLK_MIN 4000000 +#define STM32_HSECLK_BYP_MIN 1000000 +#define STM32_LSECLK_MAX 32768 +#define STM32_LSECLK_BYP_MAX 1000000 +#define STM32_LSECLK_MIN 32768 +#define STM32_PLLIN_MAX 2100000 +#define STM32_PLLIN_MIN 950000 +#define STM32_PLLVCO_MAX 432000000 +#define STM32_PLLVCO_MIN 100000000 +#define STM32_PLLOUT_MAX 180000000 +#define STM32_PLLOUT_MIN 12500000 +#define STM32_PLLI2SOUT_MAX 216000000 +#define STM32_PLLSAIOUT_MAX 216000000 +#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4) +#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2) +#define STM32_SPII2S_MAX 45000000 +#endif + #if defined(STM32F2XX) #define STM32_SYSCLK_MAX 120000000 #define STM32_HSECLK_MAX 26000000 @@ -395,10 +437,32 @@ * @name RCC_PLLI2SCFGR register bits definitions * @{ */ +#define STM32_PLLI2SM_MASK (31 << 0) /**< PLLI2SM mask. */ #define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ +#define STM32_PLLI2SP_MASK (3 << 16) /**< PLLI2SP mask. */ +#define STM32_PLLI2SP_DIV2 (0 << 16) /**< PLLI2S clock divided by 2. */ +#define STM32_PLLI2SP_DIV4 (1 << 16) /**< PLLI2S clock divided by 4. */ +#define STM32_PLLI2SP_DIV6 (2 << 16) /**< PLLI2S clock divided by 6. */ +#define STM32_PLLI2SP_DIV8 (3 << 16) /**< PLLI2S clock divided by 8. */ +#define STM32_PLLI2SQ_MASK (15 << 24) /**< PLLI2SQ mask. */ #define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ /** @} */ +/** + * @name RCC_PLLSAICFGR register bits definitions + * @{ + */ +#define STM32_PLLSAIM_MASK (31 << 0) /**< PLLSAIM mask. */ +#define STM32_PLLSAIN_MASK (511 << 6) /**< PLLSAIN mask. */ +#define STM32_PLLSAIP_MASK (3 << 16) /**< PLLSAIP mask. */ +#define STM32_PLLSAIP_DIV2 (0 << 16) /**< PLLSAI clock divided by 2. */ +#define STM32_PLLSAIP_DIV4 (1 << 16) /**< PLLSAI clock divided by 4. */ +#define STM32_PLLSAIP_DIV6 (2 << 16) /**< PLLSAI clock divided by 6. */ +#define STM32_PLLSAIP_DIV8 (3 << 16) /**< PLLSAI clock divided by 8. */ +#define STM32_PLLSAIQ_MASK (15 << 24) /**< PLLSAIQ mask. */ +#define STM32_PLLSAIR_MASK (7 << 28) /**< PLLSAIR mask. */ +/** @} */ + /** * @name RCC_BDCR register bits definitions * @{ @@ -410,6 +474,80 @@ #define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ /** @} */ +/** + * @name RCC_DCKCFGR register bits definitions + * @{ + */ +#define STM32_PLLI2SDIVQ_MASK (31 << 0) /**< PLLI2SDIVQ mask. */ + +#define STM32_PLLSAIDIVQ_MASK (31 << 8) /**< PLLSAIDIVQ mask. */ + +#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */ +#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */ +#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */ +#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */ +#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/ +#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */ + +#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */ +#define STM32_SAI1SEL_PLLSAI (0 << 20) /**< SAI1 source is PLLSAI. */ +#define STM32_SAI1SEL_PLLI2S (1 << 20) /**< SAI1 source is PLLI2S. */ +#define STM32_SAI1SEL_PLLR (2 << 20) /**< SAI1 source is PLLR. */ +#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/ + +#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */ +#define STM32_SAI2SEL_PLLSAI (0 << 22) /**< SAI2 source is PLLSAI. */ +#define STM32_SAI2SEL_PLLI2S (1 << 22) /**< SAI2 source is PLLI2S. */ +#define STM32_SAI2SEL_PLLR (2 << 22) /**< SAI2 source is PLLR. */ +#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/ + +#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */ +#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */ +#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */ + +#define STM32_I2S1SEL_MASK (3 << 25) /**< I2S1SEL mask. */ +#define STM32_I2S1SEL_PLLR (0 << 25) /**< I2S1 source is PLLR. */ +#define STM32_I2S1SEL_AFIN (1 << 25) /**< I2S1 source is AF Input. */ +#define STM32_I2S1SEL_MCO1 (2 << 25) /**< I2S1 source is MCO1. */ +#define STM32_I2S1SEL_OFF 0xFFFFFFFFU /**< I2S1 clock is not required.*/ + +#define STM32_I2S2SEL_MASK (3 << 27) /**< I2S2SEL mask. */ +#define STM32_I2S2SEL_PLLR (0 << 27) /**< I2S2 source is PLLR. */ +#define STM32_I2S2SEL_AFIN (1 << 27) /**< I2S2 source is AF Input. */ +#define STM32_I2S2SEL_MCO1 (2 << 27) /**< I2S2 source is MCO1. */ +#define STM32_I2S2SEL_OFF 0xFFFFFFFFU /**< I2S2 clock is not required.*/ + +#define STM32_DSISEL_MASK (1 << 28) /**< DSISEL mask. */ +#define STM32_DSISEL_PHY (0 << 28) /**< DSI source is DSI-PSY. */ +#define STM32_DSISEL_PLLR (1 << 28) /**< DSI source is PLLR. */ +/** @} */ + +/** + * @name RCC_DCKCFGR2 register bits definitions + * @{ + */ +#define STM32_I2C1SEL_MASK (3 << 22) /**< I2C1SEL mask. */ +#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is PCLK1. */ +#define STM32_I2C1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */ +#define STM32_I2C1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */ + +#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */ +#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */ +#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */ + +#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */ +#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */ +#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */ + +#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */ +#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */ +#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */ + +#define STM32_SPDIFSEL_MASK (1 << 29) /**< SPDIFSEL mask. */ +#define STM32_SPDIFSEL_PLLI2S (0 << 29) /**< SPDIF source is PLLI2S. */ +#define STM32_SPDIFSEL_PLL (1 << 29) /**< SPDIF source is PLL. */ +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -597,6 +735,156 @@ #endif #endif /* !defined(STM32F4XX) */ +/** + * @brief I2S clock source. + */ +#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#endif + +/** + * @brief PLLI2SN multiplier value. + * @note The allowed values are 192..432, except for + * STM32F446 where values are 50...432. + * @note The default value is calculated for a 96MHz I2S clock + * output from an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SN_VALUE 192 +#endif + +/** + * @brief PLLI2SM divider value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 96MHz I2S clock + * output from an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SM_VALUE 4 +#endif + +/** + * @brief PLLI2SR divider value. + * @note The allowed values are 2..7. + * @note The default value is calculated for a 96MHz I2S clock + * output from an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SR_VALUE 4 +#endif + +/** + * @brief PLLI2SP divider value. + * @note The allowed values are 2, 4, 6 and 8. + */ +#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SP_VALUE 4 +#endif + +/** + * @brief PLLI2SQ divider value. + * @note The allowed values are 2..15. + */ +#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SQ_VALUE 4 +#endif + +/** + * @brief STM32_PLLI2SDIVQ divider value (SAI clock divider). + */ +#if !defined(STM32_PLLI2SDIVQ) || defined(__DOXYGEN__) +#define STM32_PLLI2SDIVQ 0 +#endif + +/** + * @brief PLLSAIM value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 96MHz SAI clock + * output from an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIM_VALUE 4 +#endif + +/** + * @brief PLLSAIN value. + * @note The allowed values are 50..432. + * @note The default value is calculated for a 96MHz SAI clock + * output from an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIN_VALUE 192 +#endif + +/** + * @brief PLLSAIM value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 96MHz SAI clock + * output from an external 8MHz HSE clock. + */ +#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIM_VALUE 4 +#endif + +/** + * @brief PLLSAIR value. + * @note The allowed values are 2..7. + */ +#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIR_VALUE 4 +#endif + +/** + * @brief PLLSAIP divider value. + * @note The allowed values are 2, 4, 6 and 8. + */ +#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIP_VALUE 8 +#endif + +/** + * @brief PLLSAIQ value. + * @note The allowed values are 2..15. + */ +#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIQ_VALUE 4 +#endif + +/** + * @brief PLLSAIDIVR divider value (SAI clock divider). + */ +#if !defined(STM32_PLLSAIDIVR) || defined(__DOXYGEN__) +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#endif + +/** + * @brief PLLSAIDIVR divider value (LCD clock divider). + */ +#if !defined(STM32_PLLSAIDIVQ) || defined(__DOXYGEN__) +#define STM32_PLLSAIDIVQ 0 +#endif + +/** + * @brief SAI1SEL value (SAI1 clock source). + */ +#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__) +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#endif + +/** + * @brief SAI2SEL value (SAI2 clock source). + */ +#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__) +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#endif + +/** + * @brief PLL48CLK clock source. + */ +#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__) +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#endif + /** * @brief AHB prescaler value. */ @@ -663,53 +951,6 @@ #if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #endif - -/** - * @brief I2S clock source. - */ -#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) -#define STM32_I2SSRC STM32_I2SSRC_CKIN -#endif - -/** - * @brief PLLI2SN multiplier value. - * @note The allowed values are 192..432. - */ -#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLI2SN_VALUE 192 -#endif - -/** - * @brief PLLI2SR multiplier value. - * @note The allowed values are 2..7. - */ -#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLI2SR_VALUE 5 -#endif - -/** - * @brief PLLSAIQ value. - * @note The allowed values are 2..15. - */ -#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAIQ_VALUE 8 -#endif - -/** - * @brief PLLSAIQ value. - * @note The allowed values are 49..432. - */ -#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAIN_VALUE 120 -#endif - -/** - * @brief PLLSAIQ value. - * @note The allowed values are 2..7. - */ -#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLSAIR_VALUE 4 -#endif /** @} */ /*===========================================================================*/ @@ -739,7 +980,7 @@ */ #if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ defined(STM32F40_41xxx) || defined(STM32F446xx) || \ - defined(__DOXYGEN__) + defined(STM32F469_479xx) || defined(__DOXYGEN__) #if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) #define STM32_0WS_THRESHOLD 30000000 #define STM32_1WS_THRESHOLD 60000000 @@ -829,7 +1070,7 @@ #error "invalid VDD voltage specified" #endif -#elif defined(STM32F411xx) +#elif defined(STM32F410xx) || defined(STM32F411xx) #if (STM32_VDD >= 270) && (STM32_VDD <= 360) #define STM32_0WS_THRESHOLD 30000000 #define STM32_1WS_THRESHOLD 64000000 @@ -945,6 +1186,17 @@ #error "HSI not enabled, required by STM32_I2SSRC" #endif +#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \ + (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SAI1SEL" +#endif + +#if ((STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \ + (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SAI2SEL" +#endif #endif /* !STM32_HSI_ENABLED */ /* @@ -954,10 +1206,17 @@ #if STM32_HSECLK == 0 #error "HSE frequency not defined" -#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#else /* STM32_HSECLK != 0 */ +#if defined(STM32_HSE_BYPASS) +#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)" +#endif +#else /* !defined(STM32_HSE_BYPASS) */ +#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" #endif - +#endif /* !defined(STM32_HSE_BYPASS) */ +#endif /* STM32_HSECLK != 0 */ #else /* !STM32_HSE_ENABLED */ #if STM32_SW == STM32_SW_HSE @@ -1035,7 +1294,7 @@ #endif /** - * @brief PLLs input clock frequency. + * @brief PLL input clock frequency. */ #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) #define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) @@ -1082,13 +1341,13 @@ * @brief STM32_PLLP field. */ #if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) -#define STM32_PLLP (0 << 16) +#define STM32_PLLP STM32_PLLP_DIV2 #elif STM32_PLLP_VALUE == 4 -#define STM32_PLLP (1 << 16) +#define STM32_PLLP STM32_PLLP_DIV4 #elif STM32_PLLP_VALUE == 6 -#define STM32_PLLP (2 << 16) +#define STM32_PLLP STM32_PLLP_DIV6 #elif STM32_PLLP_VALUE == 8 -#define STM32_PLLP (3 << 16) +#define STM32_PLLP STM32_PLLP_DIV8 #else #error "invalid STM32_PLLP_VALUE value specified" #endif @@ -1149,7 +1408,8 @@ /* Calculating VOS settings, it is different for each sub-platform.*/ #if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(STM32F446xx) || defined(__DOXYGEN__) + defined(STM32F446xx) || defined(STM32F469_479xx) || \ + defined(__DOXYGEN__) #if STM32_SYSCLK <= 120000000 #define STM32_VOS STM32_VOS_SCALE3 #define STM32_OVERDRIVE_REQUIRED FALSE @@ -1180,7 +1440,7 @@ #endif #define STM32_OVERDRIVE_REQUIRED FALSE -#elif defined(STM32F411xx) +#elif defined(STM32F410xx) || defined(STM32F411xx) || defined(STM32F412xx) #if STM32_SYSCLK <= 64000000 #define STM32_VOS STM32_VOS_SCALE3 #elif STM32_SYSCLK <= 84000000 @@ -1277,7 +1537,10 @@ /* * PLLI2S enable check. */ -#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__) +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \ + (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \ + (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S) || \ + defined(__DOXYGEN__) /** * @brief PLLI2S activation flag. */ @@ -1286,15 +1549,59 @@ #define STM32_ACTIVATE_PLLI2S FALSE #endif +/** + * @brief STM32_PLLI2SM field. + */ +#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SM (STM32_PLLI2SM_VALUE << 0) +#else +#error "invalid STM32_PLLI2SM_VALUE value specified" +#endif + /** * @brief STM32_PLLI2SN field. */ +#if defined (STM32F446xx) || defined(__DOXYGEN__) +#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) +#else +#error "invalid STM32_PLLI2SN_VALUE value specified" +#endif +#else /* !defined(STM32F446xx) */ #if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \ defined(__DOXYGEN__) #define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) #else #error "invalid STM32_PLLI2SN_VALUE value specified" #endif +#endif /* defined(STM32F446xx) */ + +/** + * @brief STM32_PLLI2SP field. + */ +#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLI2SP STM32_PLLI2SP_DIV2 +#elif STM32_PLLI2SP_VALUE == 4 +#define STM32_PLLI2SP STM32_PLLI2SP_DIV4 +#elif STM32_PLLI2SP_VALUE == 6 +#define STM32_PLLI2SP STM32_PLLI2SP_DIV6 +#elif STM32_PLLI2SP_VALUE == 8 +#define STM32_PLLI2SP STM32_PLLI2SP_DIV8 +#else +#error "invalid STM32_PLLI2SP_VALUE value specified" +#endif + +/** + * @brief STM32_PLLI2SQ field. + */ +#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24) +#else +#error "invalid STM32_PLLI2SQ_VALUE value specified" +#endif /** * @brief STM32_PLLI2SR field. @@ -1306,10 +1613,80 @@ #error "invalid STM32_PLLI2SR_VALUE value specified" #endif +/** + * @brief PLLI2S input clock frequency. + */ +#if defined(STM32F446xx) +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLI2SCLKIN (STM32_HSECLK / STM32_PLLI2SM_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLI2SCLKIN (STM32_HSICLK / STM32_PLLI2SM_VALUE) +#else +#error "invalid STM32_PLLSRC value specified" +#endif +#else /* !defined(STM32F446xx) */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLI2SCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLI2SCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) +#else +#error "invalid STM32_PLLSRC value specified" +#endif +#endif /* defined(STM32F446xx) */ + +/** + * @brief PLLI2S VCO frequency. + */ +#define STM32_PLLI2SVCO (STM32_PLLI2SCLKIN * STM32_PLLI2SN_VALUE) + +/* + * PLLI2S VCO frequency range check. + */ +#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ + (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLLI2S P output clock frequency. + */ +#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE) + +/** + * @brief PLLI2S Q output clock frequency. + */ +#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE) + +/** + * @brief PLLI2S R output clock frequency. + */ +#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE) + +/* + * PLLSAI enable check. + */ +#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \ + (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \ + (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \ + (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) || \ + defined(__DOXYGEN__) /** * @brief PLLSAI activation flag. */ +#define STM32_ACTIVATE_PLLSAI TRUE +#else #define STM32_ACTIVATE_PLLSAI FALSE +#endif + +/** + * @brief STM32_PLLSAIM field. + */ +#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0) +#else +#error "invalid STM32_PLLSAIM_VALUE value specified" +#endif /** * @brief STM32_PLLSAIN field. @@ -1328,7 +1705,7 @@ defined(__DOXYGEN__) #define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24) #else -#error "invalid STM32_PLLSAIR_VALUE value specified" +#error "invalid STM32_PLLSAIQ_VALUE value specified" #endif /** @@ -1342,34 +1719,89 @@ #endif /** - * @brief PLL VCO frequency. + * @brief STM32_PLLSAIP field. */ -#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE) -/* - * PLLI2S VCO frequency range check. - */ -#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ - (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) -#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLSAIP STM32_PLLSAIP_DIV2 + +#elif STM32_PLLSAIP_VALUE == 4 +#define STM32_PLLSAIP STM32_PLLSAIP_DIV4 + +#elif STM32_PLLSAIP_VALUE == 6 +#define STM32_PLLSAIP STM32_PLLSAIP_DIV6 + +#elif STM32_PLLSAIP_VALUE == 8 +#define STM32_PLLSAIP STM32_PLLSAIP_DIV8 + +#else +#error "invalid STM32_PLLSAIP_VALUE value specified" #endif /** - * @brief PLLI2S output clock frequency. + * @brief PLLSAI input clock frequency. */ -#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE) +#if defined(STM32F446xx) +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLSAIM_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLSAIM_VALUE) +#else +#error "invalid STM32_PLLSRC value specified" +#endif +#else /* !defined(STM32F446xx) */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLM_VALUE) +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLM_VALUE) +#else +#error "invalid STM32_PLLSRC value specified" +#endif +#endif /* defined(STM32F446xx) */ + +/** + * @brief PLLSAI VCO frequency. + */ +#define STM32_PLLSAIVCO (STM32_PLLSAICLKIN * STM32_PLLSAIN_VALUE) + +/* + * PLLSAI VCO frequency range check. + */ +#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \ + (STM32_PLLSAIVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLLSAI P output clock frequency. + */ +#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE) + +/** + * @brief PLLSAI Q output clock frequency. + */ +#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE) + +/** + * @brief PLLSAI R output clock frequency. + */ +#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE) /** * @brief MCO1 divider clock. */ #if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__) #define STM32_MCO1DIVCLK STM32_HSICLK + #elif STM32_MCO1SEL == STM32_MCO1SEL_LSE #define STM32_MCO1DIVCLK STM32_LSECLK + #elif STM32_MCO1SEL == STM32_MCO1SEL_HSE #define STM32_MCO1DIVCLK STM32_HSECLK + #elif STM32_MCO1SEL == STM32_MCO1SEL_PLL #define STM32_MCO1DIVCLK STM32_PLLCLKOUT + #else #error "invalid STM32_MCO1SEL value specified" #endif @@ -1379,14 +1811,19 @@ */ #if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__) #define STM32_MCO1CLK STM32_MCO1DIVCLK + #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2 #define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2) + #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3 #define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3) + #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4 #define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4) + #elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5 #define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5) + #else #error "invalid STM32_MCO1PRE value specified" #endif @@ -1396,12 +1833,16 @@ */ #if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__) #define STM32_MCO2DIVCLK STM32_HSECLK + #elif STM32_MCO2SEL == STM32_MCO2SEL_PLL #define STM32_MCO2DIVCLK STM32_PLLCLKOUT + #elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK #define STM32_MCO2DIVCLK STM32_SYSCLK + #elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S #define STM32_MCO2DIVCLK STM32_PLLI2S + #else #error "invalid STM32_MCO2SEL value specified" #endif @@ -1411,14 +1852,19 @@ */ #if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__) #define STM32_MCO2CLK STM32_MCO2DIVCLK + #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2 #define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2) + #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3 #define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3) + #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4 #define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4) + #elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5 #define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5) + #else #error "invalid STM32_MCO2PRE value specified" #endif @@ -1448,12 +1894,16 @@ */ #if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) #define STM32_RTCCLK 0 + #elif STM32_RTCSEL == STM32_RTCSEL_LSE #define STM32_RTCCLK STM32_LSECLK + #elif STM32_RTCSEL == STM32_RTCSEL_LSI #define STM32_RTCCLK STM32_LSICLK + #elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV #define STM32_RTCCLK STM32_HSEDIVCLK + #else #error "invalid STM32_RTCSEL value specified" #endif @@ -1462,10 +1912,16 @@ * @brief 48MHz frequency. */ #if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__) +#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__) #define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) +#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI +#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE) #else -#define STM32_PLL48CLK 0 +#error "invalid source selected for PLL48CLK clock" #endif +#else /* !STM32_CLOCK48_REQUIRED */ +#define STM32_PLL48CLK 0 +#endif /* !STM32_CLOCK48_REQUIRED */ /** * @brief Clock of timers connected to APB1 @@ -1547,6 +2003,6 @@ extern "C" { } #endif -#endif /* _HAL_LLD_H_ */ +#endif /* HAL_LLD_H */ /** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index a9a3e4721..f497dd143 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -22,10 +22,14 @@ * @{ */ -#ifndef _STM32_REGISTRY_H_ -#define _STM32_REGISTRY_H_ +#ifndef STM32_REGISTRY_H +#define STM32_REGISTRY_H -#if defined(STM32F446xx) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define STM32F469_479xx +#define STM32F4XX + +#elif defined(STM32F446xx) #define STM32F4XX #elif defined(STM32F439xx) || defined(STM32F429xx) @@ -36,6 +40,20 @@ #define STM32F427_437xx #define STM32F4XX +#elif defined(STM32F412Cx) || defined(STM32F412Rx) || \ + defined(STM32F412Vx) || defined(STM32F412Zx) +#define STM32F412xx +#define STM32F4XX + +#elif defined(STM32F411xE) +#define STM32F411xx +#define STM32F4XX + +#elif defined(STM32F410Cx) || defined(STM32F410Rx) || \ + defined(STM32F410Tx) +#define STM32F410xx +#define STM32F4XX + #elif defined(STM32F405xx) || defined(STM32F415xx) || \ defined(STM32F407xx) || defined(STM32F417xx) #define STM32F40_41xxx @@ -45,10 +63,6 @@ #define STM32F401xx #define STM32F4XX -#elif defined(STM32F411xE) -#define STM32F411xx -#define STM32F4XX - #elif defined(STM32F205xx) || defined(STM32F215xx) || \ defined(STM32F207xx) || defined(STM32F217xx) #define STM32F2XX @@ -67,9 +81,11 @@ */ /*===========================================================================*/ -/* STM32F446xx. */ +/* STM32F469xx, STM32F479xx. */ /*===========================================================================*/ -#if defined(STM32F446xx) + +#if defined(STM32F469_479xx) || defined(__DOXYGEN__) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -98,6 +114,7 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 TRUE +#define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -168,6 +185,377 @@ #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOI TRUE +#define STM32_HAS_GPIOJ TRUE +#define STM32_HAS_GPIOK TRUE + +#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ + RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | \ + RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | \ + RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | \ + RCC_AHB1ENR_GPIOHEN | \ + RCC_AHB1ENR_GPIOIEN | \ + RCC_AHB1ENR_GPIOJEN | \ + RCC_AHB1ENR_GPIOKEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 + +#define STM32_HAS_I2C4 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 TRUE +#define STM32_QUADSPI1_HANDLER Vector1AC +#define STM32_QUADSPI1_NUMBER 91 +#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_QUADSPI1_DMA_CHN 0x30000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE +#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SDC_SDIO_DMA_CHN 0x04004000 + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_SPI4_RX_DMA_CHN 0x00005004 +#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI4_TX_DMA_CHN 0x00050040 + +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE +#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI5_RX_DMA_CHN 0x00702000 +#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SPI5_TX_DMA_CHN 0x07020000 + +#define STM32_HAS_SPI6 TRUE +#define STM32_SPI6_SUPPORTS_I2S FALSE +#define STM32_SPI6_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 6) +#define STM32_SPI6_RX_DMA_CHN 0x01000000 +#define STM32_SPI6_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5) +#define STM32_SPI6_TX_DMA_CHN 0x00100000 + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 4 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 4 + +#define STM32_HAS_TIM9 TRUE +#define STM32_TIM9_IS_32BITS FALSE +#define STM32_TIM9_CHANNELS 2 + +#define STM32_HAS_TIM10 TRUE +#define STM32_TIM10_IS_32BITS FALSE +#define STM32_TIM10_CHANNELS 1 + +#define STM32_HAS_TIM11 TRUE +#define STM32_TIM11_IS_32BITS FALSE +#define STM32_TIM11_CHANNELS 1 + +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 + +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 1 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 + +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) +#define STM32_USART3_RX_DMA_CHN 0x00000040 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x00074000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_UART4_RX_DMA_CHN 0x00000400 +#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_UART4_TX_DMA_CHN 0x00040000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) +#define STM32_UART5_RX_DMA_CHN 0x00000004 +#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_UART5_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +#define STM32_HAS_UART7 TRUE +#define STM32_UART7_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_UART7_RX_DMA_CHN 0x00004000 +#define STM32_UART7_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) +#define STM32_UART7_TX_DMA_CHN 0x00000050 + +#define STM32_HAS_UART8 TRUE +#define STM32_UART8_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_UART8_RX_DMA_CHN 0x05000000 +#define STM32_UART8_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) +#define STM32_UART8_TX_DMA_CHN 0x00000005 +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_OTG_STEPPING 2 +#define STM32_HAS_OTG1 TRUE +#define STM32_OTG1_ENDPOINTS 5 +#define STM32_HAS_OTG2 TRUE +#define STM32_OTG2_ENDPOINTS 7 + +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED FALSE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC TRUE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D TRUE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC TRUE +#define STM32_FSMC_IS_FMC TRUE +#define STM32_FSMC_HANDLER Vector100 +#define STM32_FSMC_NUMBER 48 + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE FALSE + +#endif /* defined(STM32F469_479xx) */ + +/*===========================================================================*/ +/* STM32F446xx. */ +/*===========================================================================*/ + +#if defined(STM32F446xx) + +/* ADC attributes.*/ +#define STM32_ADC_HANDLER Vector88 +#define STM32_ADC_NUMBER 18 + +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00001100 + +#define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_ADC3_DMA_CHN 0x00000022 + +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_HAS_CAN3 FALSE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_DAC1_CH1_DMA_CHN 0x00700000 + +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_DAC1_CH2_DMA_CHN 0x07000000 + +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_CACHE_HANDLING FALSE + +#define STM32_HAS_DMA1 TRUE +#define STM32_DMA1_CH0_HANDLER Vector6C +#define STM32_DMA1_CH1_HANDLER Vector70 +#define STM32_DMA1_CH2_HANDLER Vector74 +#define STM32_DMA1_CH3_HANDLER Vector78 +#define STM32_DMA1_CH4_HANDLER Vector7C +#define STM32_DMA1_CH5_HANDLER Vector80 +#define STM32_DMA1_CH6_HANDLER Vector84 +#define STM32_DMA1_CH7_HANDLER VectorFC +#define STM32_DMA1_CH0_NUMBER 11 +#define STM32_DMA1_CH1_NUMBER 12 +#define STM32_DMA1_CH2_NUMBER 13 +#define STM32_DMA1_CH3_NUMBER 14 +#define STM32_DMA1_CH4_NUMBER 15 +#define STM32_DMA1_CH5_NUMBER 16 +#define STM32_DMA1_CH6_NUMBER 17 +#define STM32_DMA1_CH7_NUMBER 47 + +#define STM32_HAS_DMA2 TRUE +#define STM32_DMA2_CH0_HANDLER Vector120 +#define STM32_DMA2_CH1_HANDLER Vector124 +#define STM32_DMA2_CH2_HANDLER Vector128 +#define STM32_DMA2_CH3_HANDLER Vector12C +#define STM32_DMA2_CH4_HANDLER Vector130 +#define STM32_DMA2_CH5_HANDLER Vector150 +#define STM32_DMA2_CH6_HANDLER Vector154 +#define STM32_DMA2_CH7_HANDLER Vector158 +#define STM32_DMA2_CH0_NUMBER 56 +#define STM32_DMA2_CH1_NUMBER 57 +#define STM32_DMA2_CH2_NUMBER 58 +#define STM32_DMA2_CH3_NUMBER 59 +#define STM32_DMA2_CH4_NUMBER 60 +#define STM32_DMA2_CH5_NUMBER 68 +#define STM32_DMA2_CH6_NUMBER 69 +#define STM32_DMA2_CH7_NUMBER 70 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 23 +#define STM32_EXTI_IMR_MASK 0x00000000U + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE @@ -205,6 +593,13 @@ #define STM32_HAS_I2C4 FALSE +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 TRUE +#define STM32_QUADSPI1_HANDLER Vector1B0 +#define STM32_QUADSPI1_NUMBER 92 +#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_QUADSPI1_DMA_CHN 0x30000000 + /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE @@ -291,7 +686,7 @@ #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 +#define STM32_TIM8_CHANNELS 4 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE @@ -299,11 +694,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -311,11 +706,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -405,8 +800,9 @@ /*===========================================================================*/ /* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */ /*===========================================================================*/ -#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(__DOXYGEN__) + +#if defined(STM32F429_439xx) || defined(STM32F427_437xx) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -435,6 +831,7 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 TRUE +#define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -544,6 +941,9 @@ #define STM32_HAS_I2C4 FALSE +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE @@ -643,7 +1043,7 @@ #define STM32_HAS_TIM8 TRUE #define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 +#define STM32_TIM8_CHANNELS 4 #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE @@ -651,11 +1051,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -663,11 +1063,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -764,11 +1164,899 @@ #endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */ +/*===========================================================================*/ +/* STM32F412Cx, STM32F412Rx, STM32F412Vx, STM32F412Zx */ +/*===========================================================================*/ + +#if defined(STM32F412xx) + +/* ADC attributes.*/ +#define STM32_ADC_HANDLER Vector88 +#define STM32_ADC_NUMBER 18 + +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_HAS_CAN3 FALSE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_CACHE_HANDLING FALSE + +#define STM32_HAS_DMA1 TRUE +#define STM32_DMA1_CH0_HANDLER Vector6C +#define STM32_DMA1_CH1_HANDLER Vector70 +#define STM32_DMA1_CH2_HANDLER Vector74 +#define STM32_DMA1_CH3_HANDLER Vector78 +#define STM32_DMA1_CH4_HANDLER Vector7C +#define STM32_DMA1_CH5_HANDLER Vector80 +#define STM32_DMA1_CH6_HANDLER Vector84 +#define STM32_DMA1_CH7_HANDLER VectorFC +#define STM32_DMA1_CH0_NUMBER 11 +#define STM32_DMA1_CH1_NUMBER 12 +#define STM32_DMA1_CH2_NUMBER 13 +#define STM32_DMA1_CH3_NUMBER 14 +#define STM32_DMA1_CH4_NUMBER 15 +#define STM32_DMA1_CH5_NUMBER 16 +#define STM32_DMA1_CH6_NUMBER 17 +#define STM32_DMA1_CH7_NUMBER 47 + +#define STM32_HAS_DMA2 TRUE +#define STM32_DMA2_CH0_HANDLER Vector120 +#define STM32_DMA2_CH1_HANDLER Vector124 +#define STM32_DMA2_CH2_HANDLER Vector128 +#define STM32_DMA2_CH3_HANDLER Vector12C +#define STM32_DMA2_CH4_HANDLER Vector130 +#define STM32_DMA2_CH5_HANDLER Vector150 +#define STM32_DMA2_CH6_HANDLER Vector154 +#define STM32_DMA2_CH7_HANDLER Vector158 +#define STM32_DMA2_CH0_NUMBER 56 +#define STM32_DMA2_CH1_NUMBER 57 +#define STM32_DMA2_CH2_NUMBER 58 +#define STM32_DMA2_CH3_NUMBER 59 +#define STM32_DMA2_CH4_NUMBER 60 +#define STM32_DMA2_CH5_NUMBER 68 +#define STM32_DMA2_CH6_NUMBER 69 +#define STM32_DMA2_CH7_NUMBER 70 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 23 +#define STM32_EXTI_IMR_MASK 0x00000000U + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ + RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | \ + RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | \ + RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | \ + RCC_AHB1ENR_GPIOHEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 + +#define STM32_HAS_I2C4 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 TRUE +#define STM32_QUADSPI1_HANDLER Vector1B0 +#define STM32_QUADSPI1_NUMBER 92 +#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_QUADSPI1_DMA_CHN 0x30000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE +#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SDC_SDIO_DMA_CHN 0x04004000 + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 3))|\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI4_RX_DMA_CHN 0x00045004 +#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI4_TX_DMA_CHN 0x00050040 + +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE +#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI5_RX_DMA_CHN 0x00702000 +#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ + STM32_DMA_STREAM_ID_MSK(2, 5))|\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SPI5_TX_DMA_CHN 0x07520000 + +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 4 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM9 TRUE +#define STM32_TIM9_IS_32BITS FALSE +#define STM32_TIM9_CHANNELS 2 + +#define STM32_HAS_TIM10 TRUE +#define STM32_TIM10_IS_32BITS FALSE +#define STM32_TIM10_CHANNELS 1 + +#define STM32_HAS_TIM11 TRUE +#define STM32_TIM11_IS_32BITS FALSE +#define STM32_TIM11_CHANNELS 1 + +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 + +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 1 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 + +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) +#define STM32_USART3_RX_DMA_CHN 0x00000040 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x00074000 + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_OTG_STEPPING 1 +#define STM32_HAS_OTG1 TRUE +#define STM32_OTG1_ENDPOINTS 4 + +#define STM32_HAS_OTG2 FALSE +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED FALSE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE FALSE + +#endif /* defined(STM32F412xx) */ + +/*===========================================================================*/ +/* STM32F411xC, STM32F411xE */ +/*===========================================================================*/ + +#if defined(STM32F411xx) + +/* ADC attributes.*/ +#define STM32_ADC_HANDLER Vector88 +#define STM32_ADC_NUMBER 18 + +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_HAS_CAN3 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_CACHE_HANDLING FALSE + +#define STM32_HAS_DMA1 TRUE +#define STM32_DMA1_CH0_HANDLER Vector6C +#define STM32_DMA1_CH1_HANDLER Vector70 +#define STM32_DMA1_CH2_HANDLER Vector74 +#define STM32_DMA1_CH3_HANDLER Vector78 +#define STM32_DMA1_CH4_HANDLER Vector7C +#define STM32_DMA1_CH5_HANDLER Vector80 +#define STM32_DMA1_CH6_HANDLER Vector84 +#define STM32_DMA1_CH7_HANDLER VectorFC +#define STM32_DMA1_CH0_NUMBER 11 +#define STM32_DMA1_CH1_NUMBER 12 +#define STM32_DMA1_CH2_NUMBER 13 +#define STM32_DMA1_CH3_NUMBER 14 +#define STM32_DMA1_CH4_NUMBER 15 +#define STM32_DMA1_CH5_NUMBER 16 +#define STM32_DMA1_CH6_NUMBER 17 +#define STM32_DMA1_CH7_NUMBER 47 + +#define STM32_HAS_DMA2 TRUE +#define STM32_DMA2_CH0_HANDLER Vector120 +#define STM32_DMA2_CH1_HANDLER Vector124 +#define STM32_DMA2_CH2_HANDLER Vector128 +#define STM32_DMA2_CH3_HANDLER Vector12C +#define STM32_DMA2_CH4_HANDLER Vector130 +#define STM32_DMA2_CH5_HANDLER Vector150 +#define STM32_DMA2_CH6_HANDLER Vector154 +#define STM32_DMA2_CH7_HANDLER Vector158 +#define STM32_DMA2_CH0_NUMBER 56 +#define STM32_DMA2_CH1_NUMBER 57 +#define STM32_DMA2_CH2_NUMBER 58 +#define STM32_DMA2_CH3_NUMBER 59 +#define STM32_DMA2_CH4_NUMBER 60 +#define STM32_DMA2_CH5_NUMBER 68 +#define STM32_DMA2_CH6_NUMBER 69 +#define STM32_DMA2_CH7_NUMBER 70 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 23 +#define STM32_EXTI_IMR_MASK 0x00000000U + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ + RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | \ + RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN | \ + RCC_AHB1ENR_GPIOHEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 + +#define STM32_HAS_I2C4 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE +#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SDC_SDIO_DMA_CHN 0x04004000 + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_SPI4_RX_DMA_CHN 0x00005004 +#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI4_TX_DMA_CHN 0x00050040 + +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE +#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI5_RX_DMA_CHN 0x00702000 +#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SPI5_TX_DMA_CHN 0x07020000 + +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 4 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM9 TRUE +#define STM32_TIM9_IS_32BITS FALSE +#define STM32_TIM9_CHANNELS 2 + +#define STM32_HAS_TIM10 TRUE +#define STM32_TIM10_IS_32BITS FALSE +#define STM32_TIM10_CHANNELS 1 + +#define STM32_HAS_TIM11 TRUE +#define STM32_TIM11_IS_32BITS FALSE +#define STM32_TIM11_CHANNELS 1 + +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_OTG_STEPPING 1 +#define STM32_HAS_OTG1 TRUE +#define STM32_OTG1_ENDPOINTS 4 + +#define STM32_HAS_OTG2 FALSE +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED FALSE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE FALSE + +#endif /* defined(STM32F411xx) */ + +/*===========================================================================*/ +/* STM32F410Cx, STM32F410Rx. */ +/*===========================================================================*/ + +#if defined(STM32F410xx) + +/* ADC attributes.*/ +#define STM32_ADC_HANDLER Vector88 +#define STM32_ADC_NUMBER 18 + +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_HAS_CAN3 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_DAC1_CH1_DMA_CHN 0x00700000 + +#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_CACHE_HANDLING FALSE + +#define STM32_HAS_DMA1 TRUE +#define STM32_DMA1_CH0_HANDLER Vector6C +#define STM32_DMA1_CH1_HANDLER Vector70 +#define STM32_DMA1_CH2_HANDLER Vector74 +#define STM32_DMA1_CH3_HANDLER Vector78 +#define STM32_DMA1_CH4_HANDLER Vector7C +#define STM32_DMA1_CH5_HANDLER Vector80 +#define STM32_DMA1_CH6_HANDLER Vector84 +#define STM32_DMA1_CH7_HANDLER VectorFC +#define STM32_DMA1_CH0_NUMBER 11 +#define STM32_DMA1_CH1_NUMBER 12 +#define STM32_DMA1_CH2_NUMBER 13 +#define STM32_DMA1_CH3_NUMBER 14 +#define STM32_DMA1_CH4_NUMBER 15 +#define STM32_DMA1_CH5_NUMBER 16 +#define STM32_DMA1_CH6_NUMBER 17 +#define STM32_DMA1_CH7_NUMBER 47 + +#define STM32_HAS_DMA2 TRUE +#define STM32_DMA2_CH0_HANDLER Vector120 +#define STM32_DMA2_CH1_HANDLER Vector124 +#define STM32_DMA2_CH2_HANDLER Vector128 +#define STM32_DMA2_CH3_HANDLER Vector12C +#define STM32_DMA2_CH4_HANDLER Vector130 +#define STM32_DMA2_CH5_HANDLER Vector150 +#define STM32_DMA2_CH6_HANDLER Vector154 +#define STM32_DMA2_CH7_HANDLER Vector158 +#define STM32_DMA2_CH0_NUMBER 56 +#define STM32_DMA2_CH1_NUMBER 57 +#define STM32_DMA2_CH2_NUMBER 58 +#define STM32_DMA2_CH3_NUMBER 59 +#define STM32_DMA2_CH4_NUMBER 60 +#define STM32_DMA2_CH5_NUMBER 68 +#define STM32_DMA2_CH6_NUMBER 69 +#define STM32_DMA2_CH7_NUMBER 70 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 23 +#define STM32_EXTI_IMR_MASK 0x00000000U + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD FALSE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ + RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | \ + RCC_AHB1ENR_GPIOHEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 FALSE + +#define STM32_HAS_I2C4 FALSE +#define STM32_I2C4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0)) |\ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C4_RX_DMA_CHN 0x00002007 +#define STM32_I2C4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) |\ + STM32_DMA_STREAM_ID_MSK(1, 1)) +#define STM32_I2C4_TX_DMA_CHN 0x00040020 + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_SPI1_TX_DMA_CHN 0x00003200 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S TRUE +#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI5_RX_DMA_CHN 0x00702000 +#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SPI5_TX_DMA_CHN 0x07020000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 4 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM9 TRUE +#define STM32_TIM9_IS_32BITS FALSE +#define STM32_TIM9_CHANNELS 2 + +#define STM32_HAS_TIM11 TRUE +#define STM32_TIM11_IS_32BITS FALSE +#define STM32_TIM11_CHANNELS 1 + +#define STM32_HAS_TIM2 FALSE +#define STM32_HAS_TIM3 FALSE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_RX_DMA_CHN 0x60400000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED FALSE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE FALSE + +#endif /* defined(STM32F410xx) */ + /*===========================================================================*/ /* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx */ /* STM32F215xx, STM32F207xx, STM32F217xx. */ /*===========================================================================*/ + #if defined(STM32F40_41xxx) || defined(STM32F2XX) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -797,6 +2085,7 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 TRUE +#define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -911,6 +2200,9 @@ #define STM32_HAS_I2C4 FALSE +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #if !defined(STM32F2XX) @@ -1001,11 +2293,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -1013,11 +2305,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE @@ -1105,7 +2397,9 @@ /*===========================================================================*/ /* STM32F401xx. */ /*===========================================================================*/ + #if defined(STM32F401xx) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -1134,6 +2428,7 @@ /* CAN attributes.*/ #define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 TRUE +#define STM32_HAS_CAN3 FALSE #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ @@ -1231,6 +2526,9 @@ #define STM32_HAS_I2C4 FALSE +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE @@ -1313,11 +2611,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM6 FALSE #define STM32_HAS_TIM7 FALSE @@ -1390,297 +2688,8 @@ #define STM32_CRC_PROGRAMMABLE FALSE #endif /* defined(STM32F401xx) */ - -/*===========================================================================*/ -/* STM32F411xE. */ -/*===========================================================================*/ -#if defined(STM32F411xx) -/* ADC attributes.*/ -#define STM32_ADC_HANDLER Vector88 -#define STM32_ADC_NUMBER 18 - -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -#define STM32_HAS_SDADC1 FALSE -#define STM32_HAS_SDADC2 FALSE -#define STM32_HAS_SDADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE - -/* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 FALSE -#define STM32_HAS_DAC1_CH2 FALSE -#define STM32_HAS_DAC2_CH1 FALSE -#define STM32_HAS_DAC2_CH2 FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA TRUE -#define STM32_DMA_CACHE_HANDLING FALSE - -#define STM32_HAS_DMA1 TRUE -#define STM32_DMA1_CH0_HANDLER Vector6C -#define STM32_DMA1_CH1_HANDLER Vector70 -#define STM32_DMA1_CH2_HANDLER Vector74 -#define STM32_DMA1_CH3_HANDLER Vector78 -#define STM32_DMA1_CH4_HANDLER Vector7C -#define STM32_DMA1_CH5_HANDLER Vector80 -#define STM32_DMA1_CH6_HANDLER Vector84 -#define STM32_DMA1_CH7_HANDLER VectorFC -#define STM32_DMA1_CH0_NUMBER 11 -#define STM32_DMA1_CH1_NUMBER 12 -#define STM32_DMA1_CH2_NUMBER 13 -#define STM32_DMA1_CH3_NUMBER 14 -#define STM32_DMA1_CH4_NUMBER 15 -#define STM32_DMA1_CH5_NUMBER 16 -#define STM32_DMA1_CH6_NUMBER 17 -#define STM32_DMA1_CH7_NUMBER 47 - -#define STM32_HAS_DMA2 TRUE -#define STM32_DMA2_CH0_HANDLER Vector120 -#define STM32_DMA2_CH1_HANDLER Vector124 -#define STM32_DMA2_CH2_HANDLER Vector128 -#define STM32_DMA2_CH3_HANDLER Vector12C -#define STM32_DMA2_CH4_HANDLER Vector130 -#define STM32_DMA2_CH5_HANDLER Vector150 -#define STM32_DMA2_CH6_HANDLER Vector154 -#define STM32_DMA2_CH7_HANDLER Vector158 -#define STM32_DMA2_CH0_NUMBER 56 -#define STM32_DMA2_CH1_NUMBER 57 -#define STM32_DMA2_CH2_NUMBER 58 -#define STM32_DMA2_CH3_NUMBER 59 -#define STM32_DMA2_CH4_NUMBER 60 -#define STM32_DMA2_CH5_NUMBER 68 -#define STM32_DMA2_CH6_NUMBER 69 -#define STM32_DMA2_CH7_NUMBER 70 - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 23 -#define STM32_EXTI_IMR_MASK 0x00000000U - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOH TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOI FALSE -#define STM32_HAS_GPIOJ FALSE -#define STM32_HAS_GPIOK FALSE -#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ - RCC_AHB1ENR_GPIOBEN | \ - RCC_AHB1ENR_GPIOCEN | \ - RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN | \ - RCC_AHB1ENR_GPIOHEN) - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C1_RX_DMA_CHN 0x00100001 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x11000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C2_RX_DMA_CHN 0x00007700 -#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_I2C2_TX_DMA_CHN 0x70000000 - -#define STM32_HAS_I2C3 TRUE -#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_I2C3_RX_DMA_CHN 0x00000300 -#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C3_TX_DMA_CHN 0x00030000 - -#define STM32_HAS_I2C4 FALSE - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS TRUE -#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE -#define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE -#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SDC_SDIO_DMA_CHN 0x04004000 - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE -#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_SPI1_RX_DMA_CHN 0x00000303 -#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI1_TX_DMA_CHN 0x00303000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE -#define STM32_SPI2_I2S_FULLDUPLEX TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_SUPPORTS_I2S TRUE -#define STM32_SPI3_I2S_FULLDUPLEX TRUE -#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_SUPPORTS_I2S FALSE -#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_SPI4_RX_DMA_CHN 0x00005004 -#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_SPI4_TX_DMA_CHN 0x00050040 - -#define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_SUPPORTS_I2S FALSE -#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI5_RX_DMA_CHN 0x00702000 -#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SPI5_TX_DMA_CHN 0x07020000 - -#define STM32_HAS_SPI6 FALSE - -/* TIM attributes.*/ -#define STM32_TIM_MAX_CHANNELS 4 - -#define STM32_HAS_TIM1 TRUE -#define STM32_TIM1_IS_32BITS FALSE -#define STM32_TIM1_CHANNELS 4 - -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - -#define STM32_HAS_TIM3 TRUE -#define STM32_TIM3_IS_32BITS FALSE -#define STM32_TIM3_CHANNELS 4 - -#define STM32_HAS_TIM4 TRUE -#define STM32_TIM4_IS_32BITS FALSE -#define STM32_TIM4_CHANNELS 4 - -#define STM32_HAS_TIM5 TRUE -#define STM32_TIM5_IS_32BITS TRUE -#define STM32_TIM5_CHANNELS 4 - -#define STM32_HAS_TIM9 TRUE -#define STM32_TIM9_IS_32BITS FALSE -#define STM32_TIM9_CHANNELS 2 - -#define STM32_HAS_TIM10 TRUE -#define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 - -#define STM32_HAS_TIM11 TRUE -#define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 - -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE -#define STM32_HAS_TIM20 FALSE -#define STM32_HAS_TIM21 FALSE -#define STM32_HAS_TIM22 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00400400 -#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) -#define STM32_USART1_TX_DMA_CHN 0x40000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_USART2_RX_DMA_CHN 0x00400000 -#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_USART2_TX_DMA_CHN 0x04000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE - -#define STM32_HAS_USART6 TRUE -#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 2)) -#define STM32_USART6_RX_DMA_CHN 0x00000550 -#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ - STM32_DMA_STREAM_ID_MSK(2, 7)) -#define STM32_USART6_TX_DMA_CHN 0x55000000 - -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE -#define STM32_HAS_LPUART1 FALSE - -/* USB attributes.*/ -#define STM32_OTG_STEPPING 1 -#define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 4 - -#define STM32_HAS_OTG2 FALSE -#define STM32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define STM32_HAS_IWDG TRUE -#define STM32_IWDG_IS_WINDOWED FALSE - -/* LTDC attributes.*/ -#define STM32_HAS_LTDC FALSE - -/* DMA2D attributes.*/ -#define STM32_HAS_DMA2D FALSE - -/* FSMC attributes.*/ -#define STM32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(STM32F411xx) */ /** @} */ -#endif /* _STM32_REGISTRY_H_ */ +#endif /* STM32_REGISTRY_H */ /** @} */