EXT support for STM32F7xx.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8163 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio
parent
4fda1c3f30
commit
0f926c98c2
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@ -280,18 +280,33 @@
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_USE_SPI4 FALSE
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#define STM32_SPI_USE_SPI5 FALSE
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#define STM32_SPI_USE_SPI6 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
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#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_SPI4_IRQ_PRIORITY 10
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#define STM32_SPI_SPI5_IRQ_PRIORITY 10
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#define STM32_SPI_SPI6_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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@ -0,0 +1,375 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F7xx/ext_lld_isr.c
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* @brief STM32F7xx EXT subsystem low level driver ISR code.
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*
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* @addtogroup EXT
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_EXT || defined(__DOXYGEN__)
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#include "ext_lld_isr.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/**
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* @brief EXTI[0] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector58) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 0);
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EXTI->PR = pr;
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if (pr & (1 << 0))
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EXTD1.config->channels[0].cb(&EXTD1, 0);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[1] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector5C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 1);
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EXTI->PR = pr;
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if (pr & (1 << 1))
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EXTD1.config->channels[1].cb(&EXTD1, 1);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[2] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector60) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 2);
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EXTI->PR = pr;
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if (pr & (1 << 2))
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EXTD1.config->channels[2].cb(&EXTD1, 2);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[3] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector64) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 3);
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EXTI->PR = pr;
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if (pr & (1 << 3))
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EXTD1.config->channels[3].cb(&EXTD1, 3);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[4] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector68) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 4);
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EXTI->PR = pr;
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if (pr & (1 << 4))
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EXTD1.config->channels[4].cb(&EXTD1, 4);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[5]...EXTI[9] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector9C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) |
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(1 << 9));
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EXTI->PR = pr;
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if (pr & (1 << 5))
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EXTD1.config->channels[5].cb(&EXTD1, 5);
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if (pr & (1 << 6))
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EXTD1.config->channels[6].cb(&EXTD1, 6);
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if (pr & (1 << 7))
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EXTD1.config->channels[7].cb(&EXTD1, 7);
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if (pr & (1 << 8))
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EXTD1.config->channels[8].cb(&EXTD1, 8);
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if (pr & (1 << 9))
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EXTD1.config->channels[9].cb(&EXTD1, 9);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[10]...EXTI[15] interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorE0) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) |
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(1 << 14) | (1 << 15));
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EXTI->PR = pr;
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if (pr & (1 << 10))
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EXTD1.config->channels[10].cb(&EXTD1, 10);
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if (pr & (1 << 11))
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EXTD1.config->channels[11].cb(&EXTD1, 11);
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if (pr & (1 << 12))
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EXTD1.config->channels[12].cb(&EXTD1, 12);
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if (pr & (1 << 13))
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EXTD1.config->channels[13].cb(&EXTD1, 13);
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if (pr & (1 << 14))
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EXTD1.config->channels[14].cb(&EXTD1, 14);
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if (pr & (1 << 15))
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EXTD1.config->channels[15].cb(&EXTD1, 15);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[16] interrupt handler (PVD).
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector44) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 16);
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EXTI->PR = pr;
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if (pr & (1 << 16))
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EXTD1.config->channels[16].cb(&EXTD1, 16);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[17] interrupt handler (RTC_ALARM).
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorE4) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 17);
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EXTI->PR = pr;
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if (pr & (1 << 17))
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EXTD1.config->channels[17].cb(&EXTD1, 17);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorE8) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 18);
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EXTI->PR = pr;
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if (pr & (1 << 18))
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EXTD1.config->channels[18].cb(&EXTD1, 18);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[19] interrupt handler (ETH_WKUP).
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector138) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 19);
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EXTI->PR = pr;
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if (pr & (1 << 19))
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EXTD1.config->channels[19].cb(&EXTD1, 19);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[20] interrupt handler (OTG_HS_WKUP).
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector170) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 20);
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EXTI->PR = pr;
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if (pr & (1 << 20))
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EXTD1.config->channels[20].cb(&EXTD1, 20);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[21] interrupt handler (TAMPER_STAMP).
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector48) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 21);
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EXTI->PR = pr;
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if (pr & (1 << 21))
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EXTD1.config->channels[21].cb(&EXTD1, 21);
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief EXTI[22] interrupt handler (RTC_WKUP).
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(Vector4C) {
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uint32_t pr;
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OSAL_IRQ_PROLOGUE();
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pr = EXTI->PR & EXTI->IMR & (1 << 22);
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EXTI->PR = pr;
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if (pr & (1 << 22))
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EXTD1.config->channels[22].cb(&EXTD1, 22);
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OSAL_IRQ_EPILOGUE();
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}
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Enables EXTI IRQ sources.
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*
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* @notapi
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*/
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void ext_lld_exti_irq_enable(void) {
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nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
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nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
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nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
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nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
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nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
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nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
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nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
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nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
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nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
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nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
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nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
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nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
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nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY);
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nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY);
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}
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/**
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* @brief Disables EXTI IRQ sources.
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*
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* @notapi
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*/
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void ext_lld_exti_irq_disable(void) {
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nvicDisableVector(EXTI0_IRQn);
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nvicDisableVector(EXTI1_IRQn);
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nvicDisableVector(EXTI2_IRQn);
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nvicDisableVector(EXTI3_IRQn);
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nvicDisableVector(EXTI4_IRQn);
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nvicDisableVector(EXTI9_5_IRQn);
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nvicDisableVector(EXTI15_10_IRQn);
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nvicDisableVector(PVD_IRQn);
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nvicDisableVector(RTC_Alarm_IRQn);
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nvicDisableVector(OTG_FS_WKUP_IRQn);
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nvicDisableVector(ETH_WKUP_IRQn);
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nvicDisableVector(OTG_HS_WKUP_IRQn);
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nvicDisableVector(TAMP_STAMP_IRQn);
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nvicDisableVector(RTC_WKUP_IRQn);
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}
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#endif /* HAL_USE_EXT */
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/** @} */
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@ -0,0 +1,170 @@
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
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|
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http://www.apache.org/licenses/LICENSE-2.0
|
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|
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Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
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limitations under the License.
|
||||
*/
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/**
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* @file STM32F7xx/ext_lld_isr.h
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* @brief STM32F7xx EXT subsystem low level driver ISR header.
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*
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* @addtogroup EXT
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* @{
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*/
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#ifndef _EXT_LLD_ISR_H_
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#define _EXT_LLD_ISR_H_
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#if HAL_USE_EXT || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief EXTI0 interrupt priority level setting.
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*/
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#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
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#endif
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/**
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* @brief EXTI1 interrupt priority level setting.
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*/
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#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
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#endif
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/**
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* @brief EXTI2 interrupt priority level setting.
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*/
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#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
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#endif
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/**
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* @brief EXTI3 interrupt priority level setting.
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||||
*/
|
||||
#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI4 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI9..5 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI15..10 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI16 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI17 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI18 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI19 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI20 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI21 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI21_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI22 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI22_IRQ_PRIORITY 6
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void ext_lld_exti_irq_enable(void);
|
||||
void ext_lld_exti_irq_disable(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_EXT */
|
||||
|
||||
#endif /* _EXT_LLD_ISR_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -143,7 +143,8 @@
|
|||
#define STM32_ETH_NUMBER 61
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 23
|
||||
#define STM32_EXTI_NUM_LINES 23
|
||||
#define STM32_EXTI_IMR_MASK 0
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
|
|
|
|||
Loading…
Reference in New Issue